会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明授权
    • Method and opportunistic sensing
    • 方法和机会主义感知
    • US09525669B2
    • 2016-12-20
    • US14440885
    • 2013-12-05
    • ST-Ericsson SA
    • Ulf BjorkengrenAndreas AnyuruBenn PorsckePatrik RydMats FagerstromMats Bergstrom
    • H04L29/06H04L9/32H04W4/04
    • H04L63/0428H04L9/3242H04L63/0421H04L63/062H04L2209/24H04W4/043
    • A method in a first device for anonymously delivering data to a part that has initiated a task is provided. The first device and the part initiating a task are participants in opportunistic sensing. The method comprises creating a data sample and encrypting the data sample with a public key of the task initiating part. After communicating the protected sample to one or more intermediate devices, one of the one or more intermediate devices delivers the protected sample to the task initiating part, such that the task initiating part does not know the identity of the first device. The task initiating device only know the identity of the one of the one or more intermediate devices that delivered the protected sample to the task initiating part, wherein the intermediate devices are participants in the opportunistic sensing.
    • 提供了一种用于向已经发起任务的部分匿名传递数据的第一设备中的方法。 第一个设备和启动任务的部分是机会感知的参与者。 该方法包括使用任务启动部分的公钥创建数据样本并加密数据样本。 在将受保护的样本传送到一个或多个中间设备之后,一个或多个中间设备之一将受保护的样本传送到任务启动部分,使得任务启动部分不知道第一设备的身份。 任务启动设备仅知道将受保护样本传递到任务启动部分的一个或多个中间设备之一的身份,其中中间设备是机会感知中的参与者。
    • 4. 发明申请
    • Presence and Operability Test of a Decoupling Capacitor
    • 去耦电容器的存在和可操作性测试
    • US20160274173A1
    • 2016-09-22
    • US15076146
    • 2016-03-21
    • ST-Ericsson SA
    • Christophe Belet
    • G01R31/02G05F1/46G01R19/04
    • G01R31/028G01R19/04G01R31/40G05F1/46G05F1/56
    • Electronic device (101) comprising a power source (110), a power management unit (102) coupled to the power source, and a set of loads (103a,103b, 103c,103d), the power management unit comprising a set of voltage regulators blocks (104a,104b, 104c,104d), each voltage regulator block being respectively coupled to an associated load of the set of loads for allowing power transfer from the power source to the load. The electronic device comprises a spike detector block (106), coupled to each of the voltage regulator blocks, and configured to detect a spike in a voltage signal from a voltage regulator block for testing the presence and the operability of a decoupling capacitor (Ca, Cb, Cc, Cd) between an output of the voltage regulator block and an input of the associated load.
    • 电子设备(101),包括电源(110),耦合到电源的电源管理单元(102)和一组负载(103a,103b,103c,103d),所述电源管理单元包括一组电压 调节器块(104a,104b,104c,104d),每个电压调节器块分别耦合到该组负载的相关负载,以允许从电源到负载的电力传输。 电子设备包括尖峰检测器块(106),其耦合到每个电压调节器块,并且被配置为检测来自电压调节器块的电压信号中的尖峰,用于测试去耦电容器(Ca, Cb,Cc,Cd)在调压器块的输出和相关负载的输入之间。
    • 5. 发明授权
    • Step-up/step-down voltage converter having low output ripple
    • 具有低输出纹波的升压/降压型电压转换器
    • US09444329B2
    • 2016-09-13
    • US14000512
    • 2012-02-20
    • Patrik Arno
    • Patrik Arno
    • H02M3/02H02M3/158H02M3/07
    • H02M3/02H02M3/07H02M3/1584H02M2003/072
    • A voltage converter device converts an input signal having a given input voltage value into an output signal having an output voltage different from the input voltage. The device comprises a main module, arranged between an input terminal and a first circuit node, The device is adapted to output at the first circuit node a pulse-width-modulated signal switching between a first voltage value and a second voltage value, defining a switching range, by switching successively between a first mode of operation and a second mode of operation. The switching range of the pulse width modulation has an amplitude, calculated as the absolute difference between the first and the second voltage value, inferior or equal to half the input voltage.
    • 电压转换器装置将具有给定输入电压值的输入信号转换成具有不同于输入电压的输出电压的输出信号。 该装置包括布置在输入端和第一电路节点之间的主模块。该装置适于在第一电路节点处输出在第一电压值和第二电压值之间切换的脉冲宽度调制信号, 切换范围,通过在第一操作模式和第二操作模式之间连续切换。 脉冲宽度调制的切换范围具有作为第一和第二电压值之间的绝对差计算的振幅,等于或等于输入电压的一半。
    • 6. 发明授权
    • Regulating the activity of a core
    • 调节核心的活动
    • US09442552B2
    • 2016-09-13
    • US14343175
    • 2012-09-06
    • Gilles RiesAbdelaziz Goulahsen
    • Gilles RiesAbdelaziz Goulahsen
    • G06F1/26G06F1/32G06F1/20G06F11/00
    • G06F1/3206G06F1/206G06F1/324G06F1/3296G06F11/00Y02D10/126
    • It is proposed a method for regulating the activity of a core running at a given clock rate. The method comprises: monitoring (S100) a value of a parameter of the core, the parameter being a critical parameter for a safe operating of the core; determining whether the monitored value reaches a trigger value; when the monitored value reaches the trigger value (S120): modifying the clock rate of the core (S130) by decreasing the ratio of active cycles of the clock; and running the core at the clock rate modified (S140) by decreasing the ratio of active cycles of the clock; when the monitored value reaches a second time the trigger value (S170): modifying the clock rate of the core (S180) by increasing the ratio of active cycles of the clock; and running the core at the clock rate (S190) modified by increasing the ratio of active cycles of the clock.
    • 提出了一种用于调节以给定时钟速率运行的核的活动的方法。 该方法包括:监视(S100)核心参数的值,该参数是核心安全运行的关键参数; 确定所监视的值是否达到触发值; 当监视值达到触发值时(S120):通过减小时钟的有效周期的比例来修改核心的时钟速率(S130); 并通过降低时钟的有效周期的比例,以修改的时钟速率(S140)运行核心; 当监视值达到第二次触发值时(S170):通过增加时钟的有效周期的比例来修改核心的时钟速率(S180); 并通过增加时钟的有效周期比例,以时钟速率(S190)运行核心。
    • 8. 发明授权
    • CPU current ripple and OCV effect mitigation
    • CPU电流纹波和OCV效应减轻
    • US09429981B2
    • 2016-08-30
    • US13784909
    • 2013-03-05
    • ST-Ericsson SA
    • Håkan Persson
    • G06F1/04G06F1/06G06F1/10G06F1/32
    • G06F1/06G06F1/10G06F1/3203G06F1/3243Y02D10/152
    • High frequency current transients, due to logic switching inside the CPU, are reduced by applying clock signals having different relative phases to different parts of the CPU. This reduces the amplitude of current variations, and hence noise induced onto the power supply voltage. In some embodiments, different CPU cores within multi-core CPUs are clocked with a different clock phases. Additionally a method and circuit for low-latency communication in the presence of large OCV effects is provided. The low-latency communication may be based on a FIFO. Strobes are used to indicate safe points in time to update and read signals between transmitter and receiver. The strobes are generated in a central clock generation module. The strobe mechanism is used to transfer the read and write pointers between the transmitter and receiver, while the payload data is transferred using a FIFO data array that allows data writes to be asynchronous to corresponding data reads.
    • 通过将具有不同相对相位的时钟信号施加到CPU的不同部分,由于CPU内部的逻辑切换引起的高频电流瞬变被减少。 这降低了电流变化的幅度,并因此降低了对电源电压的感应。 在一些实施例中,多核CPU内的不同CPU内核以不同的时钟相位计时。 另外,提供了在存在大的OCV效应的情况下用于低等待时间通信的方法和电路。 低延迟通信可以基于FIFO。 标记用于指示安全点在更新和读取发射机和接收机之间的信号。 选通在中央时钟发生模块中产生。 选通机制用于在发送器和接收器之间传送读取和写入指针,同时使用允许数据写入与相应数据读取异步的FIFO数据数据传输有效载荷数据。
    • 10. 发明授权
    • DC/DC converter having a step-up converter supplying a step-down converter
    • DC / DC转换器具有提供降压转换器的升压转换器
    • US09413242B2
    • 2016-08-09
    • US14363056
    • 2012-12-05
    • ST-Ericsson SA
    • Patrik Arno
    • H02M3/158H02M3/335H02M1/00
    • H02M3/1582H02M3/33569H02M2001/007
    • A DC-DC converter has a Step-Up stage connected to a Step-Down stage. A common Step-Down controller is designed and configured such that a single reference voltage is compared to the output voltage of the Step-Down stage by a single comparator, producing a single error signal. The error signal is then compared to two different saw signals to generate first and second pulse-width modulated signals respectively. The first and second pulse-width modulated signals are inputted to a control unit that generates a first pair of control signals and a second pair of control signals, which control switching of the Step-Up stage and of the Step-Down stage.
    • DC-DC转换器具有连接到降压级的升压级。 设计并配置了一个通用的降压控制器,使得单个参考电压由单个比较器与降压级的输出电压进行比较,产生单个误差信号。 然后将误差信号与两个不同的锯信号进行比较,以分别产生第一和第二脉冲宽度调制信号。 第一和第二脉冲宽度调制信号被输入到产生第一对控制信号的控制单元和控制升压阶段和降压阶段的切换的第二对控制信号。