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    • 2. 发明授权
    • Dynamic gate drive voltage adjustment
    • 动态门极驱动电压调节
    • US07701189B2
    • 2010-04-20
    • US12105121
    • 2008-04-17
    • Dirk Gehrke
    • Dirk Gehrke
    • G05F1/00
    • H02M3/1588H02M2001/0019H02M2001/0048Y02B70/1466Y02B70/1491
    • A DC-DC buck converter comprises a high-side power FET having a current path connected in series between an input terminal and an inductor connected to an output terminal supplying an output current to a load. The converter further comprises a low-side power FET having a current path connected between a reference terminal and an interconnection node of the high-side power FET with the inductor. The converter has a pulse width modulation controller receiving a feedback signal from the output terminal and providing pulse width modulated signals, and a gate driver circuit that receives the pulse width modulated signals from the pulse width modulation controller and applies pulse width modulated drive signals to the gates of the power FETs. The gate driver circuit supplies the drive signals to the gates of the power FETs at a variable voltage level adjusted in response to at least the output current, minimizing the power dissipation of the gate driver circuit.
    • DC-DC降压转换器包括具有串联连接在输入端子和连接到向负载提供输出电流的输出端子的电感器之间的电感器的高边功率FET。 该转换器还包括具有连接在具有电感器的高侧功率FET的参考端子和互连节点之间的电流通路的低端功率FET。 该转换器具有接收来自输出端子的反馈信号并提供脉冲宽度调制信号的脉冲宽度调制控制器以及从脉冲宽度调制控制器接收脉冲宽度调制信号的栅极驱动器电路,并将脉冲宽度调制驱动信号施加到 功率FET的栅极。 栅极驱动器电路以至少响应于输出电流调节的可变电压电平将功率FET的栅极提供给功率FET的栅极,从而最小化栅极驱动器电路的功率消耗。
    • 4. 发明授权
    • High precision power-on-reset circuit with an adjustable trigger level
    • 具有可调触发电平的高精度上电复位电路
    • US07847606B2
    • 2010-12-07
    • US12413193
    • 2009-03-27
    • Ingo HehemannKwet ChaiMichael Wendt
    • Ingo HehemannKwet ChaiMichael Wendt
    • H03L7/00
    • H03K17/223
    • An electronic device comprising circuitry for providing a Power-on-Reset (POR) signal as a function of a supply voltage level of the circuitry. The circuitry comprises a Vbe-cell or a Vgs-cell comprising a first current path including a first transistor and a second current path including a second transistor. Each transistor has a control terminal for controlling a first current in the first current path and a second current in the second current path, wherein a control voltage level is commonly applied to the control terminals of the first and the second transistor. The control voltage level is derived from the current supply voltage level of the circuitry, and the circuitry further comprises a POR output node for providing a POR output signal, which changes from a first state to a second state in response to the ratio of the magnitudes of the first current and the second current.
    • 一种电子设备,包括用于提供作为电路的电源电压电平的函数的上电复位(POR)信号的电路。 电路包括Vbe单元或Vgs单元,其包括包括第一晶体管的第一电流路径和包括第二晶体管的第二电流路径。 每个晶体管具有用于控制第一电流路径中的第一电流和第二电流路径中的第二电流的控制端子,其中通常将控制电压电平施加到第一和第二晶体管的控制端子。 控制电压电平由电路的当前电源电压电平得出,并且电路还包括用于提供POR输出信号的POR输出节点,POR输出信号响应于第一状态与第二状态的比值而从第一状态改变到第二状态 的第一个当前和第二个电流。
    • 5. 发明授权
    • Phase locked loop with two-step control
    • 具有两步控制的锁相环
    • US07724093B2
    • 2010-05-25
    • US12139291
    • 2008-06-13
    • Alexander WormerHarald Sandner
    • Alexander WormerHarald Sandner
    • H03L7/085H03L7/089H03L7/099
    • H03L7/113H03L7/087H03L7/089H03L7/093H03L7/0991H03L7/18H03L2207/50
    • A phase locked loop has a digitally controlled oscillator (DCO) for generating a DCO output signal (fOSC), a clock divider coupled to the DCO and receiving the DCO output signal and outputting a feedback clock signal (fN), and a phase frequency detector (PFD) coupled to the DCO and controlling the DCO by a DCO control signal (dCNTL). The PFD has a first input for receiving the feedback clock signal (fN), a second input for receiving a reference clock signal (fREF), and comprises a frequency detection stage (FD) adapted to calculate a frequency difference between the feedback clock signal (fN) and the reference clock signal (fREF) in a frequency detection mode and to adjust the DCO control signal based on said frequency difference, a phase detection (PD) stage for calculating a phase error between the feedback clock signal and the reference clock signal in a phase detection mode, and a switch for switching between the frequency detection mode and the phase detection mode upon the frequency of the feedback clock signal reaching a predetermined value.
    • 锁相环具有用于产生DCO输出信号(fOSC)的数字控制振荡器(DCO),耦合到DCO并接收DCO输出信号并输出​​反馈时钟信号(fN)的时钟分频器,以及相位频率检测器 (PFD)耦合到DCO并通过DCO控制信号(dCNTL)控制DCO。 PFD具有用于接收反馈时钟信号(fN)的第一输入端,用于接收基准时钟信号(fREF)的第二输入端,并且包括频率检测级(FD),该频率检测级适于计算反馈时钟信号 fN)和参考时钟信号(fREF),并且基于所述频率差调整DCO控制信号;相位检测(PD)级,用于计算反馈时钟信号和参考时钟信号之间的相位误差 在相位检测模式中,以及用于在反馈时钟信号的频率达到预定值时在频率检测模式和相位检测模式之间切换的开关。
    • 6. 发明授权
    • ADC with low-power sampling
    • ADC采用低功耗采样
    • US07944387B2
    • 2011-05-17
    • US12687703
    • 2010-01-14
    • Frank OhnhaeuserAndreas Wickmann
    • Frank OhnhaeuserAndreas Wickmann
    • H03M1/12
    • H03M1/002H03M1/0682H03M1/468H03M1/804
    • An apparatus for analog-to-digital conversion using successive approximation is provided, which is adapted to be supplied with a single ended supply voltage. The device includes: a first analog-to-digital conversion stage including a first set of capacitors coupled with a side at a common node and adapted to sample an input voltage and to be coupled to either a first reference voltage level or a second reference voltage level, at least one capacitor of the first set of capacitors being adapted to be left floating, a control stage being adapted to connect the at least one floating capacitor to the first reference voltage level or the second reference voltage level in response to an analog-to-digital conversion decision made by a second analog-to-digital conversion stage. The first analog-to-digital conversion stage is operable to couple the common node to a supply voltage level, in particular ground, during analog-to-digital conversion.
    • 提供了使用逐次逼近的用于模数转换的装置,其适于提供单端电源电压。 该器件包括:第一模数转换级,其包括与公共节点的一侧耦合的第一组电容器,并且适于对输入电压进行采样并耦合到第一参考电压电平或第二参考电压 所述第一组电容器中的至少一个电容适于悬浮,控制级适于将所述至少一个浮动电容器响应于模拟量电平连接到所述第一参考电压电平或所述第二参考电压电平, 通过第二模数转换级进行数模转换决定。 在模数转换期间,第一模数转换级用于将公共节点耦合到电源电压电平,特别是地。
    • 8. 发明授权
    • Resistor network for programmable transconductance stage
    • 用于可编程跨导级的电阻网络
    • US07843261B2
    • 2010-11-30
    • US12338571
    • 2008-12-18
    • Viola Schaffer
    • Viola Schaffer
    • H03F1/34
    • H03G1/0088
    • A voltage-to-current converter is provided. The voltage-to-current converter comprises an amplifier, a resistor network, an R-2R network, and switches. The amplifier has a first input node (which is an input signal), a second input node, and an output node. The resistor network is coupled to the output node of the amplifier, includes a plurality of resistors coupled in series with on another, and includes a plurality of first tap nodes. The R-2R network is coupled to the resistor network and includes a plurality of second tap nodes. Additionally, at least one switch is coupled between the second input node of the amplifier and each first tap node, and at least one switch is coupled between the second input node of the amplifier and each of the second tap nodes.
    • 提供一个电压 - 电流转换器。 电压 - 电流转换器包括放大器,电阻网络,R-2R网络和开关。 放大器具有第一输入节点(其是输入信号),第二输入节点和输出节点。 电阻器网络耦合到放大器的输出节点,包括与另一个串联耦合的多个电阻器,并且包括多个第一抽头节点。 R-2R网络耦合到电阻网络并且包括多个第二抽头节点。 另外,至少一个开关耦合在放大器的第二输入节点和每个第一抽头节点之间,并且至少一个开关耦合在放大器的第二输入节点和每个第二抽头节点之间。