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1. 发明授权

US09871529B1 Asynchronous SAR ADC with conversion speed control feedback loop 有权
公开(公告)号：US09871529B1
公开(公告)日：2018-01-16
申请号：US15425653
申请日：2017-02-06
申请人： Euhan Chong , Semyon Lebedev , Marc-Andre LaCroix
发明人： Euhan Chong , Semyon Lebedev , Marc-Andre LaCroix
IPC分类号： H03M1/38 , H03M1/12 , H03M1/00 , H03M1/06
CPC分类号： H03M1/38 , H03M1/00 , H03M1/0695 , H03M1/12 , H03M1/121 , H03M1/125
摘要： Systems and circuits for feedback control of an asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) are described. An example system includes the asynchronous SAR ADC. A timing detector circuit is coupled to the asynchronous SAR ADC to receive one or more internal signals from the asynchronous SAR ADC. The timing detector circuit outputs a timing detector signal representing an internal timing of the SAR ADC. The timing detector signal is generated based on the one or more internal signals. A regulator circuit is coupled to the timing detector circuit to receive the timing detector signal. The regulator circuit is also coupled to the asynchronous SAR ADC to output a feedback signal to the asynchronous SAR ADC. The feedback signal is generated based on the timing detector signal to control the internal timing of the SAR ADC to match a target timing.

2. 发明授权

US10776234B2 On-die input capacitive divider for wireline receivers with integrated loopback 有权
公开(公告)号：US10776234B2
公开(公告)日：2020-09-15
申请号：US16183912
申请日：2018-11-08
申请人： Marc-Andre Lacroix
发明人： Marc-Andre Lacroix
IPC分类号： G06F11/00 , G06F11/263 , G06F11/22 , H04B1/40
摘要： There is provided an integrated loopback used for on-die self-test and diagnosis of transceiver faults. According to embodiments, there is provided an interface network including an AC coupling capacitor interposed between input pins of the interface network and an input of an amplifier, a shunt capacitor interposed between the AC coupling capacitor and the input of the amplifier and a selector. The selector includes a mission mode circuit component connected to a bottom plate of the shunt capacitor and the selector is configured to select between a first mode and a second mode, wherein the first mode is mission mode and the second mode is loopback mode, wherein in the second mode the mission mode circuit component forms at least part of a circuit that supplies a loopback signal.

3. 发明申请

US20200151076A1 ON-DIE INPUT CAPACITIVE DIVIDER FOR WIRELINE RECEIVERS WITH INTEGRATED LOOPBACK 审中-公开
公开(公告)号：US20200151076A1
公开(公告)日：2020-05-14
申请号：US16183912
申请日：2018-11-08
申请人： Marc-Andre LACROIX
发明人： Marc-Andre LACROIX
IPC分类号： G06F11/263 , H04B1/40 , G06F11/22
摘要： There is provided an integrated loopback used for on-die self-test and diagnosis of transceiver faults. According to embodiments, there is provided an interface network including an AC coupling capacitor interposed between input pins of the interface network and an input of an amplifier, a shunt capacitor interposed between the AC coupling capacitor and the input of the amplifier and a selector. The selector includes a mission mode circuit component connected to a bottom plate of the shunt capacitor and the selector is configured to select between a first mode and a second mode, wherein the first mode is mission mode and the second mode is loopback mode, wherein in the second mode the mission mode circuit component forms at least part of a circuit that supplies a loopback signal.

4. 发明授权

US10103743B1 Analog-to-digital converter and control method thereof 有权
公开(公告)号：US10103743B1
公开(公告)日：2018-10-16
申请号：US15808095
申请日：2017-11-09
申请人： Luke Wang , Anthony Chan Carusone , Marc-Andre Lacroix
发明人： Luke Wang , Anthony Chan Carusone , Marc-Andre Lacroix
IPC分类号： H03M3/00 , H03M1/16 , H03M1/12 , H03M1/08 , H03H17/02
摘要： The present disclosure relates to an analog-to-digital converter (ADC) and a method for controlling an ADC. The ADC includes a plurality of quantization levels for analog-to-digital conversion. The ADC is adapted for utilizing a subset of the plurality of quantization levels for analog-to-digital signal conversion. The subset is formed by selecting at least one level to be deactivated using a greedy search method and deactivating the at least one level. The method includes using a subset of the plurality of quantization levels for analog-to-digital signal conversion, the subset being formed by selecting at least one level to be deactivated using a greedy search method and deactivating the at least one level.

5. 发明申请

US20190028236A1 FEC DRIVEN LINK OPTIMIZATION 审中-公开
公开(公告)号：US20190028236A1
公开(公告)日：2019-01-24
申请号：US15656888
申请日：2017-07-21
申请人： DAVIDE TONIETTO , MARC-ANDRE LACROIX , HENRY WONG
发明人： DAVIDE TONIETTO , MARC-ANDRE LACROIX , HENRY WONG
IPC分类号： H04L1/00 , H04L12/26
摘要： Methods, systems and computer-readable media for optimizing SerDes system parameters based on a bit error rate detected by a forward error correction unit (FEC). A SerDes receiver receives a data stream over a link and uses a FEC to detect error information in the received data stream. The system tunes and optimizes one or more SerDes system parameters using the detected error information. The system minimizes power consumption by decreasing power supply voltage until a maximum acceptable input error rate threshold is reached. The FEC allows the system to tolerate errors in the input data stream up to the threshold while preventing propagation of these errors in the FEC output data stream.

6. 发明授权

US10009035B1 Dynamic control of ADC resolution 有权
公开(公告)号：US10009035B1
公开(公告)日：2018-06-26
申请号：US15495572
申请日：2017-04-24
申请人： Marc-Andre LaCroix , Semyon Lebedev , Henry Wong , Davide Tonietto
发明人： Marc-Andre LaCroix , Semyon Lebedev , Henry Wong , Davide Tonietto
IPC分类号： H03M1/06 , H03M1/08 , H04B1/38 , H03M1/12 , H04L25/06 , H03M1/00
CPC分类号： H04B1/38 , H03M1/00 , H03M1/007 , H03M1/12 , H03M1/1215 , H03M1/46 , H04L25/067
摘要： Methods, systems and devices for dynamically controlling resolution of an analog-to-digital converter (ADC). The ADC receives an analog input signal and outputs digital data. A statistical unit coupled to the ADC obtains samples of the output signal and transmits a control signal to the ADC to adjust the resolution of the ADC. The control signal is generated by the statistical unit based on a comparison of at least one performance indicator with a target performance level. The at least one performance indicator is calculated using the samples.

7. 发明授权

US09306609B1 DC-coupled differential circuit front end 有权
标题翻译：直流耦合差分电路前端
公开(公告)号：US09306609B1
公开(公告)日：2016-04-05
申请号：US14595303
申请日：2015-01-13
申请人： Marc-Andre LaCroix
发明人： Marc-Andre LaCroix
IPC分类号： H04B3/00 , H04B1/16 , H04B3/54
CPC分类号： H04B3/548
摘要： A front-end of a first differential circuit is DC-coupled to a second differential circuit. The front-end comprises a resistive element, a voltage sensor and a current adjustor. The resistive element has a resistivity between a first end that is DC-coupled to the second circuit and a second end that is DC-coupled to the first circuit and accepts a programmable current passing therethrough to impose a voltage across the element that varies in direction and amplitude according to the current value. The voltage sensor senses a difference between a DC voltage at the second end of the resistive element and a desired reference voltage of the first circuit. The current adjustor adjusts a direction and amplitude of the programmable current so that the voltage of the first circuit matches the desired reference voltage of the first circuit. The first circuit may be a receiver circuit and the second circuit may be a transmitter circuit. The front-end may further comprise a current canceller comprising a second resistive element connected at a first end to the output of the second circuit. The current canceller senses the programmable current and generates a current of equal amplitude through the second resistive element and away from the output of the second circuit. The current canceller may be implemented in digital or analog form and/or in differential or common-mode operation.
摘要翻译：第一差分电路的前端被直流耦合到第二差分电路。前端包括电阻元件，电压传感器和电流调节器。电阻元件在与第二电路直流耦合的第一端和与第一电路直流耦合的第二端之间具有电阻率，并且接受通过其中的可编程电流，从而在方向上变化的元件施加电压和幅度根据当前值。电压传感器感测电阻元件的第二端处的直流电压与第一电路的期望参考电压之间的差。电流调节器调节可编程电流的方向和幅度，使得第一电路的电压与第一电路的期望参考电压匹配。第一电路可以是接收器电路，第二电路可以是发射机电路。前端还可以包括电流消除器，其包括在第一端连接到第二电路的输出的第二电阻元件。电流消除器感测可编程电流并且通过第二电阻元件产生相等振幅的电流并远离第二电路的输出。电流消除器可以以数字或模拟形式和/或差分或共模操作来实现。

8. 发明授权

US11133812B1 Asynchronous SAR ADC using two-stage comparator having separate resets 有权
公开(公告)号：US11133812B1
公开(公告)日：2021-09-28
申请号：US17080263
申请日：2020-10-26
申请人： Semyon Lebedev , Babak Zamanlooy , Marc-Andre Lacroix
发明人： Semyon Lebedev , Babak Zamanlooy , Marc-Andre Lacroix
IPC分类号： H03M1/06 , H03M1/46 , H03M1/40 , H03M1/38 , H03M1/12
摘要： Systems and circuits for an asynchronous SAR ADC are described. The SAR ADC includes a two-stage comparator with a preamplifier first stage and a latch second stage. The preamplifier first stage is activated by an active pulse of a first clock signal and the latch second stage is activated by an active pulse of a second clock signal. The Done signal from a done detector is fed back as the active pulse of the first clock signal. The leading edge of the active pulse of the second clock signal is driven by the leading edge of the active pulse of the first clock signal via an RS latch. The Done signal is further fed back through the RS latch to drive a trailing edge of the active pulse of the second clock signal.

9. 发明授权

US09553600B1 Skew detection and correction in time-interleaved analog-to-digital converters 有权
标题翻译：时间交错模数转换器中的偏斜检测和校正
公开(公告)号：US09553600B1
公开(公告)日：2017-01-24
申请号：US15187161
申请日：2016-06-20
申请人： Marc-Andre Lacroix , Henry Wong , Davide Tonietto
发明人： Marc-Andre Lacroix , Henry Wong , Davide Tonietto
IPC分类号： H03M1/06 , H03M1/12 , H03M1/00 , H04L7/00
CPC分类号： H03M1/0624 , G06F1/10 , H03M1/00 , H03M1/12 , H03M1/1215 , H03M1/1225 , H04L7/0008
摘要： The present disclosure provides a system, circuit, and method for correcting clock skew in time-interleaved analog-to-digital converters. At least two clock signals are received along respective channels. A delay of a first channel, carrying a first clock signal, is accounted for by applying one or more first adjustment factors to the channels until an edge of the first clock signal is aligned with a transition point of a reference signal. The first clock signal is swapped to the second channel, and vice-versa. A value of the reference signal as sampled by the first clock signal is compared to values of the reference signal as sampled by the second clock signal to determine a skew of the second channel vis-à-vis the first channel, and one or more second adjustment factors are applied to the second channel based on the determined skew of the second channel.
摘要翻译：本公开提供了一种用于校正时间交织的模数转换器中的时钟偏移的系统，电路和方法。沿相应的通道接收至少两个时钟信号。通过对通道应用一个或多个第一调整因子直到第一时钟信号的边沿与参考信号的转换点对准来考虑承载第一时钟信号的第一通道的延迟。第一个时钟信号被交换到第二个信道，反之亦然。将由第一时钟信号采样的参考信号的值与由第二时钟信号采样的参考信号的值进行比较，以确定第二信道相对于第一信道的偏斜，以及一个或多个第二信道基于确定的第二通道的倾斜度，将调整因子应用于第二通道。

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