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1. 发明申请

US20190020742A1 HIGH-SPEED INTERCONNECT SOLUTIONS WITH SUPPORT FOR CONTINUOUS TIME BACK CHANNEL COMMUNICATION 审中-公开
公开(公告)号：US20190020742A1
公开(公告)日：2019-01-17
申请号：US15797424
申请日：2017-10-30
申请人： Avago Technologies General IP (Singapore) Pte. Ltd.
发明人： Adam HEALEY
IPC分类号： H04L29/08
CPC分类号： H04L69/324 , H04B3/04 , H04B3/32 , H04L1/0008 , H04L25/03006 , H04L25/03019 , H04L25/03343 , H04L25/14 , H04L69/323 , H04L2001/0096 , H04L2025/03375 , H04L2025/0377 , H04L2025/03815
摘要： The present disclosure is directed to systems, apparatuses, and methods for performing continuous or periodic link training. Existing link training protocols generally perform link training only once during startup or initialization of a link and, as a result, are limited in their applications. After link training is performed and Open Systems Interconnect (OSI) data link layer and other high-layer data is transmitted across the link, no further link training is performed using these existing link training protocols. However, parameters of the link may change over time after link training is performed, such as temperature of the link and voltage levels of signals transmitted over the link by the transmitter of the transmitter-receiver pair.

2. 发明授权

US09742597B1 Decision feedback equalizer 有权
公开(公告)号：US09742597B1
公开(公告)日：2017-08-22
申请号：US15084351
申请日：2016-03-29
申请人： Xilinx, Inc.
发明人： Kun-Yung Chang , Siok Wei Lim , Kee Hian Tan
IPC分类号： H04L25/03
CPC分类号： H04L25/03057 , H04L25/03885 , H04L25/4902 , H04L2025/03363 , H04L2025/03375 , H04L2025/03484 , H04L2025/03764
摘要： An apparatus includes a decision feedback equalizer configured to receive a parallel signal generated based on a first clock. The decision feedback equalizer includes a first equalization block configured to receive a first symbol of a first set of parallel symbols provided by the parallel signal during a first clock cycle of the first clock. A decision feedback equalization is performed by the first equalization block to the first symbol to provide a first decision to a second equalization block. The second equalization block is configured to receive a second symbol of the first set of parallel symbols and perform a decision feedback equalization to the second symbol using the first decision received from the first equalization block to provide a second decision during the first clock cycle.

3. 发明授权

US09548801B2 Closed loop multiple transmit, multiple receive antenna wireless communication system 有权
标题翻译：闭路多发，多接收天线无线通信系统
公开(公告)号：US09548801B2
公开(公告)日：2017-01-17
申请号：US13614991
申请日：2012-09-13
申请人： Eko N. Onggosanusi , Anand G. Dabak
发明人： Eko N. Onggosanusi , Anand G. Dabak
IPC分类号： H03D1/04 , H04L27/00 , H04L27/14 , H04B7/04 , H04B7/06 , H04L1/00 , H04L1/06 , H04L25/03 , H04B1/7115 , H04B7/08
CPC分类号： H04B7/0417 , H04B1/7115 , H04B7/0634 , H04B7/082 , H04B7/0854 , H04B2201/70702 , H04L1/0001 , H04L1/0025 , H04L1/0029 , H04L1/0675 , H04L25/03343 , H04L2025/03375
摘要： A wireless receiver (74) for receiving signals from a transmitter (72). The transmitter comprises a plurality of transmit antennas (TAT1′, TAT2′) for transmitting the signals, which comprise respective independent streams of symbols. Additionally, interference occurs between the respective streams. The receiver comprises a plurality of receive antennas (RAT1′, RAT2′) for receiving the signals as influenced by a channel effect between the receiver and the transmitter. The receiver also comprises circuitry (80) for multiplying the signals times a conjugate transpose of an estimate of the channel effect and times a conjugate transpose of a linear basis transformation matrix. The receiver also comprises circuitry (84) for selecting the linear basis transformation matrix from a finite set of linear basis transformation matrices. Lastly, the receiver comprises circuitry (88) for removing the interference between the respective streams.
摘要翻译：一种用于从发射机（72）接收信号的无线接收机（74）。发射机包括用于发送信号的多个发射天线（TAT1'，TAT2'），其包括相应的独立的符号流。另外，在各个流之间发生干扰。接收机包括多个接收天线（RAT1'，RAT2'），用于接收由接收机和发射机之间的信道效应影响的信号。接收机还包括用于将信号乘以信道效应的估计的共轭转置乘以线性基变换矩阵的共轭转置次数的电路（80）。接收机还包括用于从有限线性基变换矩阵组中选择线性基变换矩阵的电路（84）。最后，接收机包括用于消除各个流之间的干扰的电路（88）。

4. 发明授权

US09237042B2 Filter network arrangement 有权
标题翻译：过滤网络布置
公开(公告)号：US09237042B2
公开(公告)日：2016-01-12
申请号：US14399810
申请日：2013-05-03
申请人： ASTRIUM LIMITED
发明人： David Young
IPC分类号： H04B3/36 , H04L25/03 , H03H21/00 , H04B7/185
CPC分类号： H04L25/03159 , H03H21/0001 , H04B7/18513 , H04L25/03878 , H04L2025/03375
摘要： There is provided a filter network arrangement comprising a filter network; and one or more correction networks, wherein the one or more correction networks is arranged to substantially equalize the passband gain and group delay of the filter network arrangement. Given an appropriate Q for the one or more correction networks, a polynomial for the one or more correction networks can be found that equalizes both the passband gain and group delay and the one or more correction networks can be synthesized from the polynomial.
摘要翻译：提供了一种包括滤波器网络的滤波器网络布置; 以及一个或多个校正网络，其中所述一个或多个校正网络被布置为基本上均衡滤波器网络布置的通带增益和组延迟。给定一个或多个校正网络的适当的Q，可以找到一个或多个校正网络的多项式，其对通带增益和组延迟两者进行均衡，并且可以从多项式来合成一个或多个校正网络。

5. 发明申请

US20130336363A1 ITERATIVE INTERFERENCE SUPPRESSION USING MIXED FEEDBACK WEIGHTS AND STABILIZING STEP SIZES 有权
标题翻译：使用混合反馈重量和稳定步长尺寸的迭代干扰抑制
公开(公告)号：US20130336363A1
公开(公告)日：2013-12-19
申请号：US13908264
申请日：2013-06-03
申请人： Rambus Inc.
发明人： Tommy Guess , Michael L. McCloud , Vijay Nagarajan , Gagandeep Singh Lamba
IPC分类号： H04B1/715
CPC分类号： H04B1/715 , H04B1/7107 , H04B1/71072 , H04B1/71075 , H04B1/7115 , H04L25/03006 , H04L2025/03375
摘要： A receiver is configured for canceling intra-cell and inter-cell interference in coded, multiple-access, spread-spectrum transmissions that propagate through frequency-selective communication channels. The receiver employs iterative symbol-estimate weighting, subtractive cancellation with a stabilizing step-size, and mixed-decision symbol estimate. Receiver embodiments may be implemented explicitly in software of programmed hardware, or implicitly in standard Rake-based hardware either within the Rake (i.e., at the finger level) or outside the Rake (i.e., at the user of subchannel symbol level).
摘要翻译：接收机被配置为消除通过频率选择性通信信道传播的编码，多址，扩频传输中的小区内和小区间干扰。接收机采用迭代符号估计加权，具有稳定步长的减法消除和混合判决符号估计。接收机实施例可以在编程硬件的软件中明确地实现，或者隐含地在Rake（即，在手指级别）处或在Rake外部（即，在子信道符号级别的用户处）的基于标准Rake的硬件中。

6. 发明授权

US08213638B2 Equalizer 有权
标题翻译：均衡器
公开(公告)号：US08213638B2
公开(公告)日：2012-07-03
申请号：US11708874
申请日：2007-02-20
申请人： Yanli Fan , Mark W. Morgan
发明人： Yanli Fan , Mark W. Morgan
IPC分类号： H03H7/30
CPC分类号： H04L25/03038 , H04L2025/03375
摘要： Methods and apparatus to provide an equalizer for analog adaptive control are disclosed. An example equalizer described herein includes a high frequency amplifier to receive an input signal and to amplify a high frequency portion of the input signal, a low frequency amplifier to receive the input signal and to amplify a low frequency portion of the input signal, and a weight factor controller to control a gain of the high frequency amplifier and a gain of the low frequency amplifier.
摘要翻译：公开了提供用于模拟自适应控制的均衡器的方法和装置。本文所述的示例均衡器包括用于接收输入信号并放大输入信号的高频部分的高频放大器，用于接收输入信号并放大输入信号的低频部分的低频放大器，以及权重因子控制器来控制高频放大器的增益和低频放大器的增益。

7. 发明申请

US20110299627A1 TRANSMITTER PRE-DISTORTION ACROSS WIDE TRANSMIT POWER DYNAMIC RANGE 有权
标题翻译：发射机预失真通过广义发射功率动态范围
公开(公告)号：US20110299627A1
公开(公告)日：2011-12-08
申请号：US13214329
申请日：2011-08-22
申请人： Arya Reza Behzad
发明人： Arya Reza Behzad
IPC分类号： H04L25/49
CPC分类号： H04L25/03343 , H04L2025/03375
摘要： An integrated circuit radio transceiver and method therefor includes an integrated circuit radio transceiver operable to provide pre-distortion settings that correspond to specified analog transmit path gain levels. Further, a change in gain is provided solely through digital gain when the new gain is within a specified range. If the gain change is not within the specified range, the gain is provided by a new transmit path gain module and, if necessary, with additional digital gain. Additionally, a new pre-distortion setting is applied to correspond to the new analog transmit path gain setting.
摘要翻译：集成电路无线电收发器及其方法包括集成电路无线电收发器，其可操作以提供对应于指定的模拟发送路径增益水平的预失真设置。此外，当新增益在指定范围内时，仅通过数字增益提供增益的变化。如果增益变化不在规定的范围内，则增益由新的发送路径增益模块提供，如有必要，则增加额外的数字增益。此外，应用新的预失真设置以对应于新的模拟发送路径增益设置。

8. 发明授权

US07940738B2 Wireless communication unit and method for processing a code division multiple access signal 有权
标题翻译：无线通信单元和用于处理码分多址信号的方法
公开(公告)号：US07940738B2
公开(公告)日：2011-05-10
申请号：US11570302
申请日：2005-05-23
申请人： Arik Gubeskys , Amir Chass
发明人： Arik Gubeskys , Amir Chass
IPC分类号： H04B7/216
CPC分类号： H04L1/008 , H04B1/7105 , H04L2025/03375 , H04L2025/03783
摘要： A method of processing a code division multiple access signal comprises receiving a CDMA signal; processing the received CDMA signal with a CDMA detector; and extracting control channel information from the processed signal. The extracted control channel information is used to equalize a subsequent received CDMA signal, to make estimation of equalizer coefficients more reliable and increasing average data throughput.
摘要翻译：一种处理码分多址信号的方法包括接收CDMA信号; 用CDMA检测器处理所接收的CDMA信号; 并从所处理的信号中提取控制信道信息。所提取的控制信道信息用于对后续接收的CDMA信号进行均衡，以使均衡器系数的估计更可靠，并增加平均数据吞吐量。

9. 发明授权

US07936807B2 Method and apparatus for reducing the processing rate of a chip-level equalization receiver 失效
标题翻译：降低芯片级均衡接收机的处理速率的方法和装置
公开(公告)号：US07936807B2
公开(公告)日：2011-05-03
申请号：US12535010
申请日：2009-08-04
申请人： Jung-Lin Pan
发明人： Jung-Lin Pan
IPC分类号： H04B1/00 , H04L1/02
CPC分类号： H04B1/70757 , H04B1/707 , H04B1/7115 , H04B2201/70707 , H04L25/03038 , H04L2025/03375 , H04L2025/03477 , H04L2025/03617
摘要： A method and apparatus for reducing the processing rate when performing chip-level equalization (CLE) in a code division multiple access (CDMA) receiver which includes an equalizer filter. Signals received by at least one antenna of the receiver are sampled at M times the chip rate. Each sample stream is split into M sample data streams at the chip rate. Multipath combining is preferably performed on each split sample data stream. The sample data streams are then combined into one combined sample data stream at the chip rate. The equalizer filter performs equalization on the combined sample stream at the chip rate. Filter coefficients are adjusted by adding a correction term to the filter coefficients utilized by the equalizer filter for a previous iteration.
摘要翻译：一种用于在包括均衡器滤波器的码分多址（CDMA）接收机中执行码片级均衡（CLE）时降低处理速率的方法和装置。由接收机的至少一个天线接收的信号以芯片速率的M倍采样。每个样本流以码片速率被分成M个采样数据流。优选对每个分割样本数据流执行多路径组合。然后将样本数据流以码片速率组合成一个组合的采样数据流。均衡器滤波器以码片速率对组合的采样流进行均衡。通过将校正项加到由均衡器滤波器用于先前迭代的滤波器系数来调整滤波器系数。

10. 发明授权

US07929913B2 Adaptive receiver architecture 有权
标题翻译：自适应接收机架构
公开(公告)号：US07929913B2
公开(公告)日：2011-04-19
申请号：US10321024
申请日：2002-12-16
申请人： Qinghua Li , Leslie A. Rusch
发明人： Qinghua Li , Leslie A. Rusch
IPC分类号： H04B1/00
CPC分类号： H04B1/71055 , H04B1/71637 , H04B1/7176 , H04B1/719 , H04L27/18 , H04L2025/03375 , H04L2025/03477 , H04L2025/03617
摘要： The present disclosure relates to an apparatus and technique for a wireless communications receiver architecture and, more particularly, to an apparatus and technique for an analog adaptive receiver architecture.
摘要翻译：本公开涉及一种用于无线通信接收机架构的装置和技术，更具体地，涉及用于模拟自适应接收机架构的装置和技术。

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