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1. 发明申请

US20200076370A1 METHOD AND DEVICE FOR FSK/GFSK DEMODULATION 审中-公开
公开(公告)号：US20200076370A1
公开(公告)日：2020-03-05
申请号：US16559961
申请日：2019-09-04
申请人： TELINK SEMICONDUCTOR (SHANGHAI) CO., LTD.
发明人： Hong NIE
IPC分类号： H03D3/02 , H04L27/144
摘要： The present invention relates to communication technologies and provides a method and a device for FSK/GFSK demodulation, the method comprises: determining a digital information vector group {Vl(i)} of a codeword a[k] to be demodulated and a corresponding phase matching vector group {θi(i)] within the duration of (2M+1)T; determining a received phase vector {tilde over (φ)}(i) of a received FSK/GFSK baseband signal φ(t, a); determining an average phase difference βl between {tilde over (φ)}(i) and θl(i); calculating the phase matching degree Ql between {tilde over (φ)}(i) and θl(i) after removing the impact of the average phase difference βl, and determining an l value corresponding to the phase matching degree Ql being the maximum; and determining the a[k], corresponding to the l value, in the digital information vector Vi(i) as a demodulation result. Because the impact of the average phase difference is removed during phase matching, the accuracy of phase matching is increased, and the performance of the phase domain demodulation technology is improved.

2. 发明授权

US10292099B2 Transmission apparatus, reception apparatus, communication system, transmission method, and reception method 有权
公开(公告)号：US10292099B2
公开(公告)日：2019-05-14
申请号：US14403929
申请日：2014-03-06
申请人： Panasonic Corporation
发明人： Koji Imamura , Takayuki Abe
IPC分类号： H04W52/02 , H04W74/04 , H04L27/06 , H04L25/02 , H04L27/04 , H04W72/04 , H03C3/00 , H03D3/02 , H04L27/10
摘要： Provided is a transmission apparatus capable of reducing power consumption of a reception apparatus. The transmission apparatus includes a modulator that modulates a data signal to generate a transmission signal. The modulator modulates the data signal by assigning the data signal to a frequency difference between a first frequency and a second frequency in a carrier.

3. 发明授权

US09306621B2 Transceiver including a high latency communication channel and a low latency communication channel 有权
标题翻译：收发器包括高延迟通信信道和低延迟通信信道
公开(公告)号：US09306621B2
公开(公告)日：2016-04-05
申请号：US14498383
申请日：2014-09-26
申请人： Broadcom Corporation
发明人： Heng Zhang , Mehdi Khanpour , Jun Cao , Chang Liu , Afshin Momtaz
IPC分类号： H04B1/74 , H03D3/02 , H03D3/00 , H04L7/033
CPC分类号： H04B1/745 , H03D3/006 , H03D3/02 , H04L7/033
摘要： Methods, systems, and apparatuses are described for reducing the latency in a transceiver. A transceiver includes a high latency communication channel and a low latency communication channel that is configured to be a bypass channel for the high latency communication channel. The low latency communication channel may be utilized when implementing the transceiver is used in low latency applications. By bypassing the high latency communication channel, the high latency that is introduced therein (due to the many stages of de-serialization used to reduce the data rate for digital processing) can be avoided. An increase in data rate is realized when the low latency communication channel is used to pass data. A delay-locked loop (DLL) may be used to phase align the transmitter clock of the transceiver with the receiver clock of the transceiver to compensate for a limited tolerance of phase offset between these clocks.
摘要翻译：描述了减少收发器中的延迟的方法，系统和装置。收发器包括高延迟通信信道和被配置为高延迟通信信道的旁路信道的低延迟通信信道。当在低延迟应用中使用收发器时，可以利用低延迟通信信道。通过绕过高延迟通信信道，可以避免其中引入的高等待时间（由于用于减少数字处理的数据速率的许多解除序列化阶段）。当低延迟通信信道用于传递数据时，实现数据速率的增加。可以使用延迟锁定环（DLL）将收发器的发射机时钟与收发器的接收机时钟相位对准，以补偿这些时钟之间的相位偏移的有限公差。

4. 发明授权

US08643431B2 On-chip millimeter wave lange coupler 有权
标题翻译：片上毫米波兰光耦合器
公开(公告)号：US08643431B2
公开(公告)日：2014-02-04
申请号：US13277265
申请日：2011-10-20
申请人： Hanyi Ding , Kwan Him Lam
发明人： Hanyi Ding , Kwan Him Lam
IPC分类号： H03D3/02 , H01P5/18
CPC分类号： H03F3/68 , H01P5/186 , H03D3/007 , H03F3/602
摘要： A Lange coupler having a first plurality of lines on a first level and a second plurality of lines on a second level. At least one line on the first level is cross-coupled to a respective line on the second level via electromagnetic waves traveling through the first and second plurality of lines. The first and second plurality of lines may be made of metal, and the first level may be higher than the second level. A substrate may be provided into which the first and second plurality of lines are etched so as to define an on-chip Lange coupler.
摘要翻译： Lange耦合器，其具有在第一电平上的第一多个线，而在第二电平上具有第二多个线。在第一级上的至少一条线通过在第一和第二条线上行进的电磁波交叉耦合到第二电平上的相应线。第一和第二多个线可以由金属制成，并且第一电平可以高于第二电平。可以提供衬底，其中蚀刻第一和第二多条线以便限定片上朗格耦合器。

5. 发明授权

US08249207B1 Clock and data recovery sampler calibration 有权
标题翻译：时钟和数据恢复采样器校准
公开(公告)号：US08249207B1
公开(公告)日：2012-08-21
申请号：US12040585
申请日：2008-02-29
申请人： Jurgen Hissen , Dragos Cartina
发明人： Jurgen Hissen , Dragos Cartina
IPC分类号： H04L7/02 , H03D3/02
CPC分类号： H03L7/091 , H03L7/0807 , H04L7/033
摘要： Methods and apparatus are disclosed, such as those involving clock and data recovery sampler calibration. One such method includes receiving an electronic data stream by a clock and data recovery (CDR) circuit comprising a data sampler and an edge sampler. The data stream includes data portions and transitioning portions. The method further includes conducting calibration of the CDR circuit. The calibration includes acquiring samples from the transitioning portions of the data stream using the data sampler; and calibrating the data sampler based at least partially on the samples acquired using the data sampler. The method allows one not only to improve performance, but also to improve yield and reduce testing and screening requirements without requiring any additional circuitry to detect the offsets and works with regular input signals.
摘要翻译：公开了诸如涉及时钟和数据恢复采样器校准的方法和装置。一种这样的方法包括通过包括数据采样器和边缘采样器的时钟和数据恢复（CDR）电路接收电子数据流。数据流包括数据部分和转换部分。该方法还包括进行CDR电路的校准。校准包括使用数据采样器从数据流的转换部分获取样本; 并且至少部分地基于使用数据采样器采集的样本校准数据采样器。该方法不仅可以提高性能，而且还可以提高产量并降低测试和筛选要求，而不需要任何附加电路来检测偏移量并使用常规输入信号。

6. 发明授权

US07408418B2 Phase locked loop circuit having reduced lock time 有权
标题翻译：锁相环电路具有减少的锁定时间
公开(公告)号：US07408418B2
公开(公告)日：2008-08-05
申请号：US11480757
申请日：2006-06-30
申请人： Philippe Sirito-Olivier
发明人： Philippe Sirito-Olivier
IPC分类号： H03L7/093 , H03D3/02
CPC分类号： H03L7/10 , H03L7/0995 , H03L7/107 , H03L2207/06
摘要： A phase locked loop circuit comprising a phase detector having a first input for receiving a first frequency signal and an output, a first filter adapted to filter the output electric signal of the phase detector, a voltage controlled oscillator adapted to generate a second frequency signal in response to the output filtered signal of the phase detector. The phase detector has a second input for receiving the second frequency signal and is adapted to compare it with the first frequency signal. The circuit comprises means adapted to amplify the difference between an electric signal coupled with the output of the phase detector and a reference electric signal and a second filter adapted to receive the output electric signal of the amplification means and to send an output electric signal to the voltage controlled oscillator. The circuit comprises further means adapted to modify the value of the electric signal in input to the second filter to decrease the response time of the second filter.
摘要翻译：一种锁相环电路，包括具有用于接收第一频率信号和输出的第一输入的相位检测器，适于滤波相位检测器的输出电信号的第一滤波器，适于产生第二频率信号的压控振荡器响应于相位检测器的输出滤波信号。相位检测器具有用于接收第二频率信号的第二输入，并且适于将其与第一频率信号进行比较。电路包括适于放大与相位检测器的输出耦合的电信号与参考电信号之间的差的装置，以及适于接收放大装置的输出电信号的第二滤波器，并将输出电信号发送到压控振荡器。该电路包括适于修改输入到第二滤波器的电信号的值以减少第二滤波器的响应时间的装置。

7. 发明授权

US07183839B2 Diode detecting circuit 失效
标题翻译：二极管检测电路
公开(公告)号：US07183839B2
公开(公告)日：2007-02-27
申请号：US10998729
申请日：2004-11-30
申请人： Shinji Saito
发明人： Shinji Saito
IPC分类号： H03D3/02
CPC分类号： H03D1/10 , H03D2200/0096
摘要： A diode detecting circuit which cancels temperature dependence of a detecting diode so as to obtain highly sensitive detection. The diode detecting circuit has a first diode detecting unit in which a first diode detects an input signal biased by a bias voltage, a second diode detecting unit in which a second diode receives the bias voltage, and an output unit which compares an output from the first diode detecting unit with an output from the second diode detecting unit.
摘要翻译：一种二极管检测电路，其消除检测二极管的温度依赖性，以获得高灵敏度的检测。二极管检测电路具有第一二极管检测单元，其中第一二极管检测到偏置电压偏置的输入信号，第二二极管检测单元，其中第二二极管接收偏置电压;以及输出单元，其将来自第一二极管检测单元，具有来自第二二极管检测单元的输出。

8. 发明申请

US20060071708A1 Phase locked loop demodulator with gain control 有权
标题翻译：具有增益控制的锁相环解调器
公开(公告)号：US20060071708A1
公开(公告)日：2006-04-06
申请号：US10532902
申请日：2003-10-09
申请人： Eric Desbonnets , Frederic Parillaud , Erick Giroux
发明人： Eric Desbonnets , Frederic Parillaud , Erick Giroux
IPC分类号： H03D3/02
CPC分类号： H03D3/244
摘要： The invention relates to a demodulator to demodulate frequency-modulated signals FM including a phase locked loop PLL including at least a phase detector, a loop filter and a voltage controlled oscillator function VCO′, characterized in that said voltage controlled oscillator function VCO′ has modifiable gain. The invention allows to eliminate drawbacks presented by the conventional use of a complex gain modifiable amplifier at the input of demodulated signal processing means. Application: demodulation of modulated signals: wireless phone, home network.
摘要翻译：本发明涉及一种用于解调包括至少包括相位检测器，环路滤波器和压控振荡器功能VCO'的锁相环PLL的调频信号FM的解调器，其特征在于所述压控振荡器功能VCO'具有可修改获得。本发明允许消除在解调信号处理装置的输入处常规使用复增益可调放大器所呈现的缺点。应用：调制信号的解调：无线电话，家庭网络。

9. 发明授权

US6160860A Phase-locked loop (PLL) circuit containing a frequency detector for improved frequency acquisition 失效
标题翻译：锁相环（PLL）电路，包含频率检测器，用于改进频率采集
公开(公告)号：US6160860A
公开(公告)日：2000-12-12
申请号：US14418
申请日：1998-01-28
申请人： Patrik Larsson
发明人： Patrik Larsson
IPC分类号： H03L7/087 , H03L7/091 , H03L7/14 , H04L7/033 , H04L7/04 , H03D3/24 , H03D3/02 , H03D3/18 , H03L7/06
CPC分类号： H03L7/14 , H03L7/087 , H03L7/091 , H04L7/033 , H04L7/041 , H04L7/044 , H04L7/046
摘要： An extended frequency lock range is achieved in a phase-locked loop (PLL) circuit based on sampled phase detectors by introducing frequency feedback into the PLL circuit. At least one data sampler samples adjacent bits of incoming data, such as data bits D.sub.X and D.sub.Y, and an edge detector samples an edge, E, of the incoming data signal between the two data bits, D.sub.X and D.sub.Y. Sequence values "101" or "010" for the data bits D.sub.X, E and D.sub.Y, are not valid and indicate that the VCO is sampling the incoming data stream too slowly. When sequence values of "101" or "010" are measured by the sampled phase detectors, the frequency of the VCO output, V.sub.O, is known to be too low, and a constant current is preferably injected by the sampled phase detector into the PLL, until the frequency becomes too high, upon which a constant current of opposite polarity is applied. A PLL circuit having a frequency detector in combination with a biased phase detector is also disclosed, to ensure that the PLL can be locked. A biased phase detector applies more phase error correction in one direction than in the other direction. For example, a positive biased phase detector applies more positive current, I.sub.UP, over time than negative current, I.sub.DOWN. The VCO control voltage is initialized to a value below the lock-in voltage for a positive biased phase detector embodiment, and the positive biased phase detector will cause a steady increase in the VCO control voltage until the PLL locks, thereby causing the phase error to be approximately zero.
摘要翻译：通过将频率反馈引入到PLL电路中，基于采样相位检测器的锁相环（PLL）电路实现了扩展频率锁定范围。至少一个数据采样器对输入数据的相邻位（例如数据位DX和DY）进行采样，边缘检测器对两个数据位DX和DY之间的输入数据信号的边沿E进行采样。数据位DX，E和DY的序列值“101”或“010”无效，表明VCO正在对输入数据流进行太慢的采样。当通过采样相位检测器测量“101”或“010”的序列值时，已知VCO输出端VO的频率太低，并且恒定电流优选地由采样相位检测器注入PLL 直到频率变得过高，施加相反极性的恒定电流。还公开了具有与偏置相位检测器组合的频率检测器的PLL电路，以确保可锁定PLL。偏置相位检测器在一个方向上比在另一个方向上更多的相位误差校正。例如，正偏置相位检测器随着时间的长短而比负电流（IDOWN）应用更多的正电流IUP。 VCO控制电压被初始化为低于正偏置相位检测器实施例的锁定电压的值，并且正偏置相位检测器将导致VCO控制电压的稳定增加，直到PLL锁定，从而导致相位误差大约为零。

10. 发明授权

US6081572A Lock-in aid frequency detector 失效
标题翻译：锁定辅助频率检测器
公开(公告)号：US6081572A
公开(公告)日：2000-06-27
申请号：US141673
申请日：1998-08-27
申请人： Jan Filip
发明人： Jan Filip
IPC分类号： H03D13/00 , H03L7/087 , H03L7/095 , H03L7/10 , H04L7/033 , H03D3/24 , H03D1/00 , H03D3/00 , H03D3/02 , H03D3/18
CPC分类号： H03L7/087 , H03D13/003 , H03L7/095 , H03L7/10
摘要： Circuit and method for generating a signal for use in locking a second signal on a first signal. The first and second signals have an associated frequency. A first beat note signal and a second beat note signal are generated from the first and second signals, respectively, when the frequencies of the first and second signals are not equal. The circuit includes a first and second flip-flop and detector circuitry. The first flip-flop is configured to receive the first and second beat note signals for generating a first state signal. The first flip-flop generates the first state signal by sampling the second beat note signal at a first periodic interval of the first beat note signal. The second flip-flop is configured to receive the first and second beat note signals for generating a second state signal. The second flip-flop generates the second state signal by sampling the second beat note signal at a second periodic interval of the first beat note signal. The detector circuitry is coupled to receive the first and second state signals from the first and second flip-flops for detecting a polarity of the frequency difference between the first and second signals. The polarity of the frequency difference is defined in a tri-state having a positive state, a negative state, and a zero state.
摘要翻译：用于产生用于锁定第一信号上的第二信号的信号的电路和方法。第一和第二信号具有相关联的频率。当第一和第二信号的频率不相等时，分别从第一和第二信号产生第一拍音信号和第二拍音信号。该电路包括第一和第二触发器和检测器电路。第一触发器被配置为接收用于产生第一状态信号的第一和第二拍音信号。第一触发器通过以第一拍音信号的第一周期性间隔采样第二拍音信号来产生第一状态信号。第二触发器被配置为接收用于产生第二状态信号的第一和第二拍音信号。第二触发器通过以第一拍音信号的第二周期性间隔采样第二拍音信号来产生第二状态信号。检测器电路被耦合以从第一和第二触发器接收第一和第二状态信号，以检测第一和第二信号之间的频率差的极性。频率差的极性被定义为具有正状态，负状态和零状态的三态。

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