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序号	专利名	申请号	申请日	公开（公告）号	公开（公告）日	发明人
101	TRANSISTOR GAIN CELL WITH FEEDBACK	EP15786178.2	2015-04-30	EP3138101B1	2019-09-04	GITERMAN, Robert; TEMAN, Adam; MEINERZHAGEN, Pascal; BURG, Andreas; FISH, Alexander

102	Semiconductor device	EP11180109.8	2011-09-06	EP2428959B1	2018-05-30	Matsuzaki, Takanori; Nagatsuka, Shuhei; Inoue, Hiroki
A semiconductor device in which stored data can be held even when power is not supplied and there is no limitation on the number of writing operations is provided. A semiconductor device is formed using a material which can sufficiently reduce the off-state current of a transistor, such as an oxide semiconductor material that is a wide-gap semiconductor. When a semiconductor material which can sufficiently reduce the off-state current of a transistor is used, the semiconductor device can hold data for a long period. In addition, by providing a capacitor or a noise removal circuit electrically connected to a write word line, a signal such as a short pulse or a noise input to a memory cell can be reduced or removed. Accordingly, a malfunction in which data written into the memory cell is erased when a transistor in the memory cell is instantaneously turned on can be prevented.
103	TRANSISTOR GAIN CELL WITH FEEDBACK	EP15786178	2015-04-30	EP3138101A4	2017-12-06	GITERMAN ROBERT; TEMAN ADAM; MEINERZHAGEN PASCAL; BURG ANDREAS; FISH ALEXANDER
A gain cell includes a write bit line input, a read bit line output, a write trigger input and a read trigger input. The gain cell also includes a write transistor, retention element and read transistor. Each of the transistors includes a respective first diffusion connection, gate connection and second diffusion connection. The write transistor first diffusion connection is connected to the write bit line input and the write transistor gate connection is connected to the write trigger input. The read transistor first diffusion connection being connected to the read bit line output and the second diffusion connection is connected to the read trigger input. The retention element buffers between write transistor and the read transistor during data retention. The retention element also connects or disconnects a write transistor diffusion connection to/from a constant voltage in accordance with a retained data level at the read transistor gate connection.
104	SEMICONDUCTOR DEVICE AND DRIVING METHOD OF THE SAME	EP11742135	2011-01-25	EP2534679A4	2016-03-16	INOUE HIROKI; KATO KIYOSHI; MATSUZAKI TAKANORI; NAGATSUKA SHUHEI

105	REFERENCE CURRENT GENERATOR, AND METHOD OF PROGRAMMING, ADJUSTING AND/OR OPERATING SAME	EP04751987.1	2004-05-12	EP1620859B1	2008-06-04	PORTMANN, Lionel; KAYAL, Maher; PASTRE, Marc; BLAGOJEVIC, Marija; DECLERCQ, Michel
There are many inventions described and illustrated herein. In a first aspect, the present invention is a technique and circuitry for reading data that is stored in memory cells. In one embodiment of this aspect, the present invention is a technique and circuitry for generating a reference current that is used, in conjunction with a sense amplifier, to read data that is stored in memory cells of a DRAM device. The technique and circuitry for generating a reference current may be implemented using an analog configuration, a digital configuration, and/or combinations of analog and digital configurations.
106	SEMICONDUCTOR MEMORY	EP01912146	2001-03-07	EP1282133A4	2007-12-19	TAKAHASHI HIROYUKI; INABA HIDEO; SONODA MASATOSHI; KATO YOSHIYUKI; NAKAGAWA ATSUSHI
A semiconductor memory the cycle time of which is shortened by accelerating the address access. A first address decoder (2) and a first refresh address decoder (5) decode an external address (Xn) fed from outside of the semiconductor memory and a refresh address (RXn) used for refresh in the semiconductor memory, respectively. A multiplexer (8) selects either a decode signal (XnDm) on the external address side or a decode signal (XnRm) on the refresh address side according to an external address transmission signal (EXTR) and a refresh address transmission signal (RFTR) so that a refresh and a Read/Write may be continuously performed in one memory cycle, and outputs the selected one as a decode signal (XnMm). A word driver (10) decodes the decode signals (XnMm, XpMq) selected by the multiplexer (8) and so forth so as to activate a word line (WLmq).
107	REFRESHING OF MULTI-PORT MEMORY IN INTEGRATED CIRCUITS	EP03797250.2	2003-08-26	EP1540658A1	2005-06-15	JAIN, Raj Kumar
A dual port memory module comprising a contention circuit for refresh in order to detect a conflict between an externally requested access and a refresh operation is described. The refresh operation is allocated to the port that is not externally accessed. When accesses through both ports are requested, a wait cycle for one of the access requests is inserted until the refresh is terminated.
108	POWER FAILURE MODE FOR A MEMORY CONTROLLER	EP99927507	1999-06-14	EP1090342A4	2002-02-06	CRETA KENNETH C
A power failure mode for a memory controller (200), such as a memory controller used in an input/output processor (100), which, when the memory controller has system power, refreshes a memory unit (210), such as an SDRAM memory unit, as required to maintain the memory image. In one embodiment, when a power failure occurs, the memory controller issues a self-refresh command to the memory, which has battery-backup power. A PCI reset signal may be used to determine when a power failure has occured. The self-refresh command places the memory in a self-refresh mode, and a programmable logic device may be used to ensure that a clock enable signal input to the memory maintains the self-refresh mode. When system power returns, the memory controller resumes refreshing the memory.
109	REFRESH STRATEGY FOR DRAMS	EP96922577	1996-06-27	EP0792506A4	1998-08-19	MOTE L RANDALL JR
An improved method of accessing dynamic random access memory (DRAM) banks (120, 130, 150, 160) during refresh cycles contemplates sequentially accessing DRAM banks which do not share common filtering capacitors (140, 170). In this manner, voltage drops caused by refresh accesses are not observed in consecutive clock cycles at the same filtering capacitors so that the filtering capacitors (140, 170) will have sufficient recovery time to restore the supply voltage to the original voltage level before another refresh hit occurs at the same capacitor. In this manner, significant voltage drops are alleviated at the voltage supply inputs (110) to the DRAM banks (120, 130, 150, 160).
110	METHOD AND STRUCTURE FOR UTILIZING A DRAM ARRAY AS SECOND LEVEL CACHE MEMORY	EP95939102	1995-11-20	EP0793827A4	1998-04-15	LEUNG WINGYU; HSU FU-CHIEH
A method and structure for using a DRAM memory array (213) as a second level cache memory in a computer system (200). The computer system includes a central processing unit (CPU) (201), a first level SRAM cache memory (202), a CPU bus (204), and a second level cache memory (213) which includes a DRAM array (317) coupled to the CPU bus. In one embodiment, the DRAM array is operated at a higher frequency than the CPU bus clock signal. In another embodiment, a widened data path is provided to the DRAM array. Both embodiments effectively increase the data rate of the DRAM array, thereby providing additional time for precharging the DRAM array. As a result the precharging of the DRAM array is transparent to the CPU bus.
111	VOLATILE/NON-VOLATILE DYNAMIC RAM CELL AND SYSTEM.	EP81901464	1981-05-14	EP0051672A4	1984-04-04	VAN VELTHOVEN ARMAND JOSEPH AN
The invention is concerned with the problem of reducing the chip area occupied by volatile/nonvolatile dynamic RAM (random access memory) cells. A volatile/non-volatile dynamic RAM cell (30, 80) includes a storage capacitor (32) for volatilely storing binary information during normal RAM operation; an alterable-threshold storage capacitor (33A or 83) for non-volatilely storing the information in non-volatile fashion during poweroff conditions; and an energy barrier (33F or 45) between the two capacitors. Information can be restored to the volatile capacitor either by CCD charge transfer or by charge-pumped operation. The energy barrier facilitates efficient charge pumped restore of information. In one embodiment, the energy barrier is a high concentration substrate surface region (45) having the same conductivity type as the substrate. Alternatively, the alterable-threshold non-volatile capacitor and the energy barrier are provided by a split-gate capacitor (33) which has an alterable threshold non-volatile section (33A) (the non-volatile capacitor) and a non-alterable threshold section (33F) (the energy barrier). The cells may be arranged in an array.
112	Semiconductor storage device	EP11194028.4	2011-12-16	EP2466587B1	2020-09-02	Nagatsuka, Shuhei; Takahashi, Yasuyuki

113	Semiconductor storage device	EP11194028.4	2011-12-16	EP2466587A3	2013-06-12	Nagatsuka, Shuhei; Takahashi, Yasuyuki
A semiconductor storage device with a novel structure, which can retain stored data even when power is not supplied (i.e., is non-volatile) and has no limitation on the number of write cycles. The semiconductor storage device includes a memory cell array in which a plurality of memory cells are arranged in matrix, a decoder configured to select a memory cell to operate among the plurality of memory cells in accordance with a control signal, and a control circuit configured to select whether to output the control signal to the decoder. In each of the plurality of memory cells, data is held by turning off a selection transistor whose channel region is formed with an oxide semiconductor.
114	Semiconductor device	EP11180109.8	2011-09-06	EP2428959A1	2012-03-14	Matsuzaki, Takanori; Nagatsuka, Shuhei; Inoue, Hiroki
A semiconductor device in which stored data can be held even when power is not supplied and there is no limitation on the number of writing operations is provided. A semiconductor device is formed using a material which can sufficiently reduce the off-state current of a transistor, such as an oxide semiconductor material that is a wide-gap semiconductor. When a semiconductor material which can sufficiently reduce the off-state current of a transistor is used, the semiconductor device can hold data for a long period. In addition, by providing a capacitor or a noise removal circuit electrically connected to a write word line, a signal such as a short pulse or a noise input to a memory cell can be reduced or removed. Accordingly, a malfunction in which data written into the memory cell is erased when a transistor in the memory cell is instantaneously turned on can be prevented.
115	Dynamic random access memory device and method for self-refreshing memory cells with temperature compensated self-refresh	EP11007526.4	2007-03-30	EP2405440A1	2012-01-11	Pyeon, Hong Beom
A dynamic random access memory (DRAM) device has an array of DRAM cells of rows by columns. Each DRAM cell of the array is coupled with a wordline of a corresponding row and a bitline of a corresponding column. An entry into and an exit from the self-refresh mode are detected by a mode detector and a self-refresh mode signal is provided. An oscillation circuit generates in response to the self-refresh mode signal generates a basic time period. A first frequency divider/time period multiplier changes the basic time period in accordance with a process variation factor relating to the DRAM device. A second frequency divider/time period multiplier further changes the changed time period in accordance with a temperature change factor. relating to the DRAM device. In the self-refresh mode, data stored in the DRAM cells is refreshed. In accordance with the two factors, the DRAM devices perform and achieve reliable self-refresh for variable DRAM cell retention time.
116	DYNAMIC RANDOM ACCESS MEMORY WITH FULLY INDEPENDENT PARTIAL ARRAY REFRESH FUNCTION	EP07719431	2007-03-28	EP2016588A4	2009-08-05	KIM JIN-KI; OH HAKJUNE
A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing. The PASR settings are made by a memory controller. Any kind of combinations of subblock addresses may be selected. Thus, the memory subblocks are fully independently refreshed. User selectable memory arrays for data retention provide effective memory control programming especially for low power mobile application.
117	DYNAMIC RANDOM ACCESS MEMORY WITH FULLY INDEPENDENT PARTIAL ARRAY REFRESH FUNCTION	EP07719431.4	2007-03-28	EP2016588A1	2009-01-21	KIM, Jin-Ki; OH, HakJune
A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing. The PASR settings are made by a memory controller. Any kind of combinations of subblock addresses may be selected. Thus, the memory subblocks are fully independently refreshed. User selectable memory arrays for data retention provide effective memory control programming especially for low power mobile application.
118	SEMICONDUCTOR MEMORY CELL, ARRAY, ARCHITECTURE AND DEVICE, AND METHOD OF OPERATING SAME	EP04751661	2004-05-07	EP1623432A4	2007-02-21	FERRANT RICHARD; OKHONIN SERGUEI; CARMAN ERIC; BRON MICHEL
There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory cell and technique of reading data from and writing data into that memory cell. In this regard, in one embodiment of this aspect of the invention, the memory cell (FIG. 3A, 3B) includes two transistors (102a, 102b) which store complementary data states (“0”, “1”). That is, the two-transistor memory cell includes a first transistor that maintains a complementary state relative to the second transistor. As such, when programmed, one of the transistors of the memory cell stores a logic low (a binary '0') and the other transistor of the memory cell stores a logic high (a binary “l”). The data state of the two-transistor complementary memory cell may be read and/or determined by sampling, sensing measuring and/or detecting the polarity of the logic states stored in each transistor of complementary memory cell (FIG. 4). That is, the two-transistor complementary memory cell is read by sampling, sensing measuring and/or detecting the difference in signals (current or voltage) stored in the two transistors.
119	SEMICONDUCTOR MEMORY AND CONTROL METHOD	EP01984292	2001-07-26	EP1329896A4	2006-01-25	TAKAHASHI HIROYUKI; SONODA MASATOSHI
A semiconductor memory in which no operating current caused by the noise of an address signal fed from outside is effectively suppressed without retarding the operating speed during read/write. The semiconductor memory comprises a circuit system including a filter circuit (102) for removing the noise of an address signal fed from outside and an ATD circuit (311) for detecting a transition of the address signal before it passes through the filter circuit (102) and generating a first address transition detection signal ( ζATD1) if a transition is detected and a circuit system including an ATD circuit (321) for detecting a transition of the address signal after it passes the filter circuit (102) and generating a second address transition detection signal ( ζATD2) if a transition is detected. The refresh is controlled by the first address transition detection signal ( ζATD1), and the read/write is controlled by the second address transition detection signal (ζATD2). Thus if noise is generated, only refresh is carried out, and the operating current is effectively suppressed. A method for controlling such a semiconductor memory is also disclosed.
120	REFRESHING OF MULTI-PORT MEMORY IN INTEGRATED CIRCUITS	EP03797250.2	2003-08-26	EP1540658B1	2005-12-28	JAIN, Raj Kumar
A dual port memory module comprising a contention circuit for refresh in order to detect a conflict between an externally requested access and a refresh operation is described. The refresh operation is allocated to the port that is not externally accessed. When accesses through both ports are requested, a wait cycle for one of the access requests is inserted until the refresh is terminated.

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