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    • 24. 发明申请
    • PROTECTION CIRCUIT FOR POWER AMPLIFIER
    • 功率放大器保护电路
    • US20110043956A1
    • 2011-02-24
    • US12715250
    • 2010-03-01
    • Wenjun SuAristotele HadjichristosGurkanwal S. SahotaMarco Cassia
    • Wenjun SuAristotele HadjichristosGurkanwal S. SahotaMarco Cassia
    • H02H3/20
    • H03F1/52H03F3/24H03F2200/435H03F2200/78H03G3/3042H04B2001/0408
    • Techniques for protecting a power amplifier (PA) are described. In an exemplary design, an apparatus includes (i) a PA module to amplify an input RF signal and provide an output RF signal and (ii) a protection circuit to control a transmitter gain to protect the PA module against high peak voltage. In an exemplary design, the protection circuit includes a set of comparators to quantize an analog input signal and provide digital comparator output signals used to adjust the transmitter gain. In another exemplary design, the protection circuit reduces and increases the transmitter gain with hysteresis. In yet another exemplary design, the protection circuit has faster response to rising amplitude than falling amplitude of the output RF signal. The hysteresis and/or the different rise and fall responses may allow the protection circuit to avoid toggling the transmitter gain under severe load mismatch and to handle time-varying envelope due to amplitude modulation.
    • 描述了用于保护功率放大器(PA)的技术。 在示例性设计中,装置包括(i)PA模块,用于放大输入RF信号并提供输出RF信号,以及(ii)保护电路以控制发射机增益以保护PA模块免受高峰值电压。 在示例性设计中,保护电路包括一组比较器,用于量化模拟输入信号并提供用于调整发射机增益的数字比较器输出信号。 在另一示例性设计中,保护电路通过滞后减小并增加发射机增益。 在又一示例性设计中,保护电路比对输出RF信号的下降幅度具有对振幅上升的响应更快。 迟滞和/或不同的上升和下降响应可以允许保护电路避免在严重负载不匹配的情况下切换发射机增益,并且由于幅度调制来处理时变包络。
    • 25. 发明申请
    • SWITCH WITH IMPROVED BIASING
    • 开关改进偏心
    • US20110025403A1
    • 2011-02-03
    • US12623197
    • 2009-11-20
    • Marco Cassia
    • Marco Cassia
    • H03K17/687H03K17/00
    • H03K17/102H03F3/72H03K17/693H03K2217/0018
    • Switches with improved biasing and having better isolation and reliability are described. In an exemplary design, a switch is implemented with a set of transistors, a set of resistors, and an additional resistor. The set of transistors is coupled in a stacked configuration, receives an input signal, and provides an output signal. The set of resistors is coupled to the gates of the set of transistors. The additional resistor is coupled to the set of resistors and receives a control signal for the set of transistors. The resistors reduce signal loss through parasitic capacitances of the transistors when they are turned on. The resistors also help split the signal swing of the input signal approximately evenly across the transistors when they are turned off, which may improve reliability of the transistors. The switch may be used in a switchplexer, a power amplifier (PA) module, etc.
    • 描述了具有改进的偏置并具有更好的隔离和可靠性的开关。 在示例性设计中,用一组晶体管,一组电阻器和附加电阻器来实现开关。 晶体管组以堆叠配置耦合,接收输入信号,并提供输出信号。 该组电阻器耦合到该组晶体管的栅极。 附加电阻器耦合到该组电阻器并且接收该组晶体管的控制信号。 当晶体管导通时,电阻通过寄生电容减小信号损耗。 电阻器还有助于在晶体管关断时大致均匀地分离输入信号的信号摆幅,这可以提高晶体管的可靠性。 开关可用于交换机,功率放大器(PA)模块等。
    • 26. 发明授权
    • High voltage logic circuits
    • 高电压逻辑电路
    • US07868657B1
    • 2011-01-11
    • US12619562
    • 2009-11-16
    • Marco Cassia
    • Marco Cassia
    • H03K19/00
    • H03K19/018521H03K19/0013H03K19/00315
    • High voltage logic circuits that can handle digital input and output signals having a larger voltage range are described. In an exemplary design, a high voltage logic circuit includes an input stage, a second stage, and an output stage. The input stage receives at least one input signal and provides (i) at least one first intermediate signal having a first voltage range and (ii) at least one second intermediate signal having a second voltage range. The second stage receives and processes the first and second intermediate signals based on a logic function and provides (i) a first drive signal having the first voltage range and (ii) a second drive signal having the second voltage range. The output stage receives the first and second drive signals and provides an output signal having a third voltage range, which may be larger than each of the first and second voltage ranges.
    • 描述了可以处理具有较大电压范围的数字输入和输出信号的高电压逻辑电路。 在示例性设计中,高压逻辑电路包括输入级,第二级和输出级。 输入级接收至少一个输入信号,并提供(i)具有第一电压范围的至少一个第一中间信号和(ii)具有第二电压范围的至少一个第二中间信号。 第二级基于逻辑功能接收和处理第一和第二中间信号,并提供(i)具有第一电压范围的第一驱动信号和(ii)具有第二电压范围的第二驱动信号。 输出级接收第一和第二驱动信号,并提供具有第三电压范围的输出信号,其可以大于第一和第二电压范围中的每一个。
    • 27. 发明授权
    • Methods and apparatuses for selectable voltage supply
    • 用于可选电压供应的方法和装置
    • US07851947B2
    • 2010-12-14
    • US11935186
    • 2007-11-05
    • Marco CassiaAristotele HadjichristosConor DonovanSang-Oh Lee
    • Marco CassiaAristotele HadjichristosConor DonovanSang-Oh Lee
    • H02B1/24
    • H03K17/693Y10T307/696Y10T307/747
    • A circuit which selects a supply voltage from a plurality of voltage supplies is presented. The circuit includes a first transistor configured to select a first voltage supply, a second transistor configured to select a second voltage supply, a first parasitic current inhibitor coupled the first transistor, the first voltage supply, and the second voltage supply, where the first parasitic current inhibitor automatically utilizes the voltage supply providing the highest voltage for preventing a substrate current from flowing through a bulk node of the first transistor, and a second parasitic current inhibitor coupled the second transistor, the first voltage supply, and the second voltage supply, where the second parasitic current inhibitor automatically utilizes the voltage supply providing the highest voltage for preventing a substrate current from flowing through a bulk node of the second transistor.
    • 提出了从多个电压源中选择电源电压的电路。 该电路包括:第一晶体管,被配置为选择第一电压源;第二晶体管,被配置为选择第二电压源;耦合第一晶体管,第一电压源和第二电压源的第一寄生电流抑制器,其中第一寄生 电流抑制器自动地利用提供最高电压的电压源来防止衬底电流流过第一晶体管的体节点,以及耦合第二晶体管,第一电压源和第二电压源的第二寄生电流抑制器,其中 第二寄生电流抑制器自动利用提供最高电压的电压源来防止衬底电流流过第二晶体管的体节点。
    • 29. 发明申请
    • CASCODE AMPLIFIER WITH PROTECTION CIRCUITRY
    • 带保护电路的CASCODE放大器
    • US20100237945A1
    • 2010-09-23
    • US12407729
    • 2009-03-19
    • Marco CassiaGurkanwal Singh Sahota
    • Marco CassiaGurkanwal Singh Sahota
    • H03F3/16
    • H03F1/223H03F1/523H03F3/211H03F3/72H03F2200/27H03F2200/294H03F2203/7206H03F2203/7215H03F2203/7236H03G1/0088
    • A cascode amplifier with protection circuitry is described. In one exemplary design, the amplifier includes multiple branches coupled in parallel, with at least one branch being switchable between “on” and “off” states. Each switchable branch includes a gain transistor coupled to a cascode transistor. The gain transistor amplifies an input signal and provides an amplified signal in the on state and does not amplify the input signal in the off state. The cascode transistor buffers the amplified signal and provides an output signal in the on state. The output signal swing may be split between the gain transistor and the cascode transistor in both the on and off states with the protection circuitry. Each transistor may then observe a fraction of the voltage swing. The voltage splitting in the off state may be achieved by floating the gain transistor and shorting the gate and source of the cascode transistor.
    • 描述了具有保护电路的共源共栅放大器。 在一个示例性设计中,放大器包括并联耦合的多个分支,至少一个分支可在“开”和“关”状态之间切换。 每个可切换分支包括耦合到共源共栅晶体管的增益晶体管。 增益晶体管放大输入信号,并将放大的信号提供为导通状态,并且不将输入信号放大在关闭状态。 共源共栅晶体管缓冲放大的信号,并提供处于导通状态的输出信号。 在保护电路中,输出信号摆幅可以在开关状态和断开状态之间在增益晶体管和共源共栅晶体管之间分开。 然后,每个晶体管可以观察电压摆幅的一小部分。 断开状态下的分压可以通过使增益晶体管浮置并使共源共栅晶体管的栅极和源极短路来实现。