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    • 41. 发明授权
    • Tunable matching circuits for power amplifiers
    • 功率放大器的可调匹配电路
    • US09143172B2
    • 2015-09-22
    • US12544177
    • 2009-08-19
    • Puay Hoe SeeAristotele HadjichristosGurkanwal Singh Sahota
    • Puay Hoe SeeAristotele HadjichristosGurkanwal Singh Sahota
    • H03F3/04H04B1/04H03F1/56H03F3/24H03F3/72
    • H04B1/0458H03F1/565H03F3/24H03F3/72H03F2200/111H03F2200/378H03F2200/387H03F2203/7209
    • Tunable matching circuits for power amplifiers are described. In an exemplary design, an apparatus may include a power amplifier and a tunable matching circuit. The power amplifier may amplify an input RF signal and provide an amplified RF signal. The tunable matching circuit may provide output impedance matching for the power amplifier, may receive the amplified RF signal and provide an output RF signal, and may be tunable based on at least one parameter effecting the operation of the power amplifier. The parameter(s) may include an envelope signal for the amplified RF signal, an average output power level of the output RF signal, a power supply voltage for the power amplifier, IC process variations, etc. The tunable matching circuit may include a series variable capacitor and/or a shunt variable capacitor. Each variable capacitor may be tunable based on a control generated based on the parameter(s).
    • 描述了用于功率放大器的可调谐匹配电路。 在示例性设计中,设备可以包括功率放大器和可调谐匹配电路。 功率放大器可以放大输入RF信号并提供放大的RF信号。 可调谐匹配电路可以为功率放大器提供输出阻抗匹配,可以接收放大的RF信号并提供输出RF信号,并且可以基于影响功率放大器的操作的至少一个参数来调节。 参数可以包括放大的RF信号的包络信号,输出RF信号的平均输出功率电平,功率放大器的电源电压,IC过程变化等。可调谐匹配电路可以包括一系列 可变电容器和/或分流可变电容器。 每个可变电容器可以基于基于参数产生的控制来调节。
    • 47. 发明申请
    • TUNABLE MATCHING CIRCUITS FOR POWER AMPLIFIERS
    • 功率放大器的可调匹配电路
    • US20100308933A1
    • 2010-12-09
    • US12544177
    • 2009-08-19
    • Puay Hoe SeeAristotele HadjichristosGurkanwal Singh Sahota
    • Puay Hoe SeeAristotele HadjichristosGurkanwal Singh Sahota
    • H03H7/38
    • H04B1/0458H03F1/565H03F3/24H03F3/72H03F2200/111H03F2200/378H03F2200/387H03F2203/7209
    • Tunable matching circuits for power amplifiers are described. In an exemplary design, an apparatus may include a power amplifier and a tunable matching circuit. The power amplifier may amplify an input RF signal and provide an amplified RF signal. The tunable matching circuit may provide output impedance matching for the power amplifier, may receive the amplified RF signal and provide an output RF signal, and may be tunable based on at least one parameter effecting the operation of the power amplifier. The parameter(s) may include an envelope signal for the amplified RF signal, an average output power level of the output RF signal, a power supply voltage for the power amplifier, IC process variations, etc. The tunable matching circuit may include a series variable capacitor and/or a shunt variable capacitor. Each variable capacitor may be tunable based on a control generated based on the parameter(s).
    • 描述了用于功率放大器的可调谐匹配电路。 在示例性设计中,设备可以包括功率放大器和可调谐匹配电路。 功率放大器可以放大输入RF信号并提供放大的RF信号。 可调谐匹配电路可以为功率放大器提供输出阻抗匹配,可以接收放大的RF信号并提供输出RF信号,并且可以基于影响功率放大器的操作的至少一个参数来调节。 参数可以包括放大的RF信号的包络信号,输出RF信号的平均输出功率电平,功率放大器的电源电压,IC过程变化等。可调谐匹配电路可以包括一系列 可变电容器和/或分流可变电容器。 每个可变电容器可以基于基于参数产生的控制来调节。
    • 49. 发明申请
    • CASCODE AMPLIFIER WITH PROTECTION CIRCUITRY
    • 带保护电路的CASCODE放大器
    • US20100237945A1
    • 2010-09-23
    • US12407729
    • 2009-03-19
    • Marco CassiaGurkanwal Singh Sahota
    • Marco CassiaGurkanwal Singh Sahota
    • H03F3/16
    • H03F1/223H03F1/523H03F3/211H03F3/72H03F2200/27H03F2200/294H03F2203/7206H03F2203/7215H03F2203/7236H03G1/0088
    • A cascode amplifier with protection circuitry is described. In one exemplary design, the amplifier includes multiple branches coupled in parallel, with at least one branch being switchable between “on” and “off” states. Each switchable branch includes a gain transistor coupled to a cascode transistor. The gain transistor amplifies an input signal and provides an amplified signal in the on state and does not amplify the input signal in the off state. The cascode transistor buffers the amplified signal and provides an output signal in the on state. The output signal swing may be split between the gain transistor and the cascode transistor in both the on and off states with the protection circuitry. Each transistor may then observe a fraction of the voltage swing. The voltage splitting in the off state may be achieved by floating the gain transistor and shorting the gate and source of the cascode transistor.
    • 描述了具有保护电路的共源共栅放大器。 在一个示例性设计中,放大器包括并联耦合的多个分支,至少一个分支可在“开”和“关”状态之间切换。 每个可切换分支包括耦合到共源共栅晶体管的增益晶体管。 增益晶体管放大输入信号,并将放大的信号提供为导通状态,并且不将输入信号放大在关闭状态。 共源共栅晶体管缓冲放大的信号,并提供处于导通状态的输出信号。 在保护电路中,输出信号摆幅可以在开关状态和断开状态之间在增益晶体管和共源共栅晶体管之间分开。 然后,每个晶体管可以观察电压摆幅的一小部分。 断开状态下的分压可以通过使增益晶体管浮置并使共源共栅晶体管的栅极和源极短路来实现。
    • 50. 发明申请
    • SYSTEM AND METHOD OF CALIBRATING POWER-ON GATING WINDOW FOR A TIME-TO-DIGITAL CONVERTER (TDC) OF A DIGITAL PHASE LOCKED LOOP (DPLL)
    • 用于数字相位锁定(DPLL)的时间到数字转换器(TDC)的校准功率增益窗口的系统和方法
    • US20090262878A1
    • 2009-10-22
    • US12107584
    • 2008-04-22
    • Bo SunGurkanwal Singh SahotaZixiang Yang
    • Bo SunGurkanwal Singh SahotaZixiang Yang
    • H04L7/00H03L7/06
    • H03L7/085H03L7/18H03L2207/50
    • A system and method are disclosed related to calibrating a power-on gating window for a time-to-digital converter (TDC) of a digital phase locked loop (DPLL). The gating window is calibrated to ensure proper operation of the DPLL, while at the same time operating the TDC in a power efficient manner. In particular, the technique entails setting the width of the TDC gating window to a default value; operating the DPLL until the control loop is substantially locked; decreasing the width of the TDC gating window by a predetermined amount, while monitoring the phase error signal generated by the phase error device of the DPLL; determining the current width of the TDC gating window at substantially a time when the phase error arrives at or crosses a predetermined threshold; and increasing the current width of the TDC gating window by a predetermined amount to build in a margin of error for the operating width of the TDC gating window.
    • 公开了一种系统和方法,用于校准数字锁相环(DPLL)的时间 - 数字转换器(TDC)的上电门控窗口。 门控窗口被校准,以确保DPLL的正常运行,同时以高效的方式操作TDC。 特别地,该技术需要将TDC门控窗口的宽度设置为默认值; 操作DPLL直到控制回路基本锁定; 同时监视由DPLL的相位误差装置产生的相位误差信号,将TDC门控窗口的宽度减小预定量; 在相位误差到达或超过预定阈值的时间基本上确定TDC门控窗口的当前宽度; 并且将TDC门控窗口的当前宽度增加预定量以构成TDC门控窗口的操作宽度的误差范围。