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1. 发明授权

US09243303B2 Method for the dissolving and rapid hydrolyzing of lignocellulose biomass, device thereof and use of the same 有权
标题翻译：木质纤维素生物质的溶解和快速水解的方法及其用途及其用途
公开(公告)号：US09243303B2
公开(公告)日：2016-01-26
申请号：US13876941
申请日：2011-07-04
申请人： Zhen Fang
发明人： Zhen Fang
IPC分类号： C07C29/00 , C09K3/00 , C13K1/02 , C08H8/00 , C12P7/10
CPC分类号： C13K1/02 , C07C29/00 , C08H8/00 , C09K3/00 , C12P7/10 , C12P2201/00 , C12P2203/00 , Y02E50/16 , Y02E50/17
摘要： A method for the dissolving and rapid hydrolyzing of the lignocellulose biomass and the device thereof are disclosed. The lignocellulose biomass is put in the pure water and rapidly heated to 330˜403° C., and then 89˜99% of the lignocellulose biomass is dissolved and rapidly hydrolyzed to saccharide in 3.38˜21.79 s. The following hydrolysis reaction can be carried out under the homogeneous phase condition for the dissolving of the lignocellulose biomass. At the same time, the solvated biomass could be easily used in the high pressure flow reactor to continuously pretreat the biomass and hydrolyze for producing saccharide, other biofuel and product. The present invention doesn't need any catalyst and doesn't pollute the environment, furthermore the process is simple and the cost is low, and it belongs to green, continuable industry encouraged by the state, and a good prospect of market application could be taken on.
摘要翻译：公开了一种用于溶解和快速水解木质纤维素生物质的方法及其装置。将木质纤维素生物质放入纯水中，迅速加热至330〜403℃，然后将89〜99％的木质纤维素生物质溶解并迅速水解成为3.38〜21.79s。以下水解反应可以在均相条件下进行，用于溶解木质纤维素生物质。同时，溶剂化生物质可以容易地用于高压流动反应器中，以连续预处理生物质，并水解生产糖，其他生物燃料和产品。本发明不需要任何催化剂，不污染环境，而且工艺简单，成本低，属于国家鼓励绿色，可持续发展的行业，市场应用前景广阔被带走

2. 发明授权

US08379659B2 Performance and traffic aware heterogeneous interconnection network 有权
标题翻译：性能和流量感知异构互连网络
公开(公告)号：US08379659B2
公开(公告)日：2013-02-19
申请号：US12748794
申请日：2010-03-29
申请人： Sriram R. Vangal , Nitin Y. Borkar , Zhen Fang
发明人： Sriram R. Vangal , Nitin Y. Borkar , Zhen Fang
IPC分类号： H04L12/54
CPC分类号： H04L47/30 , H04L47/39 , H04L49/109 , H04L49/40
摘要： In one embodiment, a method includes comparing an occupancy level of a buffer of a port of a router to a threshold, and controlling the port to operate at a first voltage and frequency based at least in part on the comparison, and at least one other port of the router is controlled to operate at a second voltage and frequency. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，一种方法包括将路由器的端口的缓冲器的占用水平与阈值进行比较，并且至少部分地基于比较来控制端口以第一电压和频率操作，以及至少一个其他路由器的端口被控制为以第二电压和频率操作。描述和要求保护其他实施例。

3. 发明授权

US08364862B2 Delegating a poll operation to another device 有权
标题翻译：将轮询操作委派给另一个设备
公开(公告)号：US08364862B2
公开(公告)日：2013-01-29
申请号：US12482614
申请日：2009-06-11
申请人： Michael J. Espig , Zhen Fang , Ravishankar Iyer , David J. Harriman
发明人： Michael J. Espig , Zhen Fang , Ravishankar Iyer , David J. Harriman
IPC分类号： G06F3/00
CPC分类号： G06F13/24 , G06F9/542
摘要： In one embodiment, the present invention includes a method for handling a registration message received from a host processor, where the registration message delegates a poll operation with respect to a device from the host processor to another component. Information from the message may be stored in a poll table, and the component may send a read request to poll the device and report a result of the poll to the host processor based on a state of the device. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于处理从主机处理器接收的注册消息的方法，其中所述注册消息将关于设备的轮询操作从主机处理器委托给另一个组件。来自消息的信息可以存储在轮询表中，并且组件可以发送读请求以轮询该设备并且基于该设备的状态向轮询处理器报告轮询的结果。描述和要求保护其他实施例。

4. 发明申请

US20120191896A1 CIRCUITRY TO SELECT, AT LEAST IN PART, AT LEAST ONE MEMORY 审中-公开
标题翻译：电路选择，至少一部分，至少一个记忆
公开(公告)号：US20120191896A1
公开(公告)日：2012-07-26
申请号：US13013104
申请日：2011-01-25
申请人： Zhen Fang , Li Zhao , Ravishankar Iyer , Srihari Makineni , Guangdeng Liao
发明人： Zhen Fang , Li Zhao , Ravishankar Iyer , Srihari Makineni , Guangdeng Liao
IPC分类号： G06F12/08
CPC分类号： G06F12/0813 , Y02D10/13
摘要： An embodiment may include circuitry to select, at least in part, from a plurality of memories, at least one memory to store data. The memories may be associated with respective processor cores. The circuitry may select, at least in part, the at least one memory based at least in part upon whether the data is included in at least one page that spans multiple memory lines that is to be processed by at least one of the processor cores. If the data is included in the at least one page, the circuitry may select, at least in part, the at least one memory, such that the at least one memory is proximate to the at least one of the processor cores. Many alternatives, variations, and modifications are possible.
摘要翻译：一个实施例可以包括至少部分地从多个存储器中选择至少一个存储器来存储数据的电路。存储器可以与相应的处理器核心相关联。该电路至少部分地至少部分地选择至少一个存储器，该至少一个存储器至少部分地基于是否将数据包括在跨越由至少一个处理器核处理的多个存储器线的至少一个页面中。如果数据被包括在至少一个页面中，则电路可以至少部分地选择至少一个存储器，使得至少一个存储器靠近处理器核心中的至少一个。许多替代方案，变化和修改是可能的。

5. 发明申请

US20100191920A1 Providing Address Range Coherency Capability To A Device 失效
标题翻译：为设备提供地址范围一致性能力
公开(公告)号：US20100191920A1
公开(公告)日：2010-07-29
申请号：US12360533
申请日：2009-01-27
申请人： Zhen Fang , David J. Harriman , Michael W. Leddige
发明人： Zhen Fang , David J. Harriman , Michael W. Leddige
IPC分类号： G06F12/08 , G06F12/00 , G06F12/10
CPC分类号： G06F12/0835 , G06F12/0888 , G06F12/1027
摘要： In one embodiment, the present invention includes a method for receiving a memory request from a device coupled to an input/output (IO) interconnect, accessing a mapping table associated with the IO interconnect to determine if an address range including an address of the memory request is coherent, and if so, sending the memory request and a coherency indicator to indicate the coherent state of data at the address, otherwise sending the memory request and the coherency indicator to indicate a non-coherent state. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于从耦合到输入/输出（IO）互连的设备接收存储器请求的方法，访问与IO互连关联的映射表，以确定包括存储器的地址的地址范围请求是一致的，如果是，则发送存储器请求和一致性指示符以指示地址处的数据的相干状态，否则发送存储器请求和一致性指示符以指示非相干状态。描述和要求保护其他实施例。

6. 发明申请

US20090292935A1 Method, System and Apparatus for Power Management of a Link Interconnect 有权
标题翻译：链路互连电源管理的方法，系统和设备
公开(公告)号：US20090292935A1
公开(公告)日：2009-11-26
申请号：US12126540
申请日：2008-05-23
申请人： Erik G. Hallnor , Zhen Fang , Hemant G. Rotithor
发明人： Erik G. Hallnor , Zhen Fang , Hemant G. Rotithor
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3253 , G06F1/3278 , Y02D10/151 , Y02D10/157
摘要： A proposal for power management control of an interconnect structure based on power state transition control. The power state transition is based on generating early warning signals and an idle timeout value setting based on response time and detection of subsequent requests.
摘要翻译：基于功率状态转换控制的互连结构的电源管理控制方案。电源状态转换基于产生预警信号和基于响应时间的空闲超时值设置以及后续请求的检测。

7. 发明申请

US20090259696A1 Node Synchronization for Multi-Processor Computer Systems 审中-公开
标题翻译：多处理器计算机系统的节点同步
公开(公告)号：US20090259696A1
公开(公告)日：2009-10-15
申请号：US12330413
申请日：2008-12-08
申请人： John Carter , Randal S. Passint , Donglai Dai , Zhen Fang , Lixin Zhang , Gregory M. Thorson
发明人： John Carter , Randal S. Passint , Donglai Dai , Zhen Fang , Lixin Zhang , Gregory M. Thorson
IPC分类号： G06F17/30
CPC分类号： G06F15/16 , Y10S707/99952
摘要： A method and apparatus for controlling access by a set of accessing nodes to memory of a home node (in a multimode computer system) determines that each node in the set of nodes has accessed the memory, and forwards a completion message to each node in the set of nodes after it is determined that each node has accessed the memory. The completion message has data indicating that each node in the set of nodes has accessed the memory of the home node.
摘要翻译：用于控制一组访问节点对家庭节点（在多模式计算机系统中）的存储器的访问的方法和装置确定该组节点中的每个节点已经访问了存储器，并将完成消息转发到在确定每个节点已访问存储器之后，节点集合。完成消息具有指示节点集合中的每个节点已经访问了家庭节点的存储器的数据。

8. 发明授权

US09395994B2 Embedded branch prediction unit 有权
标题翻译：嵌入式分支预测单元
公开(公告)号：US09395994B2
公开(公告)日：2016-07-19
申请号：US13992723
申请日：2011-12-30
申请人： Xiaowei Jiang , Srihari Makineni , Zhen Fang , Dmitri Pavlov , Ravi Iyer
发明人： Xiaowei Jiang , Srihari Makineni , Zhen Fang , Dmitri Pavlov , Ravi Iyer
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3806 , G06F9/30058
摘要： In accordance with some embodiments of the present invention, a branch prediction unit for an embedded controller may be placed in association with the instruction fetch unit instead of the decode stage. In addition, the branch prediction unit may include no branch predictor. Also, the return address stack may be associated with the instruction decode stage and is structurally separate from the branch prediction unit. In some cases, this arrangement reduces the area of the branch prediction unit, as well as power consumption.
摘要翻译：根据本发明的一些实施例，用于嵌入式控制器的分支预测单元可以与指令提取单元相关联而不是解码级放置。另外，分支预测单元也可以不包括分支预测器。此外，返回地址堆栈可以与指令解码级相关联，并且在结构上与分支预测单元分离。在某些情况下，这种布置减少了分支预测单元的面积以及功耗。

9. 发明授权

US09378164B2 Interrupt return instruction with embedded interrupt service functionality 有权
标题翻译：具有嵌入式中断服务功能的中断返回指令
公开(公告)号：US09378164B2
公开(公告)日：2016-06-28
申请号：US13997651
申请日：2011-12-22
申请人： Zhen Fang , Xiaowei Jiang , Srihari Makineni , Ramesh G. Illikkal , Ravishankar Iyer
发明人： Zhen Fang , Xiaowei Jiang , Srihari Makineni , Ramesh G. Illikkal , Ravishankar Iyer
IPC分类号： G06F13/24 , G06F9/32 , G06F9/38 , G06F9/48
CPC分类号： G06F9/3016 , G06F9/327 , G06F9/3861 , G06F9/4806 , G06F9/4812 , G06F13/24
摘要： An instruction pipeline implemented on a semiconductor chip is described. The semiconductor chip includes an execution unit having the following to execute an interrupt handling instruction. Storage circuitry to hold different sets of micro-ops where each set of micro-ops is to handle a different interrupt. First logic circuitry to execute a set of said sets of micro-ops to handle an interrupt that said set is designed for. Second logic circuitry to return program flow to an invoking program upon said first logic circuitry having handled said interrupt.
摘要翻译：描述了在半导体芯片上实现的指令流水线。半导体芯片包括执行单元，以执行中断处理指令。存储电路用于保存不同组的微操作，其中每组微操作都要处理不同的中断。第一逻辑电路，用于执行一组所述微操作组，以处理所述集合设计的中断。第二逻辑电路，用于在所述第一逻辑电路处理所述中断时将程序流返回到调用程序。

10. 发明授权

US08631207B2 Cache memory power reduction techniques 有权
标题翻译：高速缓存存储器功耗缩减技术
公开(公告)号：US08631207B2
公开(公告)日：2014-01-14
申请号：US12647461
申请日：2009-12-26
申请人： Zhen Fang , Meenakshisundara R. Chinthamani , Li Zhao , Milind B. Kamble , Ravishankar Iyer , Seung Eun Lee , Robert S. Chappell , Ryan L. Carlson
发明人： Zhen Fang , Meenakshisundara R. Chinthamani , Li Zhao , Milind B. Kamble , Ravishankar Iyer , Seung Eun Lee , Robert S. Chappell , Ryan L. Carlson
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F1/3225 , G06F1/3275 , G06F12/0895 , G06F2212/1028 , Y02D10/13 , Y02D10/14
摘要： Methods and apparatus to provide for power consumption reduction in memories (such as cache memories) are described. In one embodiment, a virtual tag is used to determine whether to access a cache way. The virtual tag access and comparison may be performed earlier in the read pipeline than the actual tag access or comparison. In another embodiment, a speculative way hit may be used based on pre-ECC partial tag match to wake up a subset of data arrays. Other embodiments are also described.
摘要翻译：描述了提供存储器（诸如高速缓存存储器）中的功耗降低的方法和装置。在一个实施例中，使用虚拟标签来确定是否访问缓存方式。虚拟标签访问和比较可以在读取管道中比实际标签访问或比较更早地进行。在另一个实施例中，可以基于ECC前部分标签匹配来使用推测方式命中来唤醒数据阵列的子集。还描述了其它实施例。

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