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91. 发明授权

US09520883B2 Frequency detection circuit and reception circuit 有权
标题翻译：频率检测电路和接收电路
公开(公告)号：US09520883B2
公开(公告)日：2016-12-13
申请号：US14834927
申请日：2015-08-25
申请人： FUJITSU LIMITED
发明人： Takayuki Shibasaki
IPC分类号： H03L7/06 , H03L7/085 , H03L7/087 , H03L7/089
CPC分类号： H03L7/085 , H03L7/087 , H03L7/089
摘要： A frequency detection circuit includes: a first comparison circuit configured to output a first comparison result produced by comparison between a second threshold value higher than a first threshold value; a second comparison circuit configured to output a second comparison result produced by comparison between a third threshold value lower than the first threshold value; a third comparison circuit configured to output a third comparison result produced by comparison between the input data, and the first threshold value at second timing of a second clock; a phase detector configured to determine in which one of the areas an edge of the input data is positioned among the three areas produced by dividing a phase in a one-bit width time into three areas; and a phase rotation detector configured to detect a rotation direction of the phase based on a change of a detection result in the phase detector.
摘要翻译：频率检测电路包括：第一比较电路，被配置为输出通过比较高于第一阈值的第二阈值而产生的第一比较结果; 第二比较电路，被配置为输出比第一阈值低的第三阈值之间的比较产生的第二比较结果; 第三比较电路，被配置为输出在第二时钟的第二定时处的输入数据和第一阈值之间的比较产生的第三比较结果; 相位检测器，被配置为通过将一位宽度时间中的相位除以三个区域来确定输入数据的边缘在哪个区域中的哪个区域中; 以及相位旋转检测器，被配置为基于相位检测器中的检测结果的变化来检测相位的旋转方向。

92. 发明授权

US09515669B2 Hybrid phase locked loop having wide locking range 有权
标题翻译：混合锁相环具有宽锁定范围
公开(公告)号：US09515669B2
公开(公告)日：2016-12-06
申请号：US15047778
申请日：2016-02-19
申请人： Microsemi SoC Corporation
发明人： Prakash Reddy
IPC分类号： H03L7/06 , H03L7/10 , H03L7/099 , H03L7/087
CPC分类号： H03L7/103 , H03L7/087 , H03L7/093 , H03L7/0991
摘要： A digital phased lock loop includes a digital controlled oscillator configured to produce an output signal at a frequency. A phase comparator compares the output signal, or a signal derived therefrom, with a reference signal to produce a phase error signal. A first loop filter produces a first control signal for the digital controlled oscillator from an output of the phase comparator. A frequency error measuring circuit coupled to the output of the phase comparator produces a frequency error signal. A second loop filter produces a second control signal for the digital controlled oscillator from an output of the frequency error measuring circuit. A circuit combines the first and second control signals and provides the combined control signals to the digital controlled oscillator.
摘要翻译：数字相位锁定环包括配置成以频率产生输出信号的数字控制振荡器。相位比较器将输出信号或由其导出的信号与参考信号进行比较，以产生相位误差信号。第一环路滤波器从相位比较器的输出产生数字控制振荡器的第一控制信号。耦合到相位比较器的输出的频率误差测量电路产生频率误差信号。第二环路滤波器从频率误差测量电路的输出产生数字控制振荡器的第二控制信号。电路组合第一和第二控制信号，并将组合的控制信号提供给数字控制振荡器。

93. 发明授权

US09509351B2 Simultaneous accommodation of a low power signal and an interfering signal in a radio frequency (RF) receiver 有权
标题翻译：在射频（RF）接收机中同时容纳低功率信号和干扰信号
公开(公告)号：US09509351B2
公开(公告)日：2016-11-29
申请号：US13559745
申请日：2012-07-27
申请人： Michael Joseph Shaw , Jonathan Lee Kennedy , Darrell Lee Livezey , Joy Laskar
发明人： Michael Joseph Shaw , Jonathan Lee Kennedy , Darrell Lee Livezey , Joy Laskar
IPC分类号： H04B15/00 , H04B1/10 , H04B1/00 , H04B1/28 , H03L7/06
CPC分类号： H04B1/10 , H03L7/06 , H04B1/0028 , H04B1/28
摘要： A method includes providing a highly linear front end in a Radio Frequency (RF) receiver, implementing a high Effective Number of Bits (ENOB) Analog to Digital Converter (ADC) circuit in the RF receiver, and sampling, through the high ENOB ADC circuit, at a frequency having harmonics that do not coincide with a desired signal component of an input signal of the RF receiver to eliminate spurs within a data bandwidth of the RF receiver. The input signal includes the desired signal component and an interference signal component. The interference signal component has a higher power level than the desired signal component. The method also includes simultaneously accommodating the desired signal component and the interference signal component in the RF receiver based on an increased dynamic range of the RF receiver and the high ENOB ADC circuit provided through the highly linear front end and the high ENOB ADC circuit.
摘要翻译：一种方法包括在射频（RF）接收机中提供高度线性的前端，实现RF接收机中的高有效位数（ENOB）模/数转换器（ADC）电路，并通过高ENOB ADC电路进行采样，其频率具有与RF接收机的输入信号的期望信号分量不一致的谐波，以消除RF接收机的数据带宽内的杂散。输入信号包括期望的信号分量和干扰信号分量。干扰信号分量具有比期望的信号分量更高的功率水平。该方法还包括基于通过高线性前端和高ENOB ADC电路提供的RF接收机和高ENOB ADC电路的增加的动态范围，同时容纳RF接收机中的期望信号分量和干扰信号分量。

94. 发明授权

US09503105B2 Phase frequency detector (PFD) circuit with improved lock time 有权
标题翻译：相位频率检测器（PFD）电路具有改进的锁定时间
公开(公告)号：US09503105B2
公开(公告)日：2016-11-22
申请号：US14868785
申请日：2015-09-29
申请人： Texas Instruments Incorporated
发明人： Peeyoosh Nitin Mirajkar , Jagdish Chand Goyal , Sankaran Aniruddhan
IPC分类号： H03L7/06 , H03L7/095 , H03L7/089 , H03L7/107
CPC分类号： H03L7/095 , H03L7/089 , H03L7/1072 , H03L7/1077
摘要： Described examples include circuitry and methods to control lock time of a phase lock loop (PLL) or other locking circuit, in which a phase frequency detector (PFD) circuit is switched from a first mode to provide a control input signal to a charge pump as a pulse signal having a pulse width corresponding to a phase difference between a reference clock signal and a feedback clock signal to a second mode to hold the control input signal at a constant value for a predetermined time in response to detected cycle slip conditions to enhance loop filter current during frequency transitions to reduce lock time for the locking circuit.
摘要翻译：所描述的示例包括控制锁相环（PLL）或其他锁定电路的锁定时间的电路和方法，其中相位频率检测器（PFD）电路从第一模式切换以向电荷泵提供控制输入信号作为脉冲信号具有对应于参考时钟信号和反馈时钟信号之间的相位差的脉冲宽度到第二模式，以响应于检测到的周期滑移条件将控制输入信号保持在恒定值一段预定时间以增强环路在频率转换期间过滤电流，以减少锁定电路的锁定时间。

95. 发明授权

US09503068B1 Supply voltage envelope detection 有权
标题翻译：电源电压包络检测
公开(公告)号：US09503068B1
公开(公告)日：2016-11-22
申请号：US15068003
申请日：2016-03-11
申请人： Apple Inc.
发明人： Joseph T. DiBene, II , Sanjay Pant , Sotirios Zogopoulos , Jafar Savoj , Inder M. Sodhi
IPC分类号： H03D1/00 , H03K5/00 , H03K5/159 , H03L7/06 , G01R19/04
CPC分类号： H03K5/159 , G01R19/04
摘要： In an embodiment, a supply voltage envelope detector circuit is configured to detect a shape of the supply voltage over time and to compare the detected shape to expected shapes that indicate voltage droop events for which corrective action may be needed. The expected shapes may be predetermined based on one or more of: the design of the integrated circuit that includes the supply voltage envelope detector circuit; attributes of the power management unit (PMU) that is to generate the supply voltage for the integrated circuit; and/or attributes of the system that includes the integrated circuit. The shape of the voltage droop may experience little variation during use, and thus may be used to detect a droop event earlier and more accurately than a threshold-based mechanism, in some embodiments.
摘要翻译：在一个实施例中，电源电压包络检测器电路被配置为随时间检测电源电压的形状，并将检测到的形状与指示可能需要校正动作的电压下降事件的预期形状进行比较。预期形状可以基于以下中的一个或多个来预先确定：包括电源电压包络检测器电路的集成电路的设计; 用于生成集成电路的电源电压的电源管理单元（PMU）的属性; 和/或包括集成电路的系统的属性。在一些实施例中，电压下降的形状可能在使用期间几乎没有变化，因此可以用于比基于阈值的机制更早和更准确地检测下垂事件。

96. 发明授权

US09490824B1 Phase-locked loop with frequency bounding circuit 有权
标题翻译：带有频率限制电路的锁相环
公开(公告)号：US09490824B1
公开(公告)日：2016-11-08
申请号：US15000911
申请日：2016-01-19
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Devesh P. Singh , Firas N. Abughazaleh , Anand Kumar Sinha , Sanjay K. Wadhwa
IPC分类号： H03L7/06 , H03L7/089 , H03L7/099
CPC分类号： H03L7/0891 , H03L7/089 , H03L7/093 , H03L7/099
摘要： A phase-locked loop (PLL) for generating an oscillating signal includes a frequency bounding circuit. When a frequency of the oscillating signal is greater than a first threshold value, which is greater than a maximum normal operational frequency of the PLL, the frequency bounding circuit forces a charge pump to discharge a loop filter until the oscillating signal frequency is less than a second threshold value that is within the normal operational frequency range of the PLL. When the frequency of the oscillating signal is less than a third threshold value, which is less than a minimum normal operational frequency of the PLL, the frequency bounding circuit forces the charge pump to charge the loop filter until the oscillating signal frequency is greater than a fourth threshold value that is within the normal operational frequency range of the PLL.
摘要翻译：用于产生振荡信号的锁相环（PLL）包括频率限制电路。当振荡信号的频率大于大于PLL的最大正常工作频率的第一阈值时，频率限制电路迫使电荷泵放电环路滤波器直到振荡信号频率小于在PLL的正常工作频率范围内的第二阈值。当振荡信号的频率小于小于PLL的最小正常工作频率的第三阈值时，频率限制电路迫使电荷泵对环路滤波器充电，直到振荡信号频率大于第四阈值在PLL的正常工作频率范围内。

97. 发明授权

US09490819B2 Auto frequency calibration for a phase locked loop and method of use 有权
标题翻译：锁相环的自动频率校准和使用方法
公开(公告)号：US09490819B2
公开(公告)日：2016-11-08
申请号：US14603900
申请日：2015-01-23
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Yen-Jen Chen , Feng Wei Kuo , Huan-Neng Chen , Chewn-Pu Jou
IPC分类号： H03L7/06 , H03L7/08 , H03L7/10 , H03L7/197 , G04F10/00 , H03L7/085 , H03L7/099 , H03M1/00
CPC分类号： H03L7/0802 , G04F10/005 , H03L7/085 , H03L7/093 , H03L7/0992 , H03L7/101 , H03L7/103 , H03L7/104 , H03L7/1976 , H03L2207/50 , H03M1/002 , H03M3/32
摘要： An apparatus comprises a code generator configured to generate a coarse tuning signal and a reset signal based on a reference frequency and a phase difference signal. The apparatus also comprises a digital loop filter configured to generate a fine tuning signal based on the phase difference signal. The apparatus further comprises a voltage control oscillator configured to generate an output signal based on the coarse tuning signal and the fine tuning signal. The apparatus additionally comprises a divider configured to generate a divider frequency based on a divider control signal and the output signal. The phase difference signal is based, at least in part, on the divider frequency, and the divider is configured to be reset based on the reset signal.
摘要翻译：一种装置，包括代码发生器，其被配置为基于参考频率和相位差信号产生粗调谐信号和复位信号。该装置还包括数字环路滤波器，其配置为基于相位差信号产生微调信号。该装置还包括电压控制振荡器，被配置为基于粗调谐信号和微调信号产生输出信号。该装置还包括分配器，其被配置为基于分频器控制信号和输出信号产生分频器频率。相位差信号至少部分地基于分频器，并且分频器被配置为基于复位信号被复位。

98. 发明授权

US09490818B2 Cancellation of delta-sigma quantization noise within a fractional-N PLL with a nonlinear time-to-digital converter 有权
$Cancellation of delta-sigma quantization noise within a fractional-N PLL with a nonlinear time-to-digital converter$
标题翻译：用非线性时间 - 数字转换器消除小数N PLL内的Δ-sigma量化噪声
公开(公告)号：US09490818B2
公开(公告)日：2016-11-08
申请号：US14448447
申请日：2014-07-31
申请人： Silicon Laboratories Inc.
发明人： Michael H. Perrott
IPC分类号： H03L7/06 , H03L7/08 , H03L7/093 , H03M1/08 , H03M1/66 , G04F10/00 , H03L7/099 , H03M3/00 , H03L7/085 , H02M3/07 , H03M7/30
CPC分类号： H03L7/0802 , G04F10/005 , H02M3/07 , H03L7/085 , H03L7/093 , H03L7/0995 , H03M1/0836 , H03M1/0854 , H03M1/66 , H03M3/358 , H03M3/368 , H03M7/3004
摘要： A fractional-N phase-locked loop (PLL) includes a nonlinear time to digital converter that generates a digital representation of a phase error corresponding to a time difference between a feedback signal of the fractional-N PLL and a reference signal. A nonlinear quantization noise cancellation circuit supplies a correction signal to ensure that the generated digital representation has reduced quantization noise. The correctional signal may be applied in the analog or digital domain.
摘要翻译：分数N锁相环（PLL）包括非线性时间到数字转换器，其产生对应于分数N PLL的反馈信号与参考信号之间的时间差的相位误差的数字表示。非线性量化噪声消除电路提供校正信号以确保生成的数字表示具有降低的量化噪声。校正信号可以应用于模拟或数字域。

99. 发明授权

US09484934B1 Delay lock loop 有权
标题翻译：延迟锁定循环
公开(公告)号：US09484934B1
公开(公告)日：2016-11-01
申请号：US14967865
申请日：2015-12-14
申请人： VIA Alliance Semiconductor Co., Ltd.
发明人： Qiang Si , Fan Jiang
IPC分类号： H03L7/06 , H03L7/085 , H03K5/134 , H03K5/00
CPC分类号： H03L7/085 , H03K5/134 , H03K2005/00019 , H03L7/0814 , H03L7/0816
摘要： A delay lock loop is provided. A delay unit includes a delay factor and delays a first clock signal to generate a second clock signal according to the delay factor. An elimination unit delays a third clock signal to generate a fourth clock signal. A phase detection unit is coupled to the delay unit and the elimination unit and generates an indication signal according to a phase difference between the second and fourth clock signals. A control unit is coupled to the phase detection unit and the delay unit. The control unit controls the delay unit according to the indication signal to adjust the delay factor. When the delay factor is equal to an initial value, an initial time difference occurs between the first and second clock signals. A time difference between the third and fourth clock signals is equal to the initial time difference.
摘要翻译：提供延迟锁定环。延迟单元包括延迟因子并延迟第一时钟信号以根据延迟因子产生第二时钟信号。消除单元延迟第三时钟信号以产生第四时钟信号。相位检测单元耦合到延迟单元和消除单元，并根据第二和第四时钟信号之间的相位差产生指示信号。控制单元耦合到相位检测单元和延迟单元。控制单元根据指示信号控制延迟单元，调整延迟系数。当延迟因子等于初始值时，在第一和第二时钟信号之间产生初始时间差。第三和第四时钟信号之间的时间差等于初始时间差。

100. 发明授权

US09484931B2 Delay locked loop circuit and operation method thereof 有权
标题翻译：延迟锁定环路电路及其运行方法
公开(公告)号：US09484931B2
公开(公告)日：2016-11-01
申请号：US14678683
申请日：2015-04-03
申请人： SK hynix Inc.
发明人： Da-In Im , Young-Suk Seo
IPC分类号： H03L7/06 , H03L7/08 , H03K5/14 , H03K3/017 , H03K5/00
CPC分类号： H03L7/08 , H03K3/017 , H03K5/14 , H03K2005/00019 , H03L7/0812 , H03L7/10
摘要： A delay locked loop (DLL) circuit may include: an input clock control unit suitable for transmitting first and second internal clocks generated based on an external clock, and controlling transmission of the second internal clock based on a clock control signal which is activated during a predetermined period; a clock delay unit suitable for generating a first delay locked clock by delaying the first internal clock by a delay time required for locking, and generating a second delay locked clock by delaying the second internal clock based on the clock control signal; and an output clock control unit suitable for outputting the first delay locked clock and the second delay locked clock during a period in which the clock control signal is activated.
摘要翻译：延迟锁定环路（DLL）电路可以包括：输入时钟控制单元，适于发送基于外部时钟产生的第一和第二内部时钟，并且基于在时钟控制信号期间激活的时钟控制信号来控制第二内部时钟的传输预定期限时钟延迟单元，适于通过将第一内部时钟延迟锁定所需的延迟时间来产生第一延迟锁定时钟，以及通过基于时钟控制信号延迟第二内部时钟来产生第二延迟锁定时钟; 以及输出时钟控制单元，其适于在时钟控制信号被激活的时段期间输出第一延迟锁定时钟和第二延迟锁定时钟。

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