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11. 发明申请

US20050264335A1 Digitally programmable I/Q phase offset compensation 有权
标题翻译：数字可编程I / Q相位补偿
公开(公告)号：US20050264335A1
公开(公告)日：2005-12-01
申请号：US10856075
申请日：2004-05-28
申请人： Zaw Soe
发明人： Zaw Soe
IPC分类号： H03H11/26
CPC分类号： H03H11/265
摘要： Delays are produced in differential signals using a variable capacitance provided by MOS varactors coupled between the differential signals. The capacitance values of the MOS varactors is controlled by a bias voltage applied to the bodies of the varactors. Selective application of bias voltages to the MOS varactors may be employed to selectively delay one pair of differential signals with respect to another pair of differential signals so as to change the relative phases of the signals. A logic circuit may be used to control the application of bias voltage to the MOS varactors so that signal phases may be adjusted in a manner that is predictable and programmable. These methods may be implemented to compensate for phase offsets between in-phase and quadrature signals of a local oscillator.
摘要翻译：使用由差分信号之间耦合的MOS变容二极管提供的可变电容在差分信号中产生延迟。 MOS可变电抗器的电容值由施加到变容二极体的偏置电压来控制。可以选择性地施加偏置电压到MOS可变电抗器，以便相对于另一对差分信号选择性地延迟一对差分信号，以便改变信号的相对相位。可以使用逻辑电路来控制向MOS可变电抗器施加偏置电压，使得可以以可预测和可编程的方式调整信号相位。可以实现这些方法来补偿本地振荡器的同相和正交信号之间的相位偏移。

12. 发明授权

US09143204B2 Direct coupled biasing circuit for high frequency applications 有权
标题翻译：用于高频应用的直接耦合偏置电路
公开(公告)号：US09143204B2
公开(公告)日：2015-09-22
申请号：US13163562
申请日：2011-06-17
申请人： KhongMeng Tham , Zaw Soe
发明人： KhongMeng Tham , Zaw Soe
IPC分类号： H03G3/10 , H04B5/00 , G05F3/16
CPC分类号： H03K3/012 , G05F3/16 , H01Q1/50 , H03K17/56 , H04B5/0075
摘要： This invention eliminates the need for “capacitor coupling” or “transformer coupling,” and the associated undesirable parasitic capacitance and inductance associated with these coupling techniques when designing high frequency (˜60 GHz) circuits. At this frequency, the distance between two adjacent stages needs to be minimized. A resonant circuit in series with the power or ground leads is used to isolate a biasing signal from a high frequency signal. The introduction of this resonant circuit allows a first stage to be “directly coupled” to a next stage using a metallic trace. The “direct coupling” technique passes both the high frequency signal and the biasing voltage to the next stage. The “direct coupling” approach overcomes the large die area usage when compared to either the “AC coupling” or “transformer coupling” approach since neither capacitors nor transformers are required to transfer the high frequency signals between stages.
摘要翻译：当设计高频（〜60GHz）电路时，本发明消除了对“电容器耦合”或“变压器耦合”的需求以及与这些耦合技术相关联的不期望的寄生电容和电感。在这个频率下，两个相邻阶段之间的距离需要最小化。与电源或接地引线串联的谐振电路用于将偏置信号与高频信号隔离开来。该谐振电路的引入允许使用金属迹线将第一级“直接耦合”到下一级。 “直接耦合”技术将高频信号和偏置电压都通过下一级。与“交流耦合”或“变压器耦合”方法相比，“直接耦合”方法克服了大的管芯面积使用，因为既不需要电容器也不需要变压器来在级之间传输高频信号。

13. 发明授权

US08487695B2 Differential source follower having 6dB gain with applications to WiGig baseband filters 有权
标题翻译：具有6dB增益的差分源极跟随器应用于WiGig基带滤波器
公开(公告)号：US08487695B2
公开(公告)日：2013-07-16
申请号：US13243880
申请日：2011-09-23
申请人： Zaw Soe
发明人： Zaw Soe
IPC分类号： H03F3/45
CPC分类号： H03H11/1217 , H03F3/195 , H03F3/301 , H03F3/45179 , H03F3/505 , H03F2203/45528 , H03F2203/45544 , H03F2203/45594 , H03H3/00
摘要： A differential amplifier comprising a first upper device and a first lower device series coupled between two power supplies and a second upper device and a second lower device series coupled between the two power supplies. A first DC voltage enables the first upper device and the second upper device and a second DC voltage regulates current flow in the first lower device and the second lower device. An AC signal component is coupled to the first upper device and the second lower device while the AC signal complement is coupled to the first lower device and the second upper device. A first output signal between the first upper device and the first lower device. Separate RC networks couple the AC signals to their respective device. A first and second output signal forms between the upper device and the lower device, respectively. All the devices are same channel type.
摘要翻译：一种差分放大器，包括耦合在两个电源之间的第一上部装置和第一下部装置系列，以及耦合在两个电源之间的第二上部装置和第二下部装置。第一直流电压使得第一上部装置和第二上部装置能够和第二直流电压调节第一下部装置和第二下部装置中的电流。当AC信号补码耦合到第一下部装置和第二上部装置时，AC信号分量耦合到第一上部装置和第二下部装置。第一上部装置和第一下部装置之间的第一输出信号。单独的RC网络将AC信号耦合到其相应的设备。分别在上部装置和下部装置之间形成第一和第二输出信号。所有设备的通道类型相同。

14. 发明申请

US20130143511A1 Method and Apparatus of an Input Resistance of a Passive Mixer to Broaden the Input Matching Bandwidth of a Common Source/Gate LNA 有权
标题翻译：无源混频器的输入电阻的方法和装置，以扩大公共源/门LNA的输入匹配带宽
公开(公告)号：US20130143511A1
公开(公告)日：2013-06-06
申请号：US13312806
申请日：2011-12-06
申请人： Zaw Soe
发明人： Zaw Soe
IPC分类号： H04B1/16
CPC分类号： H03F1/42 , H03D7/125 , H03D7/1441 , H03D7/1466 , H03D7/165 , H03F1/223 , H03F3/193 , H03F3/387 , H03F3/45071 , H03F3/45179 , H03F2200/108 , H03F2200/294 , H03F2200/451 , H03F2200/492 , H03F2200/72 , H03F2200/75 , H04L27/38
摘要： A cascode common source and common gate LNAs operating at 60 GHz are introduced and described. The cascode common source LNA is simulated to arrive at an optimum ratio of upper device width to the lower device width. The voltage output of the cascode common source LNA is translated into a current to feed and apply energy to the mixer stage. These input current signals apply the energy associated with the current directly into the switched capacitors in the mixer to minimize the overall power dissipation of the system. The LNA is capacitively coupled to the mixer switches in the I and Q mixers and are enabled and disabled by the clocks generated by the quadrature oscillator. These signals are then amplified by a differential amplifier to generate the sum and difference frequency spectra.
摘要翻译：引入并描述了以60GHz操作的共源共栅和公共栅极LNA。对共源共栅源LNA进行模拟，以达到上部器件宽度与较低器件宽度的最佳比例。共源共栅源LNA的电压输出转换为电流以馈送并将能量施加到混频器级。这些输入电流信号将与电流相关联的能量直接施加到混频器中的开关电容器中，以最小化系统的总功耗。 LNA电容耦合到I和Q混频器中的混频器开关，并由正交振荡器产生的时钟使能和禁止。然后，这些信号被差分放大器放大以产生和和差频谱。

15. 发明申请

US20130141178A1 Injection Locked Divider with Injection Point Located at a Tapped Inductor 审中-公开
标题翻译：注射锁定分离器，其注射点位于螺纹电感器上
公开(公告)号：US20130141178A1
公开(公告)日：2013-06-06
申请号：US13312820
申请日：2011-12-06
申请人： Zaw Soe
发明人： Zaw Soe
IPC分类号： H03B5/12
CPC分类号： H03B5/1228 , H03B5/1215 , H03B5/1243 , H03B19/14 , H03B2200/0074
摘要： Injection locked dividers provide a divided clock signal after being driven by a injected clock signal that is a multiple of the divided clock signal. At injected clock signal at 60 GHz generates a differential 30 GHz clock signal. One innovative construction of the injection locked oscillator reduces the internal capacitive at a node by associating the parasitic capacitance at this node with the inductors of the tapped inductor resonant circuit. This provides more energy flow in the injection pulses applied to the legs of the injection locked circuit providing an increase locking range.
摘要翻译：注入锁定分频器在被分配的时钟信号的倍数的注入时钟信号驱动之后提供分频时钟信号。在60 GHz的注入时钟信号产生差分30 GHz时钟信号。注入锁定振荡器的一个创新结构通过将该节点处的寄生电容与抽头电感谐振电路的电感相关联来减少节点处的内部电容。这提供了施加到注射锁定电路的腿部的注射脉冲中提供更多的能量流，从而提供增加的锁定范围。

16. 发明申请

US20190214953A1 HIGH LINEARLY WIGIG BASEBAND AMPLIFIER WITH CHANNEL SELECT FILTER 审中-公开
公开(公告)号：US20190214953A1
公开(公告)日：2019-07-11
申请号：US16352575
申请日：2019-03-13
申请人： Zaw Soe , Kevin Jing , Steve Gao
发明人： Zaw Soe , Kevin Jing , Steve Gao
IPC分类号： H03G1/00 , H03F3/45 , H03H11/12 , H03G5/28
摘要： A circuit comprises a Sallen-Key filter, which includes a source follower that implements a unity-gain amplifier; and a programmable-gain amplifier coupled to the Sallen-Key filter. The circuit enables programmable gain via adjustment to a current mirror copying ratio in the programmable-gain amplifier, which decouples the bandwidth of the circuit from its gain settings. The programmable-gain amplifier can comprise a differential voltage-to-current converter, a current mirror pair, and programmable output gain stages. The Sallen-Key filter and at least one branch in the programmable-gain amplifier can comprise transistors arranged in identical circuit configurations.

17. 发明申请

US20130076434A1 Differential Source Follower having 6dB Gain with Applications to WiGig Baseband Filters 有权
标题翻译：差分源跟随器具有6dB增益，可应用于WiGig基带滤波器
公开(公告)号：US20130076434A1
公开(公告)日：2013-03-28
申请号：US13243880
申请日：2011-09-23
申请人： Zaw Soe
发明人： Zaw Soe
IPC分类号： H03B1/00 , H03F3/45
CPC分类号： H03H11/1217 , H03F3/195 , H03F3/301 , H03F3/45179 , H03F3/505 , H03F2203/45528 , H03F2203/45544 , H03F2203/45594 , H03H3/00
摘要： A Sallen-Key filter requires an operational amplifier with a large input impedance and a small output impedance to meet the external filter characteristics. The operational amplifier requires an internal feedback path for stability that limits performance. This invention eliminates the need for internal feedback and increases the gain of a source follower which has characteristics matching the operational amplifier in the Sallen-Key filter. The source follower provides 6 dB of AC voltage gain and is substituted for the operational amplifier in the Sallen-Key filter. The Sallen-Key filter requires a differential configuration to generate all the required signals with their compliments and uses these signals in a feed forward path. Furthermore, since the source follower uses only two n-channel stacked devices, the headroom voltage is maximized to several hundred millivolts for a 1.2V voltage supply in a 40 nm CMOS technology. Thus, the required 880 MHz bandwidth of the Sallen-Key filter can be easily met using the innovative source follower.
摘要翻译： Sallen-Key滤波器需要具有大输入阻抗和小输出阻抗的运算放大器，以满足外部滤波器特性。运算放大器需要一个内部反馈路径来稳定性，从而限制性能。本发明消除了对内部反馈的需要，并且增加了具有与Sallen-Key滤波器中的运算放大器匹配的特性的源极跟随器的增益。源极跟随器提供6 dB的交流电压增益，并代替Sallen-Key滤波器中的运算放大器。 Sallen-Key滤波器需要差分配置，以产生所有需要的信号，并在前馈路径中使用这些信号。此外，由于源极跟随器仅使用两个n沟道堆叠器件，因此在40nm CMOS技术中，1.2V电压源的裕量电压最大可达数百毫伏。因此，Sallen-Key滤波器所需的880 MHz带宽可以使用创新的源跟踪器轻松实现。

18. 发明申请

US20070155348A1 Apparatus and method for ultra wide band architectures 审中-公开
标题翻译：超宽带架构的装置和方法
公开(公告)号：US20070155348A1
公开(公告)日：2007-07-05
申请号：US11321348
申请日：2005-12-29
申请人： Behzad Razavi , Zaw Soe
发明人： Behzad Razavi , Zaw Soe
IPC分类号： H04B1/04
CPC分类号： H04B1/719 , H04B1/71635
摘要： The present invention describes a transmitter/receiver architecture that uses a Weaver architecture in conjunction with digitally controlled adder/subtractor components to insert/extract a signal into/from the multi-channel system. In the transmitter, the selection of the band select bit causes the up/downconverted IF baseband I and Q signals to insert/extract on either side of an RF LO signal. In addition, the image of the first LO is eliminated while the desired signal is enhanced after passing through this new architecture. The invention also adds an RSSI circuit to the MBOA Weaver architecture receiver architecture to detect whether an 802.11 WLAN signal is interfering with the desired UWB signal. If so, the system is designed to detect this interference and jump to a new frequency range to avoid this interference. This invention focuses on devices that operate over the entire UWB band including the newly formed 60 GHz UWB band system.
摘要翻译：本发明描述了一种使用Weaver架构结合数字控制的加法器/减法器组件来将信号插入/从多通道系统中提取的发射机/接收机体系结构。在发射机中，频带选择位的选择会导致上/下转换的IF基带I和Q信号在RF LO信号的任一侧插入/提取。另外，消除了第一个LO的图像，同时在通过这个新架构之后增强了所需的信号。本发明还向MBOA Weaver架构接收机架构添加了RSSI电路，以检测802.11 WLAN信号是否干扰所需的UWB信号。如果是这样，系统被设计为检测这种干扰并跳转到新的频率范围以避免这种干扰。本发明专注于在包括新形成的60GHz UWB频带系统的整个UWB频带上工作的设备。

19. 发明申请

US20050258989A1 Hybrid DC offset cancellation scheme for wireless receiver 有权
标题翻译：无线接收机的混合直流偏移消除方案
公开(公告)号：US20050258989A1
公开(公告)日：2005-11-24
申请号：US10851307
申请日：2004-05-21
申请人： Kuangyu Li , Song-Nien Tang , Jackie Cheng , Zaw Soe
发明人： Kuangyu Li , Song-Nien Tang , Jackie Cheng , Zaw Soe
IPC分类号： H03M1/06 , H03M1/10 , H03M1/18
CPC分类号： H03M1/1019 , H03M1/18
摘要： Systems and methods for canceling static and dynamic DC offsets by combining a digital DC offset correction scheme with an analog DC offset correction scheme. A feedback-based digital DC offset correction scheme provides different adjustment levels for a plurality of discrete gain states and the analog DC offset correction scheme operates in different cancellation modes dependent on a frame structure. A digital DC offset correction scheme collects DC offset control information and provides adjustment levels. In addition, a negative-feedback based switchable high pass filter has a plurality modes of operation, where one mode of operation includes an all-pass filter.
摘要翻译：通过组合数字直流偏移校正方案和模拟直流偏移校正方案来消除静态和动态直流偏移的系统和方法。基于反馈的数字DC偏移校正方案为多个离散增益状态提供不同的调整电平，并且模拟DC偏移校正方案根据帧结构在不同的取消模式下操作。数字DC偏移校正方案收集直流偏移控制信息并提供调整电平。此外，基于负反馈的可切换高通滤波器具有多种操作模式，其中一种操作模式包括全通滤波器。

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