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11. 发明申请

US20110317747A1 TRANSMITTING APPARATUS, RECEIVING APPARATUS, TRANSMITTING/RECEIVING SYSTEM, AND IMAGE DISPLAY SYSTEM 有权
标题翻译：发送装置，接收装置，发送/接收系统和图像显示系统
公开(公告)号：US20110317747A1
公开(公告)日：2011-12-29
申请号：US13148856
申请日：2010-10-20
申请人： Seiichi Ozawa , Hironobu Akita
发明人： Seiichi Ozawa , Hironobu Akita
IPC分类号： H04B1/38
CPC分类号： H04L7/10 , G09G3/2096 , G09G3/3611 , G09G2370/08 , G09G2370/14 , H04L7/0008 , H04L7/0091 , H04L7/0337
摘要： A data reception unit 21 of a reception device 20n receives calibration data to detect a data reception state or a clock reception state in the reception device 20n from a data transmission unit 11 of a transmission device 10. A decoder unit 24 causes a transmission unit 26 to send out calibration sample data that a sampler unit 23 obtained by sampling calibration data to the transmission device 10. A control unit 15 of the transmission device 10 detects a data reception state or a clock reception state in the reception device 20n based on calibration sample data received from the reception device 20n and controls the data transmission unit 11 and a clock transmission unit 12 based on the detection result.
摘要翻译：接收装置20n的数据接收单元21从发送装置10的数据发送单元11接收校准数据以检测接收装置20n中的数据接收状态或时钟接收状态。解码器单元24使发送单元26 发送通过将校准数据采样获得的采样器单元23的校准样本数据发送到发送设备10.发送设备10的控制单元15基于校准样本来检测接收设备20n中的数据接收状态或时钟接收状态从接收装置20n接收到的数据，并根据检测结果控制数据发送部11和时钟发送部12。

12. 发明授权

US06731149B2 Synchronizing circuit for generating a signal synchronizing with a clock signal 失效
标题翻译：用于产生与时钟信号同步的信号的同步电路
公开(公告)号：US06731149B2
公开(公告)日：2004-05-04
申请号：US10003312
申请日：2001-12-06
申请人： Katsuaki Isobe , Tsuneo Inaba , Hironobu Akita
发明人： Katsuaki Isobe , Tsuneo Inaba , Hironobu Akita
IPC分类号： H03K501
CPC分类号： H03K5/135 , H03K5/133 , H03L7/00
摘要： A first delay line for forward pulses and a second delay line for backward pulses are composed of unit delay elements. A state holding section determines the input position of a backward pulse on the second delay line according to the transfer position of a forward pulse transferred along the first delay line. In the unit delay elements constituting the first and second delay lines, the accuracy of synchronization can be improved by increasing the current driving capability of the transistors related to the rising of the pulse signal.
摘要翻译：用于正向脉冲的第一延迟线和用于反向脉冲的第二延迟线由单位延迟元件组成。状态保持部根据沿着第一延迟线传送的正向脉冲的传送位置来确定第二延迟线上的反向脉冲的输入位置。在构成第一和第二延迟线的单位延迟元件中，可以通过增加与脉冲信号的上升相关的晶体管的电流驱动能力来提高同步精度。

13. 发明授权

US06337834B1 Synchronous signal generation circuit 有权
标题翻译：同步信号发生电路
公开(公告)号：US06337834B1
公开(公告)日：2002-01-08
申请号：US09706842
申请日：2000-11-07
申请人： Katsuaki Isobe , Hironobu Akita , Satoshi Eto , Haruki Toda
发明人： Katsuaki Isobe , Hironobu Akita , Satoshi Eto , Haruki Toda
IPC分类号： G11C800
CPC分类号： G11C7/225 , G11C7/22 , G11C7/222
摘要： The present invention provides a synchronous signal generation circuit that can be operated with a high accuracy, at a high speed and with a low power consumption without being affected by the process dispersion. The synchronous signal generation circuit of the present invention comprises a real circuit including an input receiver, an off-chip driver, and a mirror-type synchronous circuit, and a dummy circuit for determining the delay time in the mirror-type synchronous circuit, the dummy circuit including an input receiver and an off-chip driver. In the dummy circuit, the input signal is supplied first to the off-chip driver and, then, to the input receiver so as to permit the signal between the off-chip driver and the input receiver to be a small amplitude signal. It follows that the real circuit and the dummy circuit are equal to each other in the signal levels in the input and output portions of each of the input receiver and the off-chip driver. The particular construction makes it possible to minimize the error in the delay time between the real circuit and the dummy circuit relative to the process dispersion so as to improve the synchronizing accuracy and, thus, to achieve a high speed I/O.
摘要翻译：本发明提供一种同步信号发生电路，其能够以高精度，高速度且低功耗地操作，而不受处理分散的影响。本发明的同步信号发生电路包括实际电路，其包括输入接收器，片外驱动器和反射镜型同步电路，以及用于确定镜式同步电路中的延迟时间的虚拟电路，虚拟电路包括输入接收器和片外驱动器。在虚拟电路中，首先将输入信号提供给片外驱动器，然后提供给输入接收器，以允许片外驱动器和输入接收器之间的信号为小振幅信号。因此，实际电路和虚拟电路在每个输入接收器和片外驱动器的输入和输出部分的信号电平中彼此相等。该特定结构使得可以将实际电路和虚拟电路之间相对于处理色散的延迟时间的误差最小化，从而提高同步精度，从而实现高速I / O。

14. 发明授权

US06292411B1 Delay control circuit synchronous with clock signal 失效
标题翻译：延时控制电路与时钟信号同步
公开(公告)号：US06292411B1
公开(公告)日：2001-09-18
申请号：US09537424
申请日：2000-03-27
申请人： Masahiro Kamoshida , Hironobu Akita
发明人： Masahiro Kamoshida , Hironobu Akita
IPC分类号： G11C700
CPC分类号： G11C7/222 , G11C7/22 , H03K5/135 , H04L7/0008 , H04L7/0037
摘要： A delay line for forward pulse has a plurality of delay units for forward pulse. A delay line for backward pulse has a plurality of delay units for backward pulse. In the delay line for backward pulse, a pulse signal is propagated in an opposite direction to a direction of the propagation in the delay line for forward pulse. A direction from an input terminal to an output terminal in the delay units for forward pulse is set to be parallel to a direction of the delay line for forward pulse. A direction from an input terminal to an output terminal in the delay units for backward pulse is set to be parallel to a direction of the delay line for backward pulse. The directions from the input terminal to the output terminal in two adjacent ones of the delay units for forward pulse are set to be opposite to one another. The directions from the input terminal to the output terminal in two adjacent ones of the delay units for backward pulse are set to be opposite to one another.
摘要翻译：用于正向脉冲的延迟线具有用于正向脉冲的多个延迟单元。用于反向脉冲的延迟线具有用于反向脉冲的多个延迟单元。在用于反向脉冲的延迟线中，脉冲信号在与正向脉冲的延迟线中的传播方向相反的方向上传播。用于正向脉冲的延迟单元中的从输入端子到输出端子的方向设置为与正向脉冲的延迟线的方向平行。用于反向脉冲的延迟单元中的从输入端子到输出端子的方向设置为与用于反向脉冲的延迟线的方向平行。从正向脉冲的两个相邻延迟单元中的输入端子到输出端子的方向被设定为彼此相反。在后向脉冲的两个相邻的延迟单元中从输入端子到输出端子的方向被设定为彼此相反。

15. 发明授权

US5886942A Word line driver and semiconductor device 失效
标题翻译：字线驱动器和半导体器件
公开(公告)号：US5886942A
公开(公告)日：1999-03-23
申请号：US964398
申请日：1997-11-06
申请人： Hironobu Akita
发明人： Hironobu Akita
IPC分类号： G11C11/407 , G11C8/08 , G11C11/408 , H01L21/8242 , H01L27/108 , G11C8/00
CPC分类号： G11C8/08 , G11C11/4085
摘要： A word line driver includes a CMOS inverter constituted by a P channel MOS transistor in which a row decode signal having the amplitude of an internal logic power supply voltage is supplied to a gate, one end of the source-drain current path is connected to a node to which a power supply voltage (VWLh) is applied, and the other end of the source-drain current path is connected to a word line, and an N channel MOS transistor in which the input signal is supplied to a gate, one end of the source-drain current path is connected to a node to which a power supply voltage (VWLl) having a negative value is applied, and the other end of the source-drain current path is connected to the word line. The circuit threshold voltage of the CMOS inverter is set to be larger than the circuit threshold voltages of other CMOS inverters which operate using internal logic power supply voltages.
摘要翻译：字线驱动器包括由P沟道MOS晶体管构成的CMOS反相器，其中具有内部逻辑电源电压的幅度的行解码信号被提供给栅极，源极 - 漏极电流路径的一端连接到施加电源电压（VWLh）的节点，源极 - 漏极电流路径的另一端连接到字线，并且其中输入信号被提供给栅极的N沟道MOS晶体管，一端源极 - 漏极电流路径连接到其上施加了负值的电源电压（VWL1）的节点，并且源极 - 漏极电流路径的另一端连接到字线。将CMOS反相器的电路阈值电压设置为大于使用内部逻辑电源电压工作的其他CMOS反相器的电路阈值电压。

16. 发明授权

US09735810B2 Transmitting device, receiving device and transmitting/receiving system 有权
公开(公告)号：US09735810B2
公开(公告)日：2017-08-15
申请号：US13519804
申请日：2011-06-02
申请人： Hironobu Akita
发明人： Hironobu Akita
IPC分类号： H04L7/04 , H04B1/04 , H04L7/033 , H04L7/00 , H04B15/02 , H04B15/04
摘要： A transmitting device has a transmission data generating part and an output buffer part. The transmission data generating part transmits a data and a clock, which are to be transmitted to a receiving device, and outputs them to the output buffer part. The output buffer part includes a data transmitting part and a clock transmitting part. The clock transmitting part generates and transmits a clock intermittently phase-shifted. The data transmitting part transmits the data in sync with the clock transmitted from the clock transmitting part.

17. 发明授权

US09584228B2 Clock control circuit and transmitter 有权
标题翻译：时钟控制电路和变送器
公开(公告)号：US09584228B2
公开(公告)日：2017-02-28
申请号：US12747807
申请日：2009-12-09
申请人： Hironobu Akita
发明人： Hironobu Akita
IPC分类号： H04B15/04
CPC分类号： H04B15/04 , H04B2215/067
摘要： A transmitter 1 comprises a clock generation portion 4, FIFO portion 6, and serial signal creation portion 7. The clock generation portion 4 performs modulation by spectrum spreading of a reference clock CKref, and generates a first clock CK1 with a high modulation factor and a second clock CK2 with a low modulation factor. The FIFO portion 6 takes as inputs the first clock CK1 which has been output from the clock generation portion 4 to a data generation portion 2 and output from the data generation portion 2, a parallel data signal which has been synchronized with the first clock CK1 in the data generation portion 2 and output, and the second clock CK2 output from the clock generation portion 4, and synchronizes the parallel data signal Pdata with the second clock CK2 and outputs the parallel data signal Pdata. The serial signal creation portion 7 converts a parallel data signal PRdata into a serial data signal Sdata.
摘要翻译：发射机1包括时钟产生部分4，FIFO部分6和串行信号产生部分7.时钟产生部分4通过参考时钟CKref的频谱扩展执行调制，并产生具有高调制因数的第一时钟CK1和具有低调制因子的第二时钟CK2。 FIFO部分6将已经从时钟产生部分4输出的第一时钟CK1作为输入，作为数据生成部分2输出，并从数据生成部分2输出与第一时钟CK1同步的并行数据信号数据产生部分2和从时钟产生部分4输出的第二时钟CK2，并行并行数据信号Pdata与第二时钟CK2并输出并行数据信号Pdata。串行信号产生部分7将并行数据信号PRdata转换为串行数据信号Sdata。

18. 发明申请

US20100266080A1 TRANSMISSION DEVICE, RECEIVING DEVICE AND COMMUNICATION SYSTEM 有权
标题翻译：传输设备，接收设备和通信系统
公开(公告)号：US20100266080A1
公开(公告)日：2010-10-21
申请号：US12808598
申请日：2009-10-27
申请人： Hironobu Akita , Seiichi Ozawa , Yohei Ishizone , Satoshi Miura
发明人： Hironobu Akita , Seiichi Ozawa , Yohei Ishizone , Satoshi Miura
IPC分类号： H04L7/04
CPC分类号： H04L7/10 , G09G5/008 , H03L7/095 , H04L7/033 , H04L7/046
摘要： Provided are a transmission device, a receiving device, and a communication system having a simple configuration and capable of reliably executing the confirmation of a changed bit rate. The communication system 1 sends, to the receiving device 3, a serial data signal Sdata that is set as a constant value across a period of a constant multiple of a cycle of the clock when a bit rate of a serial data signal Sdata in the transmission device 2 is changed. The receiving device 3 that received the serial data signal Sdata receives training data Tdata from the transmission device 2 when it is determined that the serial data signal Sdata is a constant value across a period of a constant multiple of a cycle of the clock, and proceeds to the processing of confirming the changed bit rate.
摘要翻译：提供具有简单配置并能够可靠地执行改变的比特率的确认的传输设备，接收设备和通信系统。通信系统1向发送装置3发送串行数据信号Sdata，该串行数据信号Sdata在传输中的串行数据信号Sdata的比特率时，在时钟的周期的恒定倍数的周期内被设定为恒定值设备2更改。接收到串行数据信号Sdata的接收装置3当确定串行数据信号Sdata在时钟的周期的恒定倍数的周期内是恒定值时，从发送装置2接收训练数据Tdata，并且进行以确认改变的比特率的处理。

19. 发明授权

US06552357B2 Semiconductor memory device having plate lines and precharge circuits 失效
公开(公告)号：US06552357B2
公开(公告)日：2003-04-22
申请号：US10077899
申请日：2002-02-20
申请人： Hironobu Akita
发明人： Hironobu Akita
IPC分类号： H01L2906
CPC分类号： H01L27/10897 , G11C7/12 , G11C11/4074 , G11C11/4094
摘要： A dynamic semiconductor memory device includes memory cells each having a one-transistor/one-capacitor. The memory cells are arranged at their respective intersections of bit lines and word lines. Bit-line precharge circuits are provided at bit line pairs, respectively, to precharge and equalize the bit line pairs. An output potential of a plate potential generator is applied to the power supply terminals of the bit-line precharge circuits. The memory cells have a plurality of capacitors. A plate electrode of the capacitors are connected in common. An insulation film is formed on the plate electrode and a wiring layer is formed on the insulation film. The wiring layer is electrically connected to the plate electrode through a via hole formed in the insulation film and connected in common to the power supply terminals of the bit-line precharge circuits through a contact hole formed in the insulation film, thereby transmitting a potential in proportion to variations in plate potential.

20. 发明授权

US06438059B2 Fuse programming circuit for programming fuses 失效
标题翻译：用于编程保险丝的保险丝编程电路
公开(公告)号：US06438059B2
公开(公告)日：2002-08-20
申请号：US09874208
申请日：2001-06-06
申请人： Hironobu Akita , Kenji Tsuchida
发明人： Hironobu Akita , Kenji Tsuchida
IPC分类号： G11C700
CPC分类号： H01L27/0817
摘要： A fuse is programmed by being supplied with a current. The fuse is connected to a thyristor. A control circuit is connected to the gate of the thyristor. The control circuit turns the thyristor ON to allow the fuse to be programmed.
摘要翻译：通过提供电流来编程保险丝。保险丝连接到晶闸管。控制电路连接到晶闸管的栅极。控制电路将晶闸管导通，以使熔丝被编程。

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