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11. 发明授权

US07196563B2 Comparator and AD conversion circuit having hysteresis circuit 失效
标题翻译：具有迟滞电路的比较器和AD转换电路
公开(公告)号：US07196563B2
公开(公告)日：2007-03-27
申请号：US11061224
申请日：2005-02-18
申请人： Hirofumi Yuki , Yasunori Kawamura
发明人： Hirofumi Yuki , Yasunori Kawamura
IPC分类号： H03K3/00
CPC分类号： H03K5/2481 , H03K5/249 , H03M1/0845 , H03M1/365
摘要： A comparator is provided, which compares an input voltage and a reference voltage by using a plurality of inverting circuits connected in series. The comparator includes a first inverting circuit, a second inverting circuit, a feedback path, and a capacitor arranged on the feedback path. The first inverting circuit inverts a difference between the input voltage and the reference voltage for output. The second inverting circuit further inverts the output of the first inverting circuit for output. The feedback path feeds back the output of the second inverting circuit to the input side of the first inverting circuit. The capacitor causes hysteresis such that an increasing threshold and a decreasing threshold of the second inverting circuit corresponding to an increase and a decrease of the input voltage have a difference therebetween.
摘要翻译：提供比较器，其通过使用串联连接的多个反相电路来比较输入电压和参考电压。比较器包括第一反相电路，第二反相电路，反馈路径和布置在反馈路径上的电容器。第一反相电路将输入电压和参考电压之间的差值反相输出。第二反相电路还使第一反相电路的输出反相输出。反馈路径将第二反相电路的输出反馈到第一反相电路的输入侧。电容器引起迟滞，使得对应于输入电压的增加和减小的第二反相电路的增加的阈值和减小的阈值之间具有差异。

12. 发明授权

US06989779B2 Semiconductor device having DAC channels for video signals 有权
公开(公告)号：US06989779B2
公开(公告)日：2006-01-24
申请号：US10146384
申请日：2002-05-14
申请人： Jun Sasaki , Yasunori Kawamura
发明人： Jun Sasaki , Yasunori Kawamura
IPC分类号： H03M1/66 , H04N5/21
CPC分类号： H04N9/64
摘要： A semiconductor device has a multiplicity of DAC channels for performing digital-to-analog conversion of video signals. Signal processing means for delaying processing of signals by a predetermined delay time is provided in at least one DAC channel. The signal processing means functions as a phase inversion means to reduce cross talks between the DAC channels. The signal processing means also functions as a delay circuit to reduce voltage fluctuations in the power supply.

13. 发明授权

US06667702B2 Semiconductor device having DACs and method of testing such semiconductor device 有权
公开(公告)号：US06667702B2
公开(公告)日：2003-12-23
申请号：US10127197
申请日：2002-04-19
申请人： Jun Sasaki , Yasunori Kawamura
发明人： Jun Sasaki , Yasunori Kawamura
IPC分类号： H03M106
CPC分类号： H03M1/108 , H03M1/66
摘要： A semiconductor device equipped with a DAC channel has a test pattern generation means for storing and generating test patters, and a test clock input terminal. The test pattern generation means generates a test digital signal representing a test pattern based on the high-frequency (e.g. 135 MHz) test clock input to the test clock input terminal. The test digital signal is supplied to the input end of the DAC channel. Using the test digital signals supplied from the test signal generation means, the semiconductor device can be tested in various high-frequency test modes without any tester outputting high-frequency test signals.

14. 发明授权

US5912714A Clock generator for a video signal processing apparatus 失效
标题翻译：时钟发生器，用于视频信号处理装置
公开(公告)号：US5912714A
公开(公告)日：1999-06-15
申请号：US869211
申请日：1997-06-04
申请人： Yasunori Kawamura
发明人： Yasunori Kawamura
IPC分类号： G09G1/16 , G09G5/18 , H03L7/18 , H04N5/06 , H04N5/073 , H04N5/12 , H04N5/46 , H04N7/01 , H04N9/44 , H04N9/475 , H04N9/64 , H04N9/65
CPC分类号： H04N9/642 , H04N5/06 , H04N5/073 , H04N5/46 , H04N9/641 , G09G1/16 , G09G5/18 , H04N5/126
摘要： A signal processing apparatus has a clock generator that generates a clock in accordance with the rate at which picture elements are scanned. The clock generator includes a first frequency divider for dividing the output frequency of a voltage-controlled oscillator for generating the clock, a second frequency divider for dividing the output frequency of a reference frequency oscillator, a phase comparator for comparing phases between the outputs of the first and second frequency dividers, means for applying the output of the phase comparator to the reference frequency oscillator as a control signal, and a third frequency divider for performing voltage division on the output of the voltage-controlled oscillator to obtain the clock. The clock obtained has a frequency determined as: ##EQU1## where M, N, and P represent the frequency-division ratios of the first, second, and third frequency dividers, respectively, and f.sub.x represents the reference frequency.
摘要翻译：信号处理装置具有根据扫描图像元素的速率产生时钟的时钟发生器。时钟发生器包括用于分压用于产生时钟的压控振荡器的输出频率的第一分频器，用于分频参考频率振荡器的输出频率的第二分频器，用于比较基准频率振荡器的输出之间的相位的相位比较器第一和第二分频器，用于将相位比较器的输出作为控制信号施加到参考频率振荡器的装置，以及用于对压控振荡器的输出进行分压以获得时钟的第三分频器。获得的时钟的频率确定为：其中M，N和P分别表示第一，第二和第三分频器的分频比，fx表示参考频率。

15. 发明授权

US08921240B2 Ion implantation method 有权
标题翻译：离子注入法
公开(公告)号：US08921240B2
公开(公告)日：2014-12-30
申请号：US13428481
申请日：2012-03-23
申请人： Yasunori Kawamura , Kyoko Kawakami , Yoshiki Nakashima
发明人： Yasunori Kawamura , Kyoko Kawakami , Yoshiki Nakashima
IPC分类号： H01L21/469 , H01L21/265 , H01J37/08 , H01J37/317
CPC分类号： H01L21/2658 , H01J37/08 , H01J37/3171 , H01J2237/006 , H01L21/26506
摘要： An ion implantation method includes generating CmHy+ ions (m is such an integer as 4≦m≦6, and y is such an integer as 1≦y≦2m+2) using an ion generating material expressed by CnHx (n is such an integer as 4≦n≦6, and x is such an integer as 1≦x≦2n+2), and implanting the ions into a wafer.
摘要翻译：使用由CnHx表示的离子发生材料（n是这样的整数），生成CmHy +离子（m为4＆nlE; m＆nlE; 6的整数，y为1＆nlE; y＆nlE; 2m + 2的整数）作为4＆nlE; n＆nlE; 6，x是1＆nlE; x＆nlE; 2n + 2的整数），并将离子注入晶片。

16. 发明授权

US06703876B2 Reference clock generation system and device 有权
标题翻译：参考时钟生成系统和设备
公开(公告)号：US06703876B2
公开(公告)日：2004-03-09
申请号：US10078232
申请日：2002-02-15
申请人： Masayu Fujiwara , Yasunori Kawamura
发明人： Masayu Fujiwara , Yasunori Kawamura
IPC分类号： H03L706
CPC分类号： H03L7/23 , Y10S331/02
摘要： A clock generation system having a multiplicity of PLL circuit stages connected in series such that frequency division ratios are distributed over the respective PLL circuit stages to attain the predetermined ratio, with the first PLL circuit stage receiving the first clock and the last PLL circuit stage outputting the second clock. The frequency division ratios distributed such that, at least in the PLL circuit stages other than the first stage, the S/N ratios of the respective PLL circuit stages are smaller than the S/N ratio of the noise floor associated with the clock generation system.
摘要翻译：一种具有多个PLL电路级的时钟发生系统，其串联连接使得分频比分布在各个PLL电路级上以达到预定比率，第一PLL电路级接收第一时钟和最后一个PLL电路级输出第二个时钟。分频比分布成使得至少在第一级以外的PLL电路级中，各个PLL电路级的S / N比小于与时钟发生系统相关联的本底噪声的S / N比。

17. 发明授权

US06486572B1 Semiconductor integrated circuit device with a stable operating internal circuit 失效
标题翻译：半导体集成电路器件具有稳定的工作内部电路
公开(公告)号：US06486572B1
公开(公告)日：2002-11-26
申请号：US09656422
申请日：2000-09-06
申请人： Yasunori Kawamura
发明人： Yasunori Kawamura
IPC分类号： H02J900
CPC分类号： H03K17/162 , H03K19/00384 , Y10T307/461
摘要： A semiconductor integrated circuit device has an output circuit composed of a P-channel transistor whose source is connected to a terminal for receiving a supplied voltage and an N-channel transistor whose source is connected to a terminal for receiving a ground voltage, with the node between the drains of the two transistors used as the output terminal of the output circuit. A capacitive circuit element is connected between the sources of the two transistors, and thus in parallel with the output circuit, so as to suppress variations that occur in the current supplied from the supplied power as a result of a current being fed through the output circuit to or from a load connected to the output terminal. This helps keep constant the voltage that is supplied to an internal circuit that is connected in parallel with the output circuit, and thereby stabilize the operation of the internal circuit.
摘要翻译：半导体集成电路器件具有由P沟道晶体管构成的输出电路，其源极连接到用于接收供电电压的端子和源极连接到用于接收接地电压的端子的N沟道晶体管，节点在两个晶体管的漏极之间用作输出电路的输出端。电容电路元件连接在两个晶体管的源极之间，并且因此与输出电路并联，以便抑制由于通过输出电路馈送的电流而在供电电源中提供的电流中发生的变化连接到输出端子的负载。这有助于保持提供给与输出电路并联的内部电路的电压，从而稳定内部电路的工作。

18. 发明授权

US6139017A Premium-dispensing game 有权
标题翻译：优质游戏
公开(公告)号：US6139017A
公开(公告)日：2000-10-31
申请号：US195576
申请日：1998-11-10
申请人： Yasunori Kawamura
发明人： Yasunori Kawamura
IPC分类号： G07F17/34 , A63F9/00
CPC分类号： G07F17/34 , G07F17/3253 , G07F17/3295
摘要： A self-contained game is provided wherein a player attempts to win one of a plurality of premiums displayed within the game. The game includes a premium-display space surrounded by a first plurality and second plurality of indicators. The indicators may be incandescent lamps. A controller is provided which is configured to sequentially distinguish and extinguish individual indicators comprising said first and second pluralities in a manner to give the appearance of a single indication traveling amongst said first and second plurality of indicators. A player may arrest the apparent motion of said traveling indication by actuating an interface device in an attempt to stop the indication at a selected position corresponding to one of the indicators comprising the second plurality of indicators. The controller is configured to determine which indicator was last distinguished at the time the interface was actuated, and whether the last distinguished indicator is a member of the second plurality. The controller is further configured to make a decision whether a premium is to be dispensed based on the determination that said last distinguished indicator is a member of the second plurality of indicators. A plurality of premium supports are positioned within the premium display space and are configured to releasably support premiums within the display space. Each of the supports is associated with a respective one of the second plurality of indicators so that upon the controller making a decision that a premium is to be dispensed, the controller acts to cause the premium support associated with the last distinguished indicator to release a premium.
摘要翻译：提供了一种独立游戏，其中玩家尝试赢得游戏中显示的多个保险费之一。游戏包括由第一多个和第二多个指示符包围的高级显示空间。指标可能是白炽灯。提供了一种控制器，其被配置为以使得在所述第一和第二多个指示器中行进的单个指示的出现的顺序区分和消除包括所述第一和第二多个的各个指示符。玩家可以通过启动接口设备来阻止所述旅行指示的明显动作，以试图在对应于包括第二多个指示符的指示符之一的选定位置停止指示。控制器被配置为确定在接口被启动时最后识别哪个指示符，以及最后的识别指示符是否是第二个的成员。控制器还被配置为基于所述上一个识别指示符是第二多个指示符的成员的确定来决定是否要分发溢价。多个高级支架位于高级显示空间内并且被配置为可释放地支撑显示空间内的溢价。每个支撑件与第二多个指示器中的相应一个指示器相关联，使得在控制器做出要分配溢价的决定时，控制器用于使与最后识别的指示符相关联的溢价支持释放溢价。

19. 发明授权

US5959679A Scan converter for converting a video signal for a television receiver 失效
标题翻译：用于转换电视接收机的视频信号的扫描转换器
公开(公告)号：US5959679A
公开(公告)日：1999-09-28
申请号：US951520
申请日：1997-10-16
申请人： Yasunori Kawamura
发明人： Yasunori Kawamura
IPC分类号： H04N9/00 , G09G1/16 , G09G5/00 , G09G5/391 , H04N7/01 , H04N9/44 , H04N9/64
CPC分类号： H04N7/01 , H04N9/641
摘要： A scan converter converts horizontal and vertical synchronizing signals and digital R, G, and B signals fed from a computer into a television signal through digital processing that is performed by an encoder at a rate of 4.times.fsc (where fsc represents the frequency of the chrominance subcarrier of the television signal). The scan converter has a line memory which temporarily stores the digital signals from the computer to supply the digital signals to the encoder at the rate of 4.times.fsc.
摘要翻译：扫描转换器通过数字处理将水平和垂直同步信号以及从计算机馈送的数字R，G和B信号转换成电视信号，数字处理由编码器以4xfsc的速率执行（其中fsc表示色度副载波的频率的电视信号）。扫描转换器具有行存储器，其临时存储来自计算机的数字信号，以4xfsc的速率将数字信号提供给编码器。

20. 发明授权

US5412482A Signal line changeover circuit with emitter followers 失效
标题翻译：具有发射极跟随器的信号线切换电路
公开(公告)号：US5412482A
公开(公告)日：1995-05-02
申请号：US841164
申请日：1992-02-25
申请人： Shinji Kamei , Yasunori Kawamura
发明人： Shinji Kamei , Yasunori Kawamura
IPC分类号： H03K17/00 , G11B15/12 , H03K17/16 , H03K17/62 , H04N9/79 , H04N9/793 , H04N9/83 , H04N5/782 , H04N5/262
CPC分类号： H04N9/793 , G11B15/125 , H03K17/16 , H03K17/6257 , H04N9/79 , H04N9/83
摘要： A signal line changeover circuit includes a first signal processing block having a first emitter follower for outputting a signal, a second signal processing block having a second emitter follower for outputting a signal, and a switch block having a first terminal connected to an output terminal of the first emitter follower through a first signal line, a second terminal connected to an output terminal of the second emitter follower through a second signal line, a third terminal for outputting a signal, a selection switch for alternatively connecting the first and second terminals to the third terminal, a first switch connected between the first terminal and a power line and turned on when the selection switch selects the second terminal and a second switch connected between the second terminal and the power line and turned on when the selection switch selects the first terminal.
摘要翻译：信号线切换电路包括具有用于输出信号的第一射极跟随器的第一信号处理块，具有用于输出信号的第二射极跟随器的第二信号处理块，以及具有连接到输出端的输出端的第一端子的开关块通过第一信号线的第一射极跟随器，通过第二信号线连接到第二射极跟随器的输出端的第二端子，用于输出信号的第三端子，用于将第一和第二端子交替连接到选择开关的选择开关第三端子，连接在第一端子和电力线之间的第一开关，并且当选择开关选择第二端子时接通，以及连接在第二端子和电力线之间的第二开关，并且当选择开关选择第一端子时，。

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