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11. 发明授权

US5844509A Synchronous read channel employing a data randomizer 失效
标题翻译：采用数据随机化器的同步读通道
公开(公告)号：US5844509A
公开(公告)日：1998-12-01
申请号：US820926
申请日：1997-03-19
申请人： Richard T. Behrens , Trent Dudley , Neal Glover
发明人： Richard T. Behrens , Trent Dudley , Neal Glover
IPC分类号： G11B5/012 , G11B5/09 , G11B20/10 , G11B20/12 , G11B20/14 , G11B20/18 , G11B27/30 , H03M13/31 , H03M7/46
CPC分类号： G11B20/10055 , G11B20/10 , G11B20/10009 , G11B20/1403 , G11B20/1426 , G11B20/18 , G11B27/3027 , G11B5/012 , G11B5/09 , H03M13/31 , G11B20/1258 , G11B2020/1476
摘要： A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. The read channel employs a Data Randomizer which processes unencoded user data to insure that the channel bit patterns with worst-case pattern sensitivity occur no more frequently than would be expected from random user data. The Data Randomizer employs two linear feedback shift registers: one generates a 63-bit sequence which is EXLUSIVE-OR-ed against the MSB of each pair of data bits, the other generates a 127-bit sequence which is EXCLUSIVE-OR-ed against the LSB of each pair of data bits. The Data Randomizer does not affect error propagation. When the Data Randomizer is enabled, the probability of encountering any specific pattern of length n channel bits at a randomly selected location within encoded data is approximately 1/2.sup.n.
摘要翻译：公开了一种同步读通道，其从位于磁盘介质上的磁读头读取模拟读信号，根据所需的部分响应对采样值进行滤波，从滤波后的采样值中提取定时信息，并检测估计数据序列使用离散时间序列检测器从滤波后的样本值。读通道采用数据随机化器，其处理未编码的用户数据，以确保具有最坏情况模式灵敏度的信道位模式不会比从随机用户数据预期的更频繁地发生。数据随机化器采用两个线性反馈移位寄存器：一个产生一个63位的序列，它与每对数据位的MSB相对而言是EXLUSIVE-OR-，另一个产生一个127位的序列，它是独占每对数据位的LSB。 Data Randomizer不影响错误传播。当启用数据随机器时，在编码数据内随机选择的位置遇到长度为n个通道位的任何特定模式的概率大约为+ E，fra 1/2 + EE n。

12. 发明授权

US5297184A Gain control circuit for synchronous waveform sampling 失效
标题翻译：用于同步波形采样的增益控制电路
公开(公告)号：US5297184A
公开(公告)日：1994-03-22
申请号：US12049
申请日：1993-02-01
申请人： Richard T. Behrens , Trent Dudley , Neal Glover
发明人： Richard T. Behrens , Trent Dudley , Neal Glover
IPC分类号： G11B5/09 , G11B20/10 , H03G3/20 , H04L27/08
CPC分类号： H03G3/001 , G11B20/10009 , H03G3/3036
摘要： A mixed analog and digital gain control circuit for controlling the amplitude of an analog input signal. The circuit has a variable gain amplifier that receives the signal from a read/write recording head preamplifier. The output of the variable gain amplifier is connected through a multiplexer and equalizer to an analog to digital converter for converting the analog signal to digital sample values at controlled sampling times. A gain control circuit receives the digital values and the output of a pulse detector indicating when a pulse has occurred. A gain error detector within the gain control circuit determines the amount of error in the amplitude of each detected pulse, and this error amount is filtered and sent through a digital to analog converter and then through an exponentiating circuit. The output of the exponentiating circuit is connected to a gain control input of the variable gain amplifier.
摘要翻译：一种混合的模拟和数字增益控制电路，用于控制模拟输入信号的幅度。该电路具有可变增益放大器，其接收来自读/写记录头前置放大器的信号。可变增益放大器的输出通过多路复用器和均衡器连接到模数转换器，用于在受控采样时将模拟信号转换为数字采样值。增益控制电路接收指示何时发生脉冲的数字值和脉冲检测器的输出。增益控制电路内的增益误差检测器确定每个检测脉冲幅度的误差量，并将该误差量滤波并通过数模转换器发送，然后通过取幂电路。指数电路的输出连接到可变增益放大器的增益控制输入。

13. 发明授权

US5917668A Synchronous read channel employing a frequency synthesizer for locking a timing recovery phase-lock loop to a reference frequency 失效
标题翻译：采用频率合成器的同步读通道，用于将定时恢复锁相环锁定到参考频率
公开(公告)号：US5917668A
公开(公告)日：1999-06-29
申请号：US822174
申请日：1997-03-21
申请人： Richard T. Behrens , Trent Dudley , Neal Glover , David R. Welland
发明人： Richard T. Behrens , Trent Dudley , Neal Glover , David R. Welland
IPC分类号： G11B5/012 , G11B5/09 , G11B20/10 , G11B20/12 , G11B20/14 , G11B20/18 , G11B27/30 , H03M13/31
CPC分类号： G11B20/10055 , G11B20/10 , G11B20/10009 , G11B20/1403 , G11B20/1426 , G11B20/18 , G11B27/3027 , G11B5/012 , G11B5/09 , H03M13/31 , G11B20/1258 , G11B2020/1476
摘要： A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. To ensure a small frequency error when timing recovery acquisition mode is entered, the timing recovery phase-lock loop (PLL) is first locked to a nominal read frequency which is the same as the write frequency. This is accomplished by multiplexing the output of the write frequency synthesizer into the timing recovery PLL in a lock-to-reference mode. Thereafter, the analog signal from the read head is multiplexed into the timing recovery PLL in order to acquire the actual frequency and phase of an acquisition preamble recorded prior to the user data.
摘要翻译：公开了一种同步读通道，其从位于磁盘介质上的磁读头读取模拟读信号，根据所需的部分响应对采样值进行滤波，从滤波后的采样值中提取定时信息，并检测估计数据序列使用离散时间序列检测器从滤波后的样本值。为了在进入定时恢复采集模式时确保小的频率误差，定时恢复锁相环（PLL）首先被锁定到与写入频率相同的标称读取频率。这是通过将写入频率合成器的输出以锁定参考模式复用到定时恢复PLL来实现的。此后，来自读取头的模拟信号被多路复用到定时恢复PLL中，以便获取在用户数据之前记录的获取前导码的实际频率和相位。

14. 发明授权

US5329554A Digital pulse detector 失效
标题翻译：数字脉冲检测器
公开(公告)号：US5329554A
公开(公告)日：1994-07-12
申请号：US879938
申请日：1992-05-08
申请人： Richard T. Behrens , Trent Dudley , Neal Glover
发明人： Richard T. Behrens , Trent Dudley , Neal Glover
IPC分类号： G11B20/10 , G11B20/14 , H03K5/1532 , H03K5/19 , H04L25/08 , H04L27/00 , H04L27/06
CPC分类号： G11B20/10037 , G11B20/10009 , G11B20/1403 , H03K5/19
摘要： Disclosed is a pulse detector that uses four samples of an analog signal to detect a pulse as soon as one sample beyond the time of the peak of the signal level at the pulse. The pulse detector can detect pulses by sampling at the center of a peak of the pulse or by sampling at either side of the peak of the pulse. The pulse detector detects pulses while tracking data, and it uses an alternate detection system for detecting pulses while acquiring timing and gain lock on a signal having a known data pattern. The detector uses either the sampled signal levels directly, or a moving average of two samples to perform the detection.
摘要翻译：公开了一种使用四个模拟信号样本的脉冲检测器，一旦超过脉冲信号电平峰值时间的一个采样就检测脉冲。脉冲检测器可以通过在脉冲峰值的中心采样或通过在脉冲峰值的任一侧进行采样来检测脉冲。脉冲检测器在跟踪数据的同时检测脉冲，并且在采集具有已知数据模式的信号的定时和增益锁定的同时使用用于检测脉冲的替代检测系统。检测器使用采样信号电平或两个采样的移动平均值进行检测。

15. 发明授权

US5359631A Timing recovery circuit for synchronous waveform sampling 失效
标题翻译：同步波形采样定时恢复电路
公开(公告)号：US5359631A
公开(公告)日：1994-10-25
申请号：US954350
申请日：1992-09-30
申请人： Richard T. Behrens , Trent Dudley , Neal Glover , David R. Welland
发明人： Richard T. Behrens , Trent Dudley , Neal Glover , David R. Welland
IPC分类号： G11B20/10 , G11B20/14 , H03D13/00 , H03L7/00 , H03L7/085 , H03L7/091 , H04L7/02 , H04L7/033 , H04L7/04 , H04L7/10 , H03D3/24
CPC分类号： G11B20/10037 , G11B20/1403 , H03D13/005 , H03L7/091 , H04L7/0334 , H04L7/04 , H04L7/046 , H04L7/10
摘要： A timing circuit having an analog to digital converter to sample an analog signal, a controlled oscillator for controlling sample times of the analog to digital converter, a circuit to detect pulses in the analog signal, a phase error circuit to subtract one of two samples from the other to create a phase error measurement and a frequency error circuit to add two samples together to create a frequency error measurement. The two samples are taken from either side of a pulse. The phase error measurement is used by the controlled oscillator to adjust the sample timing to take samples at desired locations on the pulse. The circuit also contains constant values used to compensate for the pulse being asymmetrical and to compensate for other pulses that occur close to the detected pulse. The circuit also inserts a known frequency in place of the analog signal to establish a frequency of the controlled oscillator.
摘要翻译：具有模拟数字转换器以对模拟信号进行采样的定时电路，用于控制模数转换器的采样时间的受控振荡器，用于检测模拟信号中的脉冲的电路，相位误差电路，以从另一个创建相位误差测量和频率误差电路，将两个样本相加在一起以创建频率误差测量。两个样本取自脉冲的任一侧。相位误差测量由受控振荡器用于调整采样定时以在脉冲的所需位置采样。电路还包含用于补偿不对称脉冲的常数值，并补偿靠近检测到的脉冲发生的其他脉冲。电路还插入已知频率代替模拟信号以建立受控振荡器的频率。

16. 发明授权

US5291499A Method and apparatus for reduced-complexity viterbi-type sequence detectors 失效
标题翻译：复杂度维特比型序列检测器的方法和装置
公开(公告)号：US5291499A
公开(公告)日：1994-03-01
申请号：US852015
申请日：1992-03-16
申请人： Richard T. Behrens , Kent D. Anderson , Neal Glover
发明人： Richard T. Behrens , Kent D. Anderson , Neal Glover
IPC分类号： G06F11/30 , G06F11/10 , G11B20/14 , G11B20/18 , H03H15/00 , H03H17/00 , H03H21/00 , H03M7/14 , H03M13/23 , H03M13/41 , H04B3/04 , H04L25/08 , H04L25/49 , H04L25/497 , H04L27/00 , G06F11/00
CPC分类号： G11B20/1426 , G11B20/1833 , H03M13/41 , H03M13/4107 , H04L25/4906 , H04L25/497
摘要： A Viterbi detector is modified to reduce its implementation complexity. A partial-response signal may be viewed as a sequence of expected samples generated from a finite-state-machine model. In a typical Viterbi demodulator implemented using the add, compare, select (ACS) method, each state in the expected sample sequence model is associated with a hardware module to perform the functions of adding new branch error metrics to path error metrics, comparing path error metrics, and selecting the path having the lowest path error metric. In this invention, an ACS module may have two or more sequence-model states dynamically associated with it, such that at some times one sequence-model state is associated with it and at other times another sequence-model state is associated with it. This reduces the number of ACS modules required and also reduces the size/complexity of the demodulator's path memories which must store one path for each ACS module. Groups of sequence-model states may be chosen to share an ACS module without significant loss in performance as compared to the original, unreduced Viterbi demodulator. The invention supports a wide range of sample models by making the expected sample sequence of an isolated medium transition programmable. The invention reduces the speed at which the detector circuitry must operate relative to the sample rate by allowing multiple samples to be processed simultaneously. Several reduced detectors for specific sample sequence models are presented for particular applications. The invention is applicable to other types of Viterbi detectors, such as decoders for convolutional codes.
摘要翻译：修改维特比检测器以减少其实现复杂度。部分响应信号可以被视为从有限状态机模型生成的预期样本的序列。在使用加法，比较，选择（ACS）方法实现的典型维特比解调器中，预期采样序列模型中的每个状态与硬件模块相关联，以执行向路径误差度量添加新的分支误差度量的功能，比较路径误差度量，并选择具有最低路径错误度量的路径。在本发明中，ACS模块可以具有与其动态相关联的两个或更多个序列模型状态，使得在某些时候一个序列模型状态与其相关联，并且在其他时间，另一个序列模型状态与其相关联。这减少了所需的ACS模块的数量，并且还降低了解调器的路径存储器的大小/复杂性，这些存储器必须存储每个ACS模块的一个路径。与原始的未导通的维特比解调器相比，可以选择一组序列模型状态来共享ACS模块而没有显着的性能损失。本发明通过使分离的介质跃迁的预期采样序列可编程化来支持范围广泛的样本模型。本发明通过允许同时处理多个采样来降低检测器电路相对于采样率运行的速度。针对特定应用提出了特定样品序列模型的几种降低检测器。本发明可应用于其它类型的维特比检测器，例如用于卷积码的解码器。

17. 发明授权

US5623377A Filtering a read signal to attenuate secondary pulses caused by pole tips of a thin film magnetic read head 失效
标题翻译：滤除读取信号以衰减由薄膜磁头读取头的极尖引起的次脉冲
公开(公告)号：US5623377A
公开(公告)日：1997-04-22
申请号：US222666
申请日：1994-04-04
申请人： Richard T. Behrens , Neal Glover , Trent O. Dudley , Alan J. Armstrong , Christopher P. Zook , William G. Bliss
发明人： Richard T. Behrens , Neal Glover , Trent O. Dudley , Alan J. Armstrong , Christopher P. Zook , William G. Bliss
IPC分类号： G11B5/09 , G11B20/10 , H03H17/02 , H03H17/06 , H04B3/06 , G11B5/035
CPC分类号： H03H17/06 , G11B20/10009 , G11B5/09 , H03H17/02
摘要： A filter for compensating discrete secondary pulse formations associated with a data stream of discrete main pulses produced from data read from magnetic media. The filter's impulse response comprises a center coefficient with side compensating coefficients for attenuating the secondary pulses when the input signal is convolved with the impulse response. The magnitude and delay of the compensation coefficients are programmable and are adaptively adjusted to optimize the impulse response for a given environment. In a traditional FIR embodiment, two delay lines are used to generate the two programmable delays between the center coefficient and side compensation coefficients. In the preferred embodiment, an IIR filter provides the two programmable delays using only one delay line thereby reducing the size and cost of the circuit. Also in the preferred embodiment, the data stream is interleaved into an even and odd data stream and processed in parallel by two filters in order to double the throughput. Further, the pre-cursor correcting portion of the filter can be disabled in order to avoid delaying the data stream while still canceling the post-cursor secondary pulses. The filter also comprises attenuation and adder means to match the coincident sample values in amplitude and add them to substantially eliminate the effect of the secondary pulses in the discrete data stream.
摘要翻译：用于补偿与从磁介质读取的数据产生的离散主脉冲的数据流相关联的离散次级脉冲形成的滤波器。滤波器的脉冲响应包括具有侧补偿系数的中心系数，用于当输入信号与脉冲响应卷积时衰减次级脉冲。补偿系数的幅度和延迟可编程，并进行自适应调整，以优化给定环境的脉冲响应。在传统的FIR实施例中，使用两条延迟线来产生中心系数和侧面补偿系数之间的两个可编程延迟。在优选实施例中，IIR滤波器仅使用一个延迟线提供两个可编程延迟，从而减小电路的尺寸和成本。同样在优选实施例中，数据流被交织成偶数和奇数数据流，并且由两个滤波器并行处理，以使吞吐量翻倍。此外，可以禁用滤波器的前光标校正部分，以避免在仍然取消后光标次级脉冲的同时延迟数据流。滤波器还包括衰减和加法器装置，以使幅度上重合的采样值相匹配，并将它们相加，以基本上消除离散数据流中次级脉冲的影响。

18. 发明授权

US6005731A Channel quality circuit employing a test pattern generator in a sampled amplitude read channel for calibration 失效
标题翻译：信道质量电路采用采样幅度读取通道中的测试码型发生器进行校准
公开(公告)号：US6005731A
公开(公告)日：1999-12-21
申请号：US844174
申请日：1997-04-18
申请人： William R. Foland, Jr. , Richard T. Behrens , Alan J. Armstrong , Neal Glover
发明人： William R. Foland, Jr. , Richard T. Behrens , Alan J. Armstrong , Neal Glover
IPC分类号： G11B5/09 , G11B20/10 , G11B20/18
CPC分类号： G11B20/10055 , G11B20/10009 , G11B20/10037 , G11B20/18 , G11B20/1816 , G11B20/182 , G11B5/09
摘要： A channel quality circuit, incorporated within a sampled amplitude read channel utilized in a magnetic storage system, for processing and accumulating performance data from the individual read channel components, wherein the performance data is used to calibrate the read channel to operate in a particular environment, to estimate the bit error rate of the storage system, and to detect defects in the magnetic medium. The channel quality circuit generates a test pattern of digital data which is written to the storage system. Then, as the test pattern is read from the storage system, the channel quality circuit accumulates performance data from the read channel components. The test pattern is used to generate expected samples and expected sample errors relative to the samples read by the read channel. Gating logic is programmed to accumulate only the particular performance data of interest. The channel quality circuit computes auto and cross-correlations, squared errors, and threshold comparisons. A defect detection filter detects particular defects in the media. In order to predict the bit error rate of the storage system, the channel quality circuit accumulates noise auto-correlation data, confidence metrics from a sequence detector, and cross-correlation of expected sample errors with actual sample errors.
摘要翻译：一种信道质量电路，其被并入在磁存储系统中使用的采样幅度读取信道中，用于处理和累积来自各个读取信道分量的性能数据，其中，所述性能数据用于校准所述读取信道以在特定环境中操作，估计存储系统的误码率，并检测磁介质中的缺陷。信道质量电路产生写入存储系统的数字数据的测试模式。然后，当从存储系统读取测试图案时，信道质量电路从读取的信道分量累积性能数据。测试模式用于产生相对于读通道读取的样本的预期样本和预期样本误差。门控逻辑被编程为仅累积感兴趣的特定性能数据。信道质量电路计算自动和互相关，平方误差和阈值比较。缺陷检测滤波器检测介质中的特定缺陷。为了预测存储系统的误码率，信道质量电路将噪声自相关数据，序列检测器的置信度量度以及预期样本误差与实际样本误差的互相关累积。

19. 发明授权

US5761212A Channel quality 失效
标题翻译：渠道质量
公开(公告)号：US5761212A
公开(公告)日：1998-06-02
申请号：US545965
申请日：1995-10-20
申请人： William R. Foland, Jr. , Richard T. Behrens , Alan J. Armstrong , Neal Glover
发明人： William R. Foland, Jr. , Richard T. Behrens , Alan J. Armstrong , Neal Glover
IPC分类号： G11B5/09 , G11B20/10 , G11B20/18 , G11C29/00
CPC分类号： G11B20/10055 , G11B20/10009 , G11B20/10037 , G11B20/18 , G11B20/1816 , G11B20/182 , G11B5/09
摘要： A measurement circuit is provided to obtain data for monitoring the quality of performance from a digital read channel. Elements of the digital read channel including a sequence detector are incorporated into an integrated circuit together with the measurement circuit. The measurement circuit relates digitized samples of readback data from a magnetic storage device to surrounding samples so that particular samples can be collected in accordance with their surroundings. The circuit includes a programmable time window which can be repeatedly opened for data collection. The circuit is designed to collect various types of data including the bit error rate, sample value, squared sample error, squared gain error, squared timing error, and the occurrences of sample error when it is outside an acceptable programmable threshold. The measurement circuit includes a signal generator for producing a test pattern that is first stored and then read to produce the digitized readback sample values. The measurement circuit also includes a conversion circuit for converting the test pattern to a sequence of expected sample values in accordance with a state machine model of the sequence detector. The sample value error results from a comparison of the readback sample value to the expected sample value.
摘要翻译：提供测量电路以获得用于从数字读取通道监视性能的数据。包括序列检测器的数字读通道的元件与测量电路一起并入集成电路中。测量电路将来自磁存储装置的回读数据的数字化样本与周围样品相关联，使得可以根据其周围环境收集特定样品。该电路包括可重复打开以供数据采集的可编程时间窗口。电路设计用于收集各种类型的数据，包括误码率，采样值，平方采样误差，平方增益误差，平方定时误差，以及采样误差超出可接受的可编程阈值时的出现。测量电路包括用于产生测试图案的信号发生器，其首先被存储然后被读取以产生数字化的回读采样值。测量电路还包括根据序列检测器的状态机模型将测试图案转换成预期样本值序列的转换电路。样本值误差来自于回读样本值与预期样本值的比较。

20. 发明授权

US5909331A Synchronous read channel sintegrated circuit employing a fault tolerant sync mark detector and method for recovering an undetectable sync mark 失效
标题翻译：采用容错同步标记检测器的同步读通道整合电路和用于恢复不可检测的同步标记的方法
公开(公告)号：US5909331A
公开(公告)日：1999-06-01
申请号：US823393
申请日：1997-03-19
申请人： Richard T. Behrens , Trent O. Dudley , Neal Glover
发明人： Richard T. Behrens , Trent O. Dudley , Neal Glover
IPC分类号： G11B5/012 , G11B5/09 , G11B20/10 , G11B20/12 , G11B20/14 , G11B20/18 , G11B27/30 , H03M13/31
CPC分类号： G11B20/10055 , G11B20/10 , G11B20/10009 , G11B20/1403 , G11B20/1426 , G11B20/18 , G11B27/3027 , G11B5/012 , G11B5/09 , H03M13/31 , G11B20/1258 , G11B2020/1476
摘要： A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. The read channel further employs an error tolerant sync mark detector, as well as a sync mark recovery procedure for synchronizing to the data when the sync mark is destroyed by a defect.
摘要翻译：公开了一种同步读通道，其从位于磁盘介质上的磁读头读取模拟读信号，根据所需的部分响应对采样值进行滤波，从滤波后的采样值中提取定时信息，并检测估计数据序列使用离散时间序列检测器从滤波后的样本值。读通道还采用容错同步标记检测器，以及当同步标记被缺陷破坏时同步到数据的同步标记恢复过程。

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