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21. 发明授权

US07538598B1 Circuit and method for supplying programming potential at voltages larger than BVDss of programming transistors 有权
标题翻译：用于在大于编程晶体管的BVDss的电压下提供编程电位的电路和方法
公开(公告)号：US07538598B1
公开(公告)日：2009-05-26
申请号：US12172675
申请日：2008-07-14
申请人： John McCollum
发明人： John McCollum
IPC分类号： H01H37/76
CPC分类号： G11C17/18
摘要： A circuit for programming an antifuse coupled between a first node and a second node includes at least one transistor for supplying a programming potential VPP to the first node. A first transistor has a source coupled to a third node switchably coupleable between a potential of VPP/2 and ground potential, a drain, and a gate. A second transistor has a source coupled to the drain of the first transistor, a drain coupled to the second node, and a gate. Programming circuitry is coupled to the gate of the first transistor and the gate of the second transistor and configured to in a programming mode apply a potential of either zero volts or VPP/2 to the gate of the first transistor and to apply a potential of VPP/2 to the gate of the second transistor. The first and second transistors have a BVDss rating of not more than about VPP/2.
摘要翻译：用于编程耦合在第一节点和第二节点之间的反熔丝的电路包括用于向第一节点提供编程电位VPP的至少一个晶体管。第一晶体管具有耦合到可在VPP / 2的电位和地电位之间切换耦合的第三节点的源极，漏极和栅极。第二晶体管具有耦合到第一晶体管的漏极的源极，耦合到第二节点的漏极和栅极。编程电路耦合到第一晶体管的栅极和第二晶体管的栅极，并被配置为在编程模式中将零电压或VPP / 2的电位施加到第一晶体管的栅极并施加VPP的电位 / 2连接到第二晶体管的栅极。第一和第二晶体管具有不大于约VPP / 2的BVDss等级。

22. 发明授权

US07532035B2 Address transition detector for fast flash memory device 有权
标题翻译：用于快速闪存器件的地址转换检测器
公开(公告)号：US07532035B2
公开(公告)日：2009-05-12
申请号：US11833833
申请日：2007-08-03
申请人： Poongyeub Lee , Ming-Chi Liu
发明人： Poongyeub Lee , Ming-Chi Liu
IPC分类号： H03K19/094 , H03K19/0175
CPC分类号： G11C7/22 , G11C7/04 , G11C7/08 , G11C7/12 , G11C8/18 , G11C2207/061 , G11C2207/2281 , H03K2005/00039
摘要： An address transition detector circuit includes an input node, an output node, a bandgap reference node, and Pbias and Nbias nodes having voltages derived from the bandgap reference node. First through fifth cascaded inverters are each powered by a p-channel and n-channel MOS bias transistors having their gates coupled respectively to the Pbias node and the Nbias node. The input of the first inverter is coupled to the input node. First and second capacitors are coupled respectively to ground from the outputs of the first and fourth cascaded inverters. A NAND gate has a first input coupled to the input node, a second input coupled the output of the fifth cascaded inverter, and an output coupled to the output node.
摘要翻译：地址转换检测器电路包括具有从带隙参考节点导出的电压的输入节点，输出节点，带隙参考节点以及Pbias和Nbias节点。第一到第五级联逆变器分别由其通道分别耦合到Pbias节点和Nbias节点的p沟道和n沟道MOS偏置晶体管供电。第一反相器的输入耦合到输入节点。第一和第二电容器从第一和第四级联逆变器的输出分别耦合到地。 NAND门具有耦合到输入节点的第一输入，耦合第五级联反相器的输出的第二输入和耦合到输出节点的输出。

23. 发明申请

US20090106531A1 FIELD PROGRAMMABLE GATE ARRAY AND MICROCONTROLLER SYSTEM-ON-A-CHIP 有权
标题翻译：现场可编程阵列阵列和微控制器系统
公开(公告)号：US20090106531A1
公开(公告)日：2009-04-23
申请号：US12345409
申请日：2008-12-29
申请人： Arunangshu Kundu , Arnold Goldfein , William C. Plants , David Hightower
发明人： Arunangshu Kundu , Arnold Goldfein , William C. Plants , David Hightower
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F15/7842 , G06F15/7867
摘要： A system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherein the inputs are connected to the field programmable gate array core, a microcontroller, a microcontroller virtual component interface translator having input and outputs, wherein the inputs are connected to the microcontroller, a system bus connected to the outputs of the field programmable gate array virtual component interface translator and also to the outputs of said microcontroller virtual component interface translator, and direct connections between the microcontroller and the routing resources of the field programmable gate array core.
摘要翻译：片上系统集成电路具有具有逻辑集群，静态随机存取存储器模块和路由资源的现场可编程门阵列核心，具有输入和输出的现场可编程门阵列虚拟组件接口转换器，其中输入被连接到现场可编程门阵列核心，微控制器，具有输入和输出的微控制器虚拟组件接口转换器，其中输入连接到微控制器，连接到现场可编程门阵列虚拟组件接口转换器的输出的系统总线，以及到所述微控制器虚拟组件接口转换器的输出，以及微控制器与现场可编程门阵列核心的路由资源之间的直接连接。

24. 发明授权

US07493506B2 Programmable system on a chip for power-supply voltage and current monitoring and control 有权
标题翻译：芯片上的可编程系统，用于电源电压和电流监控
公开(公告)号：US07493506B2
公开(公告)日：2009-02-17
申请号：US11932778
申请日：2007-10-31
申请人： Rabindranth Balasubramanian , Gregory Bakker
发明人： Rabindranth Balasubramanian , Gregory Bakker
IPC分类号： G06F1/26
CPC分类号： H03K19/1776 , G01K7/015 , G06F1/08 , G06F1/28 , G06F1/30 , G06F15/7842 , G06F15/7867 , H03F3/45475 , H03F2203/45136 , H03F2203/45166 , H03K17/223 , H03K19/177 , H03K19/17732
摘要： A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and voltage-measuring and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, or other multiple die configuration. The programmable system-on-a-chip integrated circuit with voltage-measuring, current-measuring and control circuitry performs voltage measurement and control functions and can be used to control and monitor external power supplies connected to external loads.
摘要翻译：可编程片上系统芯片集成电路器件包括可编程逻辑块，至少一个用户非易失性存储器块，以及在单个半导体集成电路芯片或倒装芯片上的电压测量和控制模拟和数字电路，面对面或其他多芯片配置。具有电压测量，电流测量和控制电路的可编程片上系统芯片集成电路执行电压测量和控制功能，可用于控制和监视连接到外部负载的外部电源。

25. 发明授权

US07463061B1 Apparatus and method for reducing leakage of unused buffers in an integrated circuit 有权
标题翻译：用于减少集成电路中未使用的缓冲器泄漏的装置和方法
公开(公告)号：US07463061B1
公开(公告)日：2008-12-09
申请号：US11185426
申请日：2005-07-19
申请人： Jonathan W. Greene , Vidya Bellippady
发明人： Jonathan W. Greene , Vidya Bellippady
IPC分类号： H03K19/20
CPC分类号： H03K19/0008
摘要： A reduced-leakage interconnect circuit includes a buffer having an input and an output, at least one multiplexer transistor coupled between a multiplexer input node and the input of the buffer, and a fixed-state multiplexer transistor coupled between a fixed-state multiplexer input node and the input of the buffer, the fixed-state multiplexer input node having a potential of either less than zero volts or more than VCC present on it.
摘要翻译：减少泄漏的互连电路包括具有输入和输出的缓冲器，耦合在多路复用器输入节点和缓冲器的输入之间的至少一个多路复用器晶体管，以及耦合在固定状态多路复用器输入节点以及缓冲器的输入，固定状态多路复用器输入节点具有小于零伏特或高于其上存在的VCC的电位。

26. 发明授权

US07459763B1 Reprogrammable metal-to-metal antifuse employing carbon-containing antifuse material 有权
公开(公告)号：US07459763B1
公开(公告)日：2008-12-02
申请号：US10784903
申请日：2004-02-20
申请人： A. Farid Issaq , Frank Hawley , John McCollum
发明人： A. Farid Issaq , Frank Hawley , John McCollum
IPC分类号： H01L29/00 , H01L31/0312
CPC分类号： H01L23/5252 , G11C17/16 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A reprogrammable metal-to-metal antifuse is disposed between two metal interconnect layers in an integrated circuit. A lower barrier layer is formed from Ti. A lower adhesion-promoting layer is disposed over the lower Ti barrier layer. An antifuse material layer selected from a group comprising at least one of amorphous carbon and amorphous carbon doped with at least one of hydrogen and fluorine is disposed over the lower adhesion-promoting layer. An upper adhesion-promoting layer is disposed over the antifuse material layer. An upper Ti barrier layer is disposed over the upper adhesion-promoting layer.

27. 发明申请

US20080284532A1 VOLTAGE- AND TEMPERATURE-COMPENSATED RC OSCILLATOR CIRCUIT 审中-公开
标题翻译：电压和温度补偿RC振荡器电路
公开(公告)号：US20080284532A1
公开(公告)日：2008-11-20
申请号：US12182329
申请日：2008-07-30
申请人： Gregory Bakker
发明人： Gregory Bakker
IPC分类号： H03K3/26 , H03K3/02 , H03K3/42 , H03L1/00
CPC分类号： H03K3/0231 , H03K3/011 , H03L1/022
摘要： An integrated temperature-compensated RC oscillator circuit includes an inverter having an input and an output. An RC network is coupled between the inverter and a pair of comparators. A first comparator has an inverting input coupled to a first reference voltage, a non-inverting input coupled to the RC network, and an output. A second comparator has an inverting input coupled to the RC network, a non-inverting input coupled to a second reference voltage, and an output. A set-reset flip-flop has a set input coupled to the output of the first comparator, a reset input coupled to the output of the second comparator, and an output coupled to the input of the inverter. Differential amplifiers in the comparators each have a diode-connected p-channel MOS transistor controlling a mirrored p-channel MOS transistor whose channel width is less than that of the diode-connected p-channel current mirror transistor.
摘要翻译：集成温度补偿RC振荡器电路包括具有输入和输出的反相器。 RC网络耦合在逆变器和一对比较器之间。第一比较器具有耦合到第一参考电压的反相输入，耦合到RC网络的非反相输入和输出。第二比较器具有耦合到RC网络的反相输入，耦合到第二参考电压的非反相输入和输出。设置复位触发器具有耦合到第一比较器的输出的设置输入，耦合到第二比较器的输出的复位输入和耦合到反相器的输入的输出。比较器中的差分放大器各自具有二极管连接的p沟道MOS晶体管，其控制沟道宽度小于二极管连接的p沟道电流镜晶体管的p沟道MOS晶体管。

28. 发明申请

US20080276030A1 SRAM BUS ARCHITECTURE AND INTERCONNECT TO AN FPGA 审中-公开
标题翻译： SRAM总线架构和与FPGA的连接
公开(公告)号：US20080276030A1
公开(公告)日：2008-11-06
申请号：US12178288
申请日：2008-07-23
申请人： William C. Plants
发明人： William C. Plants
IPC分类号： G06F13/40
CPC分类号： G11C7/10 , G11C7/18 , G11C8/10 , H03K19/17736 , H03K19/1776
摘要： An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connected in parallel with a tri-state buffer. The pass transistors and tri-state buffers are controlled by configuration SRAM bits. Some of the pass-through interconnect conductors are connected by programmable elements to the address, data and control signal lines of the SRAM blocks, while other pass through the SRAM blocks without being further connected to the SRAM bussing architecture.
摘要翻译： SRAM总线架构包括直通互连导体。每个直通互连导体通过包括与三态缓冲器并联连接的传输晶体管的元件连接到FPGA的通用互连架构的路由通道。传输晶体管和三态缓冲器由配置SRAM位控制。一些直通互连导体通过可编程元件连接到SRAM块的地址，数据和控制信号线，而其他通过SRAM块而不进一步连接到SRAM总线架构。

29. 发明授权

US07443191B2 Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array 有权
标题翻译：辐射硬化静态随机存取存储器现场可编程门阵列中误差检测和校正的装置和方法
公开(公告)号：US07443191B2
公开(公告)日：2008-10-28
申请号：US11859497
申请日：2007-09-21
申请人： William C. Plants
发明人： William C. Plants
IPC分类号： H03K19/003
CPC分类号： G06F11/1008 , G11C5/005 , G11C11/4125 , H01L27/118 , H03K19/00338 , H03K19/1776 , H03K19/17764 , H03K19/1778
摘要： The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the routing resources. Error correction circuitry coupled to the configuration data lines analyzes and corrects any errors in the configuration data that may occur due to a single event upset (SEU).
摘要翻译：本系统包括具有将逻辑模块耦合在一起的逻辑模块和路由资源的辐射容忍可编程逻辑器件。提供配置数据的配置数据线控制逻辑模块和路由资源的编程。耦合到配置数据线的错误校正电路分析和校正由于单个事件不正常（SEU）而可能发生的配置数据中的任何错误。

30. 发明授权

US07430137B2 Non-volatile memory cells in a field programmable gate array 失效
标题翻译：现场可编程门阵列中的非易失性存储单元
公开(公告)号：US07430137B2
公开(公告)日：2008-09-30
申请号：US11868694
申请日：2007-10-08
申请人： Jonathan W. Greene , Fethi Dhaoui , Robert M. Salter, III , John McCollum
发明人： Jonathan W. Greene , Fethi Dhaoui , Robert M. Salter, III , John McCollum
IPC分类号： G11C16/02 , G11C5/02 , G11C5/06 , G06F7/38 , H03K19/173 , H03K19/177 , H03K19/94
CPC分类号： H03K19/1776 , G11C16/0441 , H03K19/17736 , H03K19/1778
摘要： A non-volatile memory cell comprises a first floating gate transistor having a source, a drain, and a gate electrically coupled to a row line. A second floating gate transistor has a source, a drain, and a gate electrically coupled to the row line. A first p-channel MOS transistor has a source, a drain, and a gate, the drain of the first p-channel MOS transistor electrically coupled to the drain of the first floating gate transistor forming a first common node. A second p-channel MOS transistor has a source, a drain, and a gate, the first drain of the second p-channel MOS transistor electrically coupled to the drain of the second floating gate transistor forming a second common node, the gate of the second p-channel MOS transistor electrically coupled to the first common node, and the second common node electrically coupled to the gate of the first p-channel MOS transistor.
摘要翻译：非易失性存储单元包括具有电耦合到行线的源极，漏极和栅极的第一浮栅晶体管。第二浮栅晶体管具有电耦合到行线的源极，漏极和栅极。第一p沟道MOS晶体管具有源极，漏极和栅极，第一p沟道MOS晶体管的漏极电耦合到第一浮动栅极晶体管的漏极，形成第一公共节点。第二p沟道MOS晶体管具有源极，漏极和栅极，第二p沟道MOS晶体管的第一漏极电耦合到形成第二公共节点的第二浮栅晶体管的漏极，栅极电耦合到第一公共节点的第二P沟道MOS晶体管，以及电耦合到第一p沟道MOS晶体管的栅极的第二公共节点。

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