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21. 发明授权

US07317721B1 Systems and methods for memory utilization during packet forwarding 有权
标题翻译：数据包转发期间内存利用的系统和方法
公开(公告)号：US07317721B1
公开(公告)日：2008-01-08
申请号：US10120380
申请日：2002-04-12
申请人： Pradeep Sindhu , Raymond M. Lim , Dennis C. Ferguson
发明人： Pradeep Sindhu , Raymond M. Lim , Dennis C. Ferguson
IPC分类号： H04L12/56
CPC分类号： H04L45/16 , H04L45/02 , H04L49/201
摘要： A network device includes a memory and a packet forwarding engine. The memory stores a multicast list table, tag descriptor data and layer 2 (L2) encapsulation data. The packet forwarding engine receives a first pointer to an entry in the multicast list table, the entry including a second pointer to the tag descriptor data. The packet forwarding engine utilizes the second pointer to retrieve the tag descriptor data, the tag descriptor data including a third pointer to the encapsulation data. The packet forwarding engine constructs a packet header utilizing the retrieved encapsulation data and appends the packet header to a packet payload for forwarding out of the packet forwarding engine.
摘要翻译：网络设备包括存储器和分组转发引擎。存储器存储多播列表表，标签描述符数据和层2（L2）封装数据。分组转发引擎接收到多播列表表中的条目的第一指针，该条目包括指向标签描述符数据的第二指针。分组转发引擎利用第二指针来检索标签描述符数据，标签描述符数据包括指向封装数据的第三指针。分组转发引擎使用所检索的封装数据构建分组报头，并将分组报头附加到分组有效载荷，以转发出分组转发引擎。

22. 发明申请

US20070147257A1 IN-LINE PACKET PROCESSING 有权
标题翻译：在线分组处理
公开(公告)号：US20070147257A1
公开(公告)日：2007-06-28
申请号：US11682111
申请日：2007-03-05
申请人： Rasoul Oskouy , Dennis Ferguson , Hann-Hwan Ju , Raymond Lim , Pradeep Sindhu , Sreeram Veeragandham , Jeff Zimmer , Michael Hui
发明人： Rasoul Oskouy , Dennis Ferguson , Hann-Hwan Ju , Raymond Lim , Pradeep Sindhu , Sreeram Veeragandham , Jeff Zimmer , Michael Hui
IPC分类号： H04J3/14 , H04J3/24
CPC分类号： H04L45/74 , G06F11/08 , H04L1/0041 , H04L12/56 , H04L12/5601 , H04L29/06 , H04L45/00 , H04L45/20 , H04L45/60 , H04L47/6225 , H04L49/103 , H04L49/108 , H04L49/203 , H04L49/25 , H04L49/254 , H04L49/30 , H04L49/3009 , H04L49/3063 , H04L49/3081 , H04L49/555 , H04L49/602 , H04L49/608 , H04L49/90 , H04L49/901 , H04L49/9047 , H04L69/16 , H04L69/161 , H04L69/22 , H04L69/324 , H04L2012/5652 , H04L2012/5679 , H04Q11/0478
摘要： A method and apparatus for in-line processing a data packet while routing the packet through a router in a system transmitting data packets between a source and a destination over a network including the router. The method includes receiving the data packet and pre-processing layer header data for the data packet as the data packet is received and prior to transferring any portion of the data packet to packet memory. The data packet is thereafter stored in the packet memory. A routing through the router is determined including a next hop index describing the next connection in the network. The data packet is retrieved from the packet memory and a new layer header for the data packet is constructed from the next hop index while the data packet is being retrieved from memory. The new layer header is coupled to the data packet prior to transfer from the router.
摘要翻译：一种用于在通过包括路由器的网络在源和目的地之间传输数据分组的系统中的路由器路由数据包的同时处理数据分组的方法和装置。该方法包括在接收到数据分组并且将数据分组的任何部分传送到分组存储器之前接收数据分组和数据分组的预处理层报头数据。数据分组此后被存储在分组存储器中。确定通过路由器的路由，其包括描述网络中的下一个连接的下一跳索引。从分组存储器检索数据分组，并且在从存储器检索数据分组的同时，从下一跳索引构建数据分组的新层头。在从路由器传送之前，将新层标头耦合到数据包。

23. 发明授权

US07180893B1 Parallel layer 2 and layer 3 processing components in a network router 有权
标题翻译：并行层2和层3处理网络路由器中的组件
公开(公告)号：US07180893B1
公开(公告)日：2007-02-20
申请号：US10102960
申请日：2002-03-22
申请人： Pradeep Sindhu , Raymond M. Lim , Jeffrey G. Libby
发明人： Pradeep Sindhu , Raymond M. Lim , Jeffrey G. Libby
IPC分类号： H04L12/56 , H04J3/22 , G06F9/30
CPC分类号： H04L45/60 , H04L45/50 , H04L49/3009 , H04L49/602
摘要： A packet header processing engine includes a level 2 (L2) header generation unit and a level 3 (L3) header generation unit. The L2 and L3 header generation units are implemented in parallel with one another. The L2 generation unit writes L2 header information to a first buffer and the L3 generation unit writes L3 header information to a second buffer. When both the L2 and L3 generation units complete their operations for a particular packet, a build component combines the generated L2 and L3 header information from the buffers to form a complete packet header.
摘要翻译：分组报头处理引擎包括级别2（L2）报头生成单元和级别3（L3）报头生成单元。 L2和L3报头生成单元彼此并行实现。 L2生成单元将L2头信息写入第一缓冲器，L3生成单元将L3头信息写入第二缓冲器。当L2和L3生成单元完成其针对特定分组的操作时，构建部件组合来自缓冲器的生成的L2和L3报头信息以形成完整的分组报头。

24. 发明申请

US20050201396A1 Separation of data and control in a switching device 有权
标题翻译：切换设备中数据和控制的分离
公开(公告)号：US20050201396A1
公开(公告)日：2005-09-15
申请号：US11123112
申请日：2005-05-06
申请人： Pradeep Sindhu , Kireeti Kompella , Dennis Ferguson , Bjorn Liencres , Nalini Agarwal , Hann-Hwan Ju , Raymond Lim , Rasoul Oskouy , Sreeram Veeragandham
发明人： Pradeep Sindhu , Kireeti Kompella , Dennis Ferguson , Bjorn Liencres , Nalini Agarwal , Hann-Hwan Ju , Raymond Lim , Rasoul Oskouy , Sreeram Veeragandham
IPC分类号： H04L12/46 , H04L12/56 , H04L29/06 , H04Q11/04
CPC分类号： G06F15/167 , H04L12/5601 , H04L29/06 , H04L45/00 , H04L45/72 , H04L45/7457 , H04L47/6225 , H04L49/103 , H04L49/108 , H04L49/1538 , H04L49/203 , H04L49/25 , H04L49/252 , H04L49/3072 , H04L49/3081 , H04L49/608 , H04L49/90 , H04L49/901 , H04L49/9042 , H04L49/9047 , H04L49/9057 , H04L69/22 , H04L2012/5652 , H04L2012/5679 , H04L2012/5681 , H04Q11/0478
摘要： A method and apparatus for switching a data packet between a source and destination in a network. The data packet includes a header portion and a data portion. The header portion includes routing information for the data packet. The method includes defining a data path in the router comprising a path through the router along which the data portion of the data packet travels and defining a control path comprising a path through the router along which routing information from the header portion travels. The method includes separating the data path and control path in the router such that the routing information can be separated from the data portion allowing for the separate processing of each in the router. The data portion can be stored in a global memory while routing decisions are made on the routing information in the control path.
摘要翻译：一种用于在网络中的源和目的地之间切换数据分组的方法和装置。数据分组包括报头部分和数据部分。报头部分包括用于数据分组的路由信息。该方法包括在路由器中定义数据路径，其包括通过路由器的路径，数据分组的数据部分沿着路径行进，并且定义包括通过路由器的路径的控制路径，路由器沿着路径信息从该路径行进。该方法包括分离路由器中的数据路径和控制路径，使得路由信息可以与数据部分分离，允许路由器中的每一个的单独处理。数据部分可以存储在全局存储器中，同时对控制路径中的路由信息作出路由决定。

25. 发明授权

US08730954B2 Methods and apparatus related to any-to-any connectivity within a data center 有权
标题翻译：与数据中心内的任何连接相关的方法和设备
公开(公告)号：US08730954B2
公开(公告)日：2014-05-20
申请号：US12495337
申请日：2009-06-30
申请人： Pradeep Sindhu , Gunes Aybay , Jean-Marc Frailong , Anjan Venkatramani , Quaizar Vohra
发明人： Pradeep Sindhu , Gunes Aybay , Jean-Marc Frailong , Anjan Venkatramani , Quaizar Vohra
IPC分类号： H04Q11/00 , H04Q3/68 , H04L12/56
CPC分类号： H04Q3/68 , H04L49/1515 , H04L49/1523 , H04L49/153 , H04L49/254 , H04L49/351 , H04L49/40 , H04L49/70
摘要： In one embodiment, an apparatus includes a switch core that defines a single logical entity and has a multi-stage switch fabric physically distributed across a plurality of chassis. The multi-stage switch fabric has a plurality of ingress ports and a plurality of egress ports. The switch core is configured to be coupled to a plurality of peripheral processing devices via the plurality of ingress ports and the plurality of egress ports. The switch core is also configured to provide non-blocking connectivity at line rate between a first peripheral processing device disposed with a first chassis and a second peripheral processing device disposed within a second chassis.
摘要翻译：在一个实施例中，设备包括交换机核心，其定义单个逻辑实体并且具有物理上分布在多个机箱上的多级交换机结构。多级交换结构具有多个入口和多个出口。交换机核心被配置为经由多个入口端口和多个出口端口耦合到多个外围处理设备。交换机核心还被配置为在布置在第一机架的第一外围处理设备与设置在第二机架内的第二外围处理设备之间的线路速率下提供非阻塞连接。

26. 发明授权

US08503304B2 Filtering and route lookup in a switching device 有权
标题翻译：在交换设备中过滤和路由查找
公开(公告)号：US08503304B2
公开(公告)日：2013-08-06
申请号：US13539164
申请日：2012-06-29
申请人： Dennis C. Ferguson , Rajiv Patel , Gerald Cheung , Pradeep Sindhu
发明人： Dennis C. Ferguson , Rajiv Patel , Gerald Cheung , Pradeep Sindhu
IPC分类号： H04L12/26
CPC分类号： H04L45/745 , H04L45/00 , H04L45/60 , H04L45/7457 , H04L47/10 , H04L47/11 , H04L47/125 , H04L47/20 , H04L49/205 , H04L49/3009 , H04L49/3036 , H04L49/3072 , H04L63/0227 , H04L63/1458 , H04L69/22
摘要： Methods and devices for processing packets are provided. The processing device may Include an input interface for receiving data units containing header information of respective packets; a first module configurable to perform packet filtering based on the received data units; a second module configurable to perform traffic analysis based on the received data units; a third module configurable to perform load balancing based on the received data units; and a fourth module configurable to perform route lookups based on the received data units.
摘要翻译：提供了处理数据包的方法和设备。处理装置可以包括用于接收包含各个分组的报头信息的数据单元的输入接口; 第一模块，可配置为基于所接收的数据单元执行分组过滤; 第二模块，可配置为基于所接收的数据单元执行流量分析; 第三模块，可配置为基于所接收的数据单元执行负载平衡; 以及第四模块，其可配置为基于所接收的数据单元执行路线查找。

27. 发明授权

US08335213B2 Methods and apparatus related to low latency within a data center 有权
标题翻译：与数据中心内的低延迟相关的方法和设备
公开(公告)号：US08335213B2
公开(公告)日：2012-12-18
申请号：US12495358
申请日：2009-06-30
申请人： Pradeep Sindhu , Gunes Aybay , Jean-Marc Frailong , Anjan Venkatramani , Quaizar Vohra
发明人： Pradeep Sindhu , Gunes Aybay , Jean-Marc Frailong , Anjan Venkatramani , Quaizar Vohra
IPC分类号： H04Q11/00
CPC分类号： H04L49/602 , H04L49/1515 , H04L49/351 , H04L49/357
摘要： In one embodiment, an apparatus includes a switch core that has a multi-stage switch fabric. The multi-stage switch fabric has a set of ingress ports and a set of egress ports. The switch core can be configured to be coupled to a set of edge devices via the set of ingress ports and the set of egress ports. The switch core can be configured to receive a packet from an ingress port from the set of ingress ports. The switch core can be configured to send a set of cells associated with the packet from the ingress port to an egress port from the set of egress ports without a store-and-forward delay associated with a zero-load latency for the switch core.
摘要翻译：在一个实施例中，一种装置包括具有多级交换结构的交换机核心。多级交换结构具有一组入口端口和一组出口端口。交换机核心可以被配置为经由一组入口端口和出口端口组来耦合到一组边缘设备。交换机核心可以配置为从入口端口的一组入口端口接收数据包。交换机核心可以被配置为将来自入口端口的与分组相关联的一组小区从出口端口发送到出口端口，而没有与交换机核心的零负载延迟相关联的存储转发延迟。

28. 发明授权

US08321753B2 Optimization of packet buffer memory utilization 有权
标题翻译：分组缓冲存储器利用率的优化
公开(公告)号：US08321753B2
公开(公告)日：2012-11-27
申请号：US12759313
申请日：2010-04-13
申请人： Pradeep Sindhu , Srihari Vegesna
发明人： Pradeep Sindhu , Srihari Vegesna
IPC分类号： H03M13/00
CPC分类号： G06F11/006 , G06F11/1008 , H03M13/09 , H03M13/096 , H03M13/1515 , H03M13/19 , H04L1/0052
摘要： A method performed by an I/O unit connected to another I/O unit in a network device. The method includes receiving a packet; segmenting the packet into a group of data blocks; storing the group of data blocks in a data memory; generating data protection information for a data block of the group of data blocks; creating a control block for the data block; storing, in a control memory, a group of data items for the control block, the group of data items including information associated with a location, of the data block, within the data memory and the data protection information for the data block; performing a data integrity check on the data block, using the data protection information, to determine whether the data block contains a data error; and outputting the data block when the data integrity check indicates that the data block does not contain a data error.
摘要翻译：由与网络设备中的另一I / O单元连接的I / O单元执行的方法。该方法包括接收分组; 将分组分割成一组数据块; 将数据块组存储在数据存储器中; 生成数据块组的数据块的数据保护信息; 创建数据块的控制块; 在控制存储器中存储用于控制块的一组数据项，数据组的数据项组，包括与数据块的位置相关联的信息，数据存储器内的数据块和数据块的数据保护信息; 使用数据保护信息对数据块执行数据完整性检查，以确定数据块是否包含数据错误; 并且当数据完整性检查指示数据块不包含数据错误时，输出数据块。

29. 发明申请

US20120275307A1 METHODS AND APPARATUS FOR FLOW-CONTROLLABLE MULTI-STAGED QUEUES 有权
标题翻译：流量可控多阶段队列的方法和装置
公开(公告)号：US20120275307A1
公开(公告)日：2012-11-01
申请号：US13544604
申请日：2012-07-09
申请人： Avanindra Godbole , Pradeep Sindhu , Jean-Marc Frailong
发明人： Avanindra Godbole , Pradeep Sindhu , Jean-Marc Frailong
IPC分类号： H04L12/24
CPC分类号： H04L47/30 , H04L47/10 , H04L47/11 , H04L47/26 , H04L47/263 , H04L47/266 , H04L47/50 , H04L47/60 , H04L49/505 , H04L49/90
摘要： In one embodiment, a method includes sending a first flow control signal to a first stage of transmit queues when a receive queue is in a congestion state. The method also includes sending a second flow control signal to a second stage of transmit queues different from the first stage of transmit queues when the receive queue is in the congestion state.
摘要翻译：在一个实施例中，一种方法包括当接收队列处于拥塞状态时，向发射队列的第一级发送第一流控制信号。该方法还包括当接收队列处于拥塞状态时，将第二流控制信号发送到与发送队列的第一级不同的发送队列的第二级。

30. 发明授权

US08238246B2 Filtering and route lookup in a switching device 有权
标题翻译：在交换设备中过滤和路由查找
公开(公告)号：US08238246B2
公开(公告)日：2012-08-07
申请号：US13163477
申请日：2011-06-17
申请人： Dennis C. Ferguson , Rajiv Patel , Gerald Cheung , Pradeep Sindhu
发明人： Dennis C. Ferguson , Rajiv Patel , Gerald Cheung , Pradeep Sindhu
IPC分类号： H04L12/26
CPC分类号： H04L45/745 , H04L45/00 , H04L45/60 , H04L45/7457 , H04L47/10 , H04L47/11 , H04L47/125 , H04L47/20 , H04L49/205 , H04L49/3009 , H04L49/3036 , H04L49/3072 , H04L63/0227 , H04L63/1458 , H04L69/22
摘要： Methods and devices for processing packets are provided. The processing device may Include an input interface for receiving data units containing header information of respective packets; a first module configurable to perform packet filtering based on the received data units; a second module configurable to perform traffic analysis based on the received data units; a third module configurable to perform load balancing based on the received data units; and a fourth module configurable to perform route lookups based on the received data units.
摘要翻译：提供了处理数据包的方法和设备。处理装置可以包括用于接收包含相应分组的报头信息的数据单元的输入接口; 第一模块，可配置为基于所接收的数据单元执行分组过滤; 第二模块，可配置为基于所接收的数据单元执行流量分析; 第三模块，可配置为基于所接收的数据单元执行负载平衡; 以及第四模块，其可配置为基于所接收的数据单元执行路线查找。

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