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41. 发明授权

US07321237B2 Non-volatile look-up table for an FPGA 有权
标题翻译： FPGA的非易失性查找表
公开(公告)号：US07321237B2
公开(公告)日：2008-01-22
申请号：US11551973
申请日：2006-10-23
申请人： John McCollum , Gregory Bakker , Jonathan Greene
发明人： John McCollum , Gregory Bakker , Jonathan Greene
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H03K19/17728
摘要： A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A non-volatile memory transistor is coupled to each of the n inputs of the multiplexer. The multiplexer has x address inputs wherein 2x=n as is known in the art. The output of the multiplexer is coupled to VCC through a pullup transistor. The gate of the pullup transistor is coupled to the output of an address transition detector circuit that has inputs coupled to the address inputs of the multiplexer. A sense amplifier is coupled to the output of the multiplexer.
摘要翻译：用于FPGA的基于非易失性存储器晶体管的查找表包括n：1多路复用器。非易失性存储晶体管耦合到多路复用器的n个输入端中的每一个。如本领域已知的那样，多路复用器具有x地址输入，其中2 = n。多路复用器的输出通过上拉晶体管耦合到V CC。上拉晶体管的栅极耦合到具有耦合到多路复用器的地址输入的输入的地址转换检测器电路的输出。读出放大器耦合到多路复用器的输出端。

42. 发明申请

US20070285126A1 ARCHITECTURE FOR ROUTING RESOURCES IN A FIELD PROGRAMMABLE GATE ARRAY 失效
标题翻译：用于在现场可编程门阵列中路由资源的架构
公开(公告)号：US20070285126A1
公开(公告)日：2007-12-13
申请号：US11843575
申请日：2007-08-22
申请人： Sinan Kaptanoglu
发明人： Sinan Kaptanoglu
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17796
摘要： A turning structure for routing channels in a field programmable gate array, comprising a first plurality of routing channels having a first direction and a second plurality of routing channels having a second direction. The first plurality of routing channels intersects the second plurality of routing channels to form a plurality of matrices of intersecting interconnect conductors in the routing channels. A first number of reprogrammable elements is disposed at intersections in at least one of the plurality of matrices, a second number of reprogrammable elements disposed at intersections in at least one of the plurality of matrices. The second number of reprogrammable elements is greater than the first number of reprogrammable elements, and a third number of reprogrammable elements disposed at intersections in at least one of the plurality of matrices. The third number of reprogrammable elements is greater than the second number of reprogrammable elements.
摘要翻译：一种用于在现场可编程门阵列中路由信道的转动结构，包括具有第一方向的第一多个路由信道和具有第二方向的第二多个路由信道。第一多个路由信道与第二多个路由信道相交，以在路由信道中形成多个交叉互连导体矩阵。第一数量的可编程元件设置在多个矩阵中的至少一个矩阵中的交点处，第二数量的可重新编程元件设置在多个矩阵中的至少一个矩阵中的相交处。第二数量的可再编程元件大于第一数量的可再编程元件，并且第三数量的可重新编程元件设置在多个矩阵中的至少一个矩阵中的相交处。第三数量的可编程元件大于第二数量的可编程元件。

43. 发明申请

US20070279122A1 CIRCUIT AND METHOD FOR SUPPLYING PROGRAMMING POTENTIAL AT VOLTAGES LARGER THAN BVDSS OF PROGRAMMING TRANSISTORS 有权
标题翻译：电压超过编程晶体管BVDSS的电压编程电路的电路和方法
公开(公告)号：US20070279122A1
公开(公告)日：2007-12-06
申请号：US11769169
申请日：2007-06-27
申请人： John McCollum
发明人： John McCollum
IPC分类号： H01H37/76
CPC分类号： G11C17/18
摘要： A circuit for programming an antifuse coupled between a first node and a second node includes at least one transistor for supplying a programming potential VPP to the first node. A first transistor has a source coupled to a third node switchably coupleable between a potential of VPP/2 and ground potential, a drain, and a gate. A second transistor has a source coupled to the drain of the first transistor, a drain coupled to the second node, and a gate. Programming circuitry is coupled to the gate of the first transistor and the gate of the second transistor and configured to in a programming mode apply a potential of either zero volts or VPP/2 to the gate of the first transistor and to apply a potential of VPP/2 to the gate of the second transistor. The first and second transistors have a BVDss rating of not more than about VPP/2.
摘要翻译：用于对耦合在第一节点和第二节点之间的反熔丝进行编程的电路包括用于向第一节点提供编程电位V PP的至少一个晶体管。第一晶体管具有耦合到第三节点的源极，其可切换地耦合在V PP / 2/2的电位和地电位之间，漏极和栅极。第二晶体管具有耦合到第一晶体管的漏极的源极，耦合到第二节点的漏极和栅极。编程电路耦合到第一晶体管的栅极和第二晶体管的栅极，并且被配置为在编程模式中将零电压或VPP / 2的电位施加到第一晶体管的栅极，并施加VPP的电位 / 2连接到第二晶体管的栅极。第一和第二晶体管的BVDss等级不大于约V PP / 2。

44. 发明申请

US20070252616A1 PROGRAMMABLE SYSTEM ON A CHIP FOR TEMPERATURE MONITORING AND CONTROL 有权
标题翻译：用于温度监测和控制的芯片可编程系统
公开(公告)号：US20070252616A1
公开(公告)日：2007-11-01
申请号：US11774676
申请日：2007-07-09
申请人： Rabindranath Balasubramanian , Limin Zhu , Gregory Bakker
发明人： Rabindranath Balasubramanian , Limin Zhu , Gregory Bakker
IPC分类号： G06F13/00
CPC分类号： H03K19/1776 , G01K7/015 , G06F1/08 , G06F1/28 , G06F1/30 , G06F15/7842 , G06F15/7867 , H03F3/45475 , H03F2203/45136 , H03F2203/45166 , H03K17/223 , H03K19/177 , H03K19/17732
摘要： A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and temperature sensing and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, or other multiple die configuration. The programmable system-on-a-chip integrated circuit with temperature measuring and control circuitry performs temperature measurement and control functions and can be used to create an on-chip temperature log.
摘要翻译：可编程片上系统集成电路器件包括可编程逻辑块，至少一个用户非易失性存储器块，以及在单个半导体集成电路芯片或倒装芯片上的温度感测和控制模拟和数字电路面对或其他多模配置。具有温度测量和控制电路的可编程片上系统芯片集成电路执行温度测量和控制功能，可用于创建片上温度记录。

45. 发明授权

US07279930B2 Architecture for routing resources in a field programmable gate array 有权
标题翻译：用于在现场可编程门阵列中路由资源的架构
公开(公告)号：US07279930B2
公开(公告)日：2007-10-09
申请号：US11202686
申请日：2005-08-12
申请人： Sinan Kaptanoglu
发明人： Sinan Kaptanoglu
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17796
摘要： A turning structure for routing channels in a field programmable gate array, comprising a first plurality of routing channels having a first direction and a second plurality of routing channels having a second direction. The first plurality of routing channels intersects the second plurality of routing channels to form a plurality of matrices of intersecting interconnect conductors in the routing channels. A first number of reprogrammable elements is disposed at intersections in at least one of the plurality of matrices, a second number of reprogrammable elements disposed at intersections in at least one of the plurality of matrices. The second number of reprogrammable elements is greater than the first number of reprogrammable elements, and a third number of reprogrammable elements disposed at intersections in at least one of the plurality of matrices. The third number of reprogrammable elements is greater than the second number of reprogrammable elements.
摘要翻译：一种用于在现场可编程门阵列中路由信道的转动结构，包括具有第一方向的第一多个路由信道和具有第二方向的第二多个路由信道。第一多个路由信道与第二多个路由信道相交，以在路由信道中形成多个交叉互连导体矩阵。第一数量的可编程元件设置在多个矩阵中的至少一个矩阵中的交点处，第二数量的可重新编程元件设置在多个矩阵中的至少一个矩阵中的相交处。第二数量的可再编程元件大于第一数量的可再编程元件，并且第三数量的可重新编程元件设置在多个矩阵中的至少一个矩阵中的相交处。第三数量的可编程元件大于第二数量的可编程元件。

46. 发明申请

US20070210829A1 BLOCK SYMMETRIZATION IN A FIELD PROGRAMMABLE GATE ARRAY 有权
标题翻译：在现场可编程门阵列中的块对称
公开(公告)号：US20070210829A1
公开(公告)日：2007-09-13
申请号：US11748865
申请日：2007-05-15
申请人： Sinan Kaptanoglu
发明人： Sinan Kaptanoglu
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17728 , H03K19/1778 , H03K19/17796
摘要： An FPGA architecture has top, middle and low levels. The top level is an array of B16×16 tiles enclosed by I/O blocks. The routing resources in the middle level are expressway routing channels including interconnect conductors. At the lowest level, there are block connect routing channels, local mesh routing channels, and direct connect interconnect conductors to connect the logic elements to further routing resources. Each B1 block includes four clusters of devices. Each of the clusters includes first and second LUT3s, a LUT2, and a DFF. Each of the LUT3s have three inputs and one output. Each of the LUT2s have two inputs and one output. Each DFF has a data input and a data output. In each of the clusters the outputs of the LUT3s are multiplexed to the input of DFF, and symmetrized with the output of the DFF to form two outputs of each of the clusters.
摘要翻译： FPGA架构具有顶级，中级和低级。顶级是由I / O块包围的B16x16瓦数组。中间路由资源是高速公路路由信道，包括互连导体。在最底层，有块连接路由通道，本地网状路由通道和直接连接互连导体，以将逻辑元件连接到更多的路由资源。每个B 1块包括四组设备。每个簇包括第一和第二LUT 3 s，LUT 2和DFF。 LUT 3中的每一个具有三个输入和一个输出。 LUT 2中的每一个具有两个输入和一个输出。每个DFF都有数据输入和数据输出。在每个簇中，LUT 3的输出被复用到DFF的输入，并且与DFF的输出对称，以形成每个簇的两个输出。

47. 发明授权

US07268589B2 Address transition detector for fast flash memory device 失效
标题翻译：用于快速闪存器件的地址转换检测器
公开(公告)号：US07268589B2
公开(公告)日：2007-09-11
申请号：US11303863
申请日：2005-12-16
申请人： Poongyeub Lee , Ming-Chi Liu
发明人： Poongyeub Lee , Ming-Chi Liu
IPC分类号： H03K19/00
CPC分类号： G11C7/22 , G11C7/04 , G11C7/08 , G11C7/12 , G11C8/18 , G11C2207/061 , G11C2207/2281 , H03K2005/00039
摘要： An address transition detector circuit includes an input node, an output node, a bandgap reference node, and Pbias and Nbias nodes having voltages derived from the bandgap reference node. First through fifth cascaded inverters are each powered by a p-channel and n-channel MOS bias transistors having their gates coupled respectively to the Pbias node and the Nbias node. The input of the first inverter is coupled to the input node. First and second capacitors are coupled respectively to ground from the outputs of the first and fourth cascaded inverters. A NAND gate has a first input coupled to the input node, a second input coupled the output of the fifth cascaded inverter, and an output coupled to the output node.
摘要翻译：地址转换检测器电路包括具有从带隙参考节点导出的电压的输入节点，输出节点，带隙参考节点和P SUB偏置和N SUB偏置节点。第一到第五级联反相器各自由p沟道和n沟道MOS偏置晶体管供电，其栅极分别耦合到P偏置偏压节点和N SUB偏置节点。第一反相器的输入耦合到输入节点。第一和第二电容器从第一和第四级联逆变器的输出分别耦合到地。 NAND门具有耦合到输入节点的第一输入，耦合第五级联反相器的输出的第二输入和耦合到输出节点的输出。

48. 发明授权

US07224603B1 SRAM cell controlled by flash memory cell 失效
标题翻译：由闪存单元控制的SRAM单元
公开(公告)号：US07224603B1
公开(公告)日：2007-05-29
申请号：US11427456
申请日：2006-06-29
申请人： William C. Plants
发明人： William C. Plants
IPC分类号： G11C14/00
CPC分类号： G11C14/00 , G11C11/412 , G11C14/0063 , H03K19/1776
摘要： First and second complimentary static random-access-memory cell bit lines are coupled to first and second bit nodes through first and second access transistors controlled by a word line. A first inverter has an input coupled to the first bit node and an output coupled to the second bit node. A second inverter has an input coupled to the second bit node and an output coupled to the first bit node through a first transistor switch. A transistor switch is coupled between the output of a non-volatile memory cell and the first bit node. A control circuit coupled to the gate of the transistor switch. Either the drive level of the non-volatile memory cell is selected to overpower the output of the second inverter or the second inverter is decoupled from the first bit node while the output of the non-volatile memory cell is coupled to the first bit node.
摘要翻译：第一和第二互补静态随机存取存储器单元位线通过由字线控制的第一和第二存取晶体管耦合到第一和第二位节点。第一反相器具有耦合到第一位节点的输入和耦合到第二位节点的输出。第二反相器具有耦合到第二位节点的输入和通过第一晶体管开关耦合到第一位节点的输出。晶体管开关耦合在非易失性存储单元的输出和第一位节点之间。耦合到晶体管开关的栅极的控制电路。选择非易失性存储单元的驱动电平以使第二反相器的输出过压，或者第二反相器与第一位节点去耦，而非易失性存储单元的输出耦合到第一位节点。

49. 发明授权

US07212030B1 Field programmable gate array long line routing network 有权
标题翻译：现场可编程门阵列长线路由网络
公开(公告)号：US07212030B1
公开(公告)日：2007-05-01
申请号：US11028471
申请日：2004-12-31
申请人： Volker Hecht
发明人： Volker Hecht
IPC分类号： H03K19/173
CPC分类号： H03K19/17736
摘要： A multi-directional routing repeater has a plurality of buffers, each of the plurality of buffers has an input and an output. The output of each of the plurality of buffers is connected to a separate routing line for transmitting a signal in a separate direction of a first set of routing lines, and the input of each of the plurality of buffers is connected to one of a first set of programmable switches, one of a second set programmable switches, one of a third set of programmable switches, and one of a fourth set of programmable switches, and each one of the first set of programmable switches is connected to a separate one of the second set of programmable switches and a separate one of the second set of programmable switches, none of which are connected to an input of a same one of the plurality of buffers. Each one of the first set of programmable switches is connected to a separate routing line for transmitting a signal in a separate direction of a second set of routing lines.
摘要翻译：多方向路由中继器具有多个缓冲器，多个缓冲器中的每一个具有输入和输出。多个缓冲器中的每一个的输出被连接到单独的路由线路，用于在第一组路由线路的单独方向上发送信号，并且多个缓冲器中的每一个的输入连接到第一组可编程开关之一，第二组可编程开关之一，第三组可编程开关之一和第四组可编程开关之一，并且第一组可编程开关中的每一个连接到第二组可编程开关中的单独一个一组可编程开关和第二组可编程开关中的单独一个，其中没有一个连接到多个缓冲器中相同的一个缓冲器的输入端。第一组可编程开关中的每一个连接到用于在第二组路由线的单独方向上发送信号的分离的路线。

50. 发明授权

US07146441B1 SRAM bus architecture and interconnect to an FPGA 失效
公开(公告)号：US07146441B1
公开(公告)日：2006-12-05
申请号：US10247114
申请日：2002-09-18
申请人： William C. Plants
发明人： William C. Plants
IPC分类号： G06F13/00 , G11C15/00 , H03K19/00
CPC分类号： G11C7/10 , G11C7/18 , G11C8/10 , H03K19/17736 , H03K19/1776
摘要： An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connected in parallel with a tri-state buffer. The pass transistors and tri-state buffers are controlled by configuration SRAM bits. Some of the pass-through interconnect conductors are connected by programmable elements to the address, data and control signal lines of the SRAM blocks, while other pass through the SRAM blocks with out being further connected to the SRAM bussing architecture.

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