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41. 发明授权

US07239549B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07239549B2
公开(公告)日：2007-07-03
申请号：US11132979
申请日：2005-05-19
申请人： Pierre Fazan , Serguei Okhonin
发明人： Pierre Fazan , Serguei Okhonin
IPC分类号： G11C16/04
CPC分类号： H01L27/108 , G11C11/403 , G11C11/404 , G11C11/5621 , G11C2211/4016 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841 , H04N5/3355 , Y10S257/905 , Y10S257/907 , Y10S438/982
摘要： A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate and the drain and between the source and the drain.
摘要翻译：公开了诸如存储器件或辐射检测器的半导体器件，其中在衬底上形成数据存储单元。每个数据存储单元包括具有源极，漏极和栅极的场效应晶体管，以及布置在源极和漏极之间的用于存储在体内产生的电荷的主体。体内净电荷的大小可以通过施加到晶体管的输入信号来调节，并且可以通过在栅极和漏极之间施加电压信号来至少部分地抵消由输入信号调节净电荷在源和漏之间。

42. 发明授权

US07170807B2 Data storage device and refreshing method for use with such device 有权
标题翻译：数据存储装置和与这种装置一起使用的刷新方法
公开(公告)号：US07170807B2
公开(公告)日：2007-01-30
申请号：US11048387
申请日：2005-02-01
申请人： Pierre Fazan , Serguei Okhonin
发明人： Pierre Fazan , Serguei Okhonin
IPC分类号： G11C7/00 , G11C11/24 , G11C11/34
CPC分类号： G11C11/406 , G11C11/404 , G11C2211/4016 , G11C2211/4065 , G11C2211/4068 , H01L2924/15311
摘要： A data storage device such as a DRAM memory having a plurality of data storage cells 10 is disclosed. Each data storage cell 10 has a physical parameter which varies with time and represents one of two binary logic states. A selection circuit 16, writing circuits 18 and a refreshing circuit 22 apply input signals to the data storage cells to reverse the variation of the physical parameter with time of at least those cells representing one of the binary logic states by causing a different variation in the physical parameter of cells in one of said states than in the other.
摘要翻译：公开了诸如具有多个数据存储单元10的DRAM存储器的数据存储装置。每个数据存储单元10具有随时间变化并表示两个二进制逻辑状态之一的物理参数。选择电路16，写入电路18和刷新电路22将输入信号施加到数据存储单元，以通过使代表二进制逻辑状态之一的那些单元的至少那些单元的时间的时间来反转物理参数的变化，在所述状态之一的细胞的物理参数比在另一个状态。

43. 发明授权

US07085153B2 Semiconductor memory cell, array, architecture and device, and method of operating same 失效
标题翻译：半导体存储器单元，阵列，架构和器件及其操作方法
公开(公告)号：US07085153B2
公开(公告)日：2006-08-01
申请号：US10829877
申请日：2004-04-22
申请人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
发明人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
IPC分类号： G11C11/24
CPC分类号： G11C16/28 , G11C11/404 , G11C2211/4013 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory cell and technique of reading data from and writing data into that memory cell. In this regard, in one embodiment of this aspect of the invention, the memory cell includes two transistors which store complementary data states. That is, the two-transistor memory cell includes a first transistor that maintains a complementary state relative to the second transistor. As such, when programmed, one of the transistors of the memory cell stores a logic low (a binary “0”) and the other transistor of the memory cell stores a logic high (a binary “1”). The data state of the two-transistor complementary memory cell may be read and/or determined by sampling, sensing measuring and/or detecting the polarity of the logic states stored in each transistor of complementary memory cell. That is, the two-transistor complementary memory cell is read by sampling, sensing measuring and/or detecting the difference in signals (current or voltage) stored in the two transistors.
摘要翻译：这里描述和说明了许多发明。在第一方面，本发明涉及从该存储单元读取数据并将数据写入该存储单元的存储单元和技术。在这方面，在本发明的这个方面的一个实施例中，存储单元包括存储互补数据状态的两个晶体管。也就是说，双晶体管存储单元包括相对于第二晶体管保持互补状态的第一晶体管。这样，当被编程时，存储单元的一个晶体管存储逻辑低（二进制“0”），并且存储单元的另一晶体管存储逻辑高（二进制“1”）。可以通过采样，感测测量和/或检测存储在互补存储器单元的每个晶体管中的逻辑状态的极性来读取和/或确定双晶体管互补存储单元的数据状态。也就是说，通过采样，感测测量和/或检测存储在两个晶体管中的信号（电流或电压）的差异来读取双晶体管互补存储单元。

44. 发明申请

US20060114717A1 Low power programming technique for a floating body memory transistor, memory cell, and memory array 有权
标题翻译：用于浮体存储晶体管，存储单元和存储器阵列的低功耗编程技术
公开(公告)号：US20060114717A1
公开(公告)日：2006-06-01
申请号：US11334338
申请日：2006-01-17
申请人： Pierre Fazan , Serguei Okhonin
发明人： Pierre Fazan , Serguei Okhonin
IPC分类号： G11C11/34
CPC分类号： G11C11/404 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a memory cell, architecture, and/or array and/or technique of writing or programming data into the memory cell (for example, a technique to write or program a logic low or State “0” in a memory cell employing an electrically floating body transistor. In this regard, the present invention programs a logic low or State “0” in the memory cell while the electrically floating body transistor is in the “OFF” state or substantially “OFF” state (for example, when the device has no (or practically no) channel and/or channel current between the source and drain). In this way, the memory cell may be programmed whereby there is little to no current/power consumption by the electrically floating body transistor and/or from memory array having a plurality of electrically floating body transistors.
摘要翻译：这里描述和说明了许多发明。在一个方面，本发明涉及将数据写入或编程到存储器单元中的存储器单元，架构和/或阵列和/或技术（例如，写入或编程逻辑低或状态“0”的技术在这方面，本发明在电浮动体晶体管处于“关”状态或基本上“关”的情况下，在存储单元中编程逻辑低或状态“0” 状态（例如，当器件在源极和漏极之间没有（或几乎不存在）通道和/或沟道电流）时，可以对存储器单元进行编程，由此存储器单元的电流/功耗很少电浮体晶体管和/或具有多个电浮体晶体管的存储器阵列。

45. 发明授权

US06982918B2 Data storage device and refreshing method for use with such device 有权
标题翻译：数据存储装置和与这种装置一起使用的刷新方法
公开(公告)号：US06982918B2
公开(公告)日：2006-01-03
申请号：US10487162
申请日：2003-03-17
申请人： Pierre Fazan , Serguei Okhonin
发明人： Pierre Fazan , Serguei Okhonin
IPC分类号： G11C11/00
CPC分类号： G11C11/406 , G11C11/404 , G11C2211/4016 , G11C2211/4065 , G11C2211/4068 , H01L2924/15311
摘要： A data storage device such as a DRAM memory having a plurality of data storage cells (10) is disclosed. Each data storage cell (10) has a physical parameter which varies with time and represents one of two binary logic states. A selection circuit (16), writing circuits (18) and a refreshing circuit (22) apply input signals to the data storage cells to reverse the variation of the physical parameter with time of at least those cells representing one of the binary logic states by causing a different variation in the physical parameter of cells in one of said states than in the other.
摘要翻译：公开了诸如具有多个数据存储单元（10）的DRAM存储器的数据存储设备。每个数据存储单元（10）具有随时间变化并表示两个二进制逻辑状态之一的物理参数。选择电路（16），写入电路（18）和刷新电路（22）将输入信号施加到数据存储单元，以通过至少那些表示二进制逻辑状态之一的单元的时间来反转物理参数随时间的变化导致在所述状态之一中的细胞的物理参数的变化比在另一种状态中的不同变化。

46. 发明授权

US06937516B2 Semiconductor device 有权
公开(公告)号：US06937516B2
公开(公告)日：2005-08-30
申请号：US10694689
申请日：2003-10-28
申请人： Pierre Fazan , Serguei Okhonin
发明人： Pierre Fazan , Serguei Okhonin
IPC分类号： G01T1/24 , G11C11/403 , G11C11/404 , H01L21/8242 , H01L27/108 , H01L29/786 , H01L31/10 , G11C16/04
CPC分类号： H01L27/108 , G11C11/403 , G11C11/404 , G11C11/5621 , G11C2211/4016 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841 , H04N5/3355 , Y10S257/905 , Y10S257/907 , Y10S438/982
摘要： A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate and the drain and between the source and the drain.

47. 发明授权

US06930918B2 Semiconductor device 有权
公开(公告)号：US06930918B2
公开(公告)日：2005-08-16
申请号：US10724648
申请日：2003-12-01
申请人： Pierre Fazan , Serguei Okhonin
发明人： Pierre Fazan , Serguei Okhonin
IPC分类号： G01T1/24 , G11C11/403 , G11C11/404 , H01L21/8242 , H01L27/108 , H01L29/786 , H01L31/10 , G11C16/04
CPC分类号： H01L27/108 , G11C11/403 , G11C11/404 , G11C11/5621 , G11C2211/4016 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841 , H04N5/3355 , Y10S257/905 , Y10S257/907 , Y10S438/982
摘要： A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate and the drain and between the source and the drain.

48. 发明授权

US08873283B2 Memory cell and memory cell array having an electrically floating body transistor, and methods of operating same 有权
标题翻译：具有电浮体晶体管的存储单元和存储单元阵列及其操作方法
公开(公告)号：US08873283B2
公开(公告)日：2014-10-28
申请号：US12573203
申请日：2009-10-05
申请人： Serguei Okhonin , Mikhail Nagoga
发明人： Serguei Okhonin , Mikhail Nagoga
IPC分类号： G11C11/34 , G11C11/404 , H01L27/108 , H01L29/78 , G11C11/4076
CPC分类号： G11C11/409 , G11C11/404 , G11C11/4067 , G11C11/4076 , H01L27/108 , H01L27/10802 , H01L27/1203 , H01L29/7841
摘要： A technique of writing, programming, holding, maintaining, sampling, sensing, reading and/or determining the data state of a memory cell of a memory cell array (for example, a memory cell array having a plurality of memory cells which consist of an electrically floating body transistor). In one aspect, the present inventions are directed to techniques to control and/or operate a semiconductor memory cell (and memory cell array having a plurality of such memory cells as well as an integrated circuit device including a memory cell array) having one or more electrically floating body transistors in which an electrical charge is stored in the body region of the electrically floating body transistor. The techniques of the present inventions may employ bipolar transistor currents to control, write and/or read a data state in such a memory cell. In this regard, the present inventions may employ a bipolar transistor current to control, write and/or read a data state in/of the electrically floating body transistor of the memory cell.
摘要翻译：写入，编程，保持，维护，采样，感测，读取和/或确定存储器单元阵列的存储器单元的数据状态（例如，具有多个存储器单元的存储器单元阵列的技术）电浮体晶体管）。一方面，本发明涉及用于控制和/或操作半导体存储单元（以及具有多个这样的存储单元的存储单元阵列以及包括存储单元阵列的集成电路器件）的技术，该半导体存储单元具有一个或多个电浮动体晶体管，其中电荷存储在电浮体晶体管的体区中。本发明的技术可以采用双极晶体管电流来控制，写入和/或读取这种存储单元中的数据状态。在这方面，本发明可以采用双极晶体管电流来控制，写入和/或读取存储单元的电浮体晶体管中的数据状态。

49. 发明授权

US08537610B2 Techniques for providing a semiconductor memory device 有权
标题翻译：提供半导体存储器件的技术
公开(公告)号：US08537610B2
公开(公告)日：2013-09-17
申请号：US12834418
申请日：2010-07-12
申请人： Serguei Okhonin , Viktor I Koldiaev , Mikhail Nagoga , Yogesh Luthra
发明人： Serguei Okhonin , Viktor I Koldiaev , Mikhail Nagoga , Yogesh Luthra
IPC分类号： G11C16/04 , G11C11/24 , H01L29/788
CPC分类号： H01L27/10844 , G11C11/39 , G11C11/403 , G11C11/404 , G11C16/10 , G11C2211/4016 , H01L21/76831 , H01L21/76877 , H01L21/823475 , H01L27/1023 , H01L27/108 , H01L27/10802 , H01L29/66477 , H01L29/7841
摘要： Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region and a second region. The apparatus may also include a body region disposed between the first region and the second region and capacitively coupled to a plurality of word lines, wherein each of the plurality of word lines is capacitively coupled to different portions of the body region.
摘要翻译：公开了一种用于提供半导体存储器件的技术。在一个特定的示例性实施例中，可以将技术实现为包括第一区域和第二区域的装置。该装置还可以包括设置在第一区域和第二区域之间并且电容耦合到多个字线的主体区域，其中多个字线中的每一个电容耦合到身体区域的不同部分。

50. 发明授权

US08508970B2 Techniques for providing a direct injection semiconductor memory device 有权
标题翻译：提供直接注入半导体存储器件的技术
公开(公告)号：US08508970B2
公开(公告)日：2013-08-13
申请号：US12768322
申请日：2010-04-27
申请人： Yogesh Luthra , Serguei Okhonin , Mikhail Nagoga
发明人： Yogesh Luthra , Serguei Okhonin , Mikhail Nagoga
IPC分类号： G11C5/06
CPC分类号： H01L27/0664 , G11C5/025 , G11C5/06 , G11C5/063 , G11C7/00 , G11C8/08 , G11C8/10 , G11C11/4074 , G11C11/4094 , G11C2211/4016 , H01L29/7302 , H01L29/732
摘要： Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device. The method may comprise applying a first voltage potential to a first N-doped region via a bit line and applying a second voltage potential to a second N-doped region via a source line. The method may also comprise applying a third voltage potential to a word line, wherein the word line is spaced apart from and capacitively coupled to a body region that is electrically floating and disposed between the first N-doped region and the second N-doped region. The method may further comprise applying a fourth voltage potential to a P-type substrate via a carrier injection line.
摘要翻译：公开了提供直接注入半导体存储器件的技术。在一个特定的示例性实施例中，可以将技术实现为用于偏置直接注入半导体存储器件的方法。该方法可以包括经由位线将第一电压电势施加到第一N掺杂区域，并且经由源极线将第二电压电势施加到第二N掺杂区域。该方法还可以包括将第三电压电位施加到字线，其中字线与电浮置并且设置在第一N掺杂区域和第二N掺杂区域之间的体区间隔开并且电容耦合。该方法还可以包括经由载体注入管线向P型衬底施加第四电压电位。

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