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41. 发明申请

US20050104654A1 Technique for improving antialiasing and adjacent channel interference filtering using cascaded passive IIR filter stages combined with direct sampling and mixing 有权
标题翻译：使用级联无源IIR滤波器级与直接采样和混合相结合的改进抗混叠和相邻信道干扰滤波的技术
公开(公告)号：US20050104654A1
公开(公告)日：2005-05-19
申请号：US10712593
申请日：2003-11-13
申请人： Khurram Muhammad , Robert Staszewski , Dirk Leipold
发明人： Khurram Muhammad , Robert Staszewski , Dirk Leipold
IPC分类号： H03B1/00 , H03H19/00 , H04B1/10
CPC分类号： H04B1/109 , H03H19/004
摘要： A technique of improving antialiasing and adjacent channel interference filtering uses cascaded passive IIR filter stages combined with direct sampling and mixing. The methodology and related architecture allows for increased passive IIR filtering without necessitating use of amplifier stages.
摘要翻译：改进抗混叠和相邻信道干扰滤波的技术使用级联无源IIR滤波器级与直接采样和混合相结合。该方法和相关架构允许增加无源IIR滤波，而不需要使用放大器级。

42. 发明授权

US06791422B2 Frequency synthesizer with digitally-controlled oscillator 有权
标题翻译：具有数字控制振荡器的频率合成器
公开(公告)号：US06791422B2
公开(公告)日：2004-09-14
申请号：US10679792
申请日：2003-10-06
申请人： Robert B. Staszewski , Dirk Leipold , Khurram Muhammad , Chih-Ming Hung
发明人： Robert B. Staszewski , Dirk Leipold , Khurram Muhammad , Chih-Ming Hung
IPC分类号： H03L700
CPC分类号： H03C3/0975 , H03C3/0941 , H03C3/095 , H03C3/0958 , H03C3/0966 , H03K19/0016 , H03L7/085 , H03L7/087 , H03L7/091 , H03L7/093 , H03L7/099 , H03L7/16 , H03L2207/50 , H04L7/0029
摘要： A transmitter (10) based on a frequency synthesizer includes an LC tank (12) of a digitally controlled oscillator (DCO) with various arrays of capacitors. The LC tank 12 is divided into two major groups that reflect two general operational modes: acquisition and tracking. The first group (process/voltage/temperature and acquisition) approximately sets the desired center frequency of oscillation initially, while the second group (integer and fractional tracking) precisely controls the oscillating frequency during the actual operation. For highly accurate outputs, dynamic element matching (DEM) is used in the integer tracking controller to reduce non-linearities caused by non-uniform capacitor values. Also, a preferred range of the integer tracking capacitor array may be used for modulation after the selected channel has been acquired. A digital sigma-delta modulator circuit (50) drives a capacitor array (14d) in response to the fractional bits of the error word. On mode switches, the accumulated error is recalculated to a phase restart value to prevent perturbations.
摘要翻译：基于频率合成器的发射机（10）包括具有各种电容器阵列的数字控制振荡器（DCO）的LC箱（12）。液相色谱箱12分为反映两种一般操作模式的两个主要组：采集和跟踪。第一组（过程/电压/温度和采集）最初初始化设置所需的中心振荡频率，而第二组（整数和分数跟踪）在实际操作期间精确地控制振荡频率。对于高精度输出，在整数跟踪控制器中使用动态元件匹配（DEM）来减少由非均匀电容值引起的非线性。此外，在获取所选择的信道之后，整数跟踪电容器阵列的优选范围可以用于调制。数字Σ-Δ调制器电路（50）响应错误字的分数位驱动电容器阵列（14d）。在模式开关上，累加误差被重新计算到相位重启值，以防止扰动。

43. 发明授权

US08411793B2 Digital amplitude modulation 有权
标题翻译：数字幅度调制
公开(公告)号：US08411793B2
公开(公告)日：2013-04-02
申请号：US13081338
申请日：2011-04-06
申请人： Robert B. Staszewski , Sameh Rezeq , Dirk Leipold
发明人： Robert B. Staszewski , Sameh Rezeq , Dirk Leipold
IPC分类号： H04K1/02
CPC分类号： H04L27/361
摘要： A transmitter using quadrature modulation includes a rectangular to polar converter for converting data symbols into a polar form, where each polar symbol has a magnitude signal and an angle signal. Digital phase modulation circuitry includes an all digital PLL circuit for generating a phase modulated RF carrier signal responsive to the angle signal frequency control word (FCW) and a carrier frequency FCW. A digitally controlled amplifier for amplifying the phase modulated signal is controlled by a digital amplitude control circuitry for controlling the gain of the digitally controlled amplifier responsive to the magnitude signal.
摘要翻译：使用正交调制的发射机包括用于将数据符号转换成极性形式的矩形到极化转换器，其中每个极性符号具有幅度信号和角度信号。数字相位调制电路包括全数字PLL电路，用于响应角度信号频率控制字（FCW）和载波频率FCW产生相位调制的RF载波信号。用于放大相位调制信号的数字控制放大器由数字幅度控制电路控制，用于响应于幅度信号来控制数字控制放大器的增益。

44. 发明授权

US07767995B2 Single-electron tunnel junction for complementary metal-oxide device and method of manufacturing the same 有权
标题翻译：用于互补金属氧化物器件的单电子隧道结及其制造方法
公开(公告)号：US07767995B2
公开(公告)日：2010-08-03
申请号：US11846993
申请日：2007-08-29
申请人： Robert B. Staszewski , Renaldi Winoto , Dirk Leipold
发明人： Robert B. Staszewski , Renaldi Winoto , Dirk Leipold
IPC分类号： H01L29/06
CPC分类号： H01L27/092 , H01L29/66151 , H01L29/88 , Y10S438/979 , Y10S977/937
摘要： A method of providing a p-type substrate, disposing a pad oxide layer on the p-type substrate, disposing a nitride layer on the pad oxide layer, forming a nitride window in the nitride layer, disposing a field oxide in the nitride window, disposing a polysilicon gate over the field oxide, and diffusing a n-doped region in the p-type substrate, thereby forming at least one single-electron tunnel junction between the polysilicon gate and the n-doped region.
摘要翻译：一种提供p型衬底的方法，在p型衬底上设置焊盘氧化物层，在衬垫氧化物层上设置氮化物层，在氮化物层中形成氮化物窗，在氮化物窗中设置场氧化物，在场氧化物上设置多晶硅栅极，并扩散p型衬底中的n掺杂区域，从而在多晶硅栅极和n掺杂区域之间形成至少一个单电子隧道结。

45. 发明授权

US07483508B2 All-digital frequency synthesis with non-linear differential term for handling frequency perturbations 有权
标题翻译：用于处理频率扰动的非线性微分项的全数字频率合成
公开(公告)号：US07483508B2
公开(公告)日：2009-01-27
申请号：US10306655
申请日：2002-11-27
申请人： Robert B. Staszewski , Dirk Leipold
发明人： Robert B. Staszewski , Dirk Leipold
IPC分类号： H03D3/24
CPC分类号： H03L7/085 , H03L7/0991
摘要： An all-digital frequency synthesizer architecture is built around a digitally controlled oscillator (DCO) that is tuned in response to a digital tuning word (OTW). In exemplary embodiments: (1) a gain characteristic (KDCO) of the digitally controlled oscillator can be determined by observing a digital control word before and after a known change (Δfmax) in the oscillating frequency; (2) a portion (TUNE_TF) of the tuning word can be dithered (1202), and the resultant dithered portion (dkTF) can then be applied to a control input of switchable devices within the digitally controlled oscillator; and (3) a non-linear differential term (187, 331) can be used to expedite correction of the digitally controlled oscillator when large phase error changes (335) occur.
摘要翻译：全数字频率合成器架构围绕数字控制振荡器（DCO）构建，该振荡器响应于数字调谐字（OTW）进行调谐。在示例性实施例中：（1）数字控制振荡器的增益特性（KDCO）可以通过在振荡频率中的已知改变（Deltafmax）之前和之后观察数字控制字来确定; （2）可以对调谐字的一部分（TUNE_TF）进行抖动（1202），然后将所得到的抖动部分（dkTF）施加到数字控制振荡器内的可切换装置的控制输入端; 和（3）当大相位误差变化（335）发生时，可以使用非线性微分项（187,331）来加速数字控制振荡器的校正。

46. 发明授权

US07427940B2 Time-to-digital converter with non-inverting buffers, transmission gates and non-linearity corrector, SOC including such converter and method of phase detection for use in synthesizing a clock signal 有权
标题翻译：具有非反相缓冲器，传输门和非线性校正器的时间到数字转换器，包括这种转换器的SOC和用于合成时钟信号的相位检测方法
公开(公告)号：US07427940B2
公开(公告)日：2008-09-23
申请号：US11690506
申请日：2007-03-23
申请人： Robert Bogdan Staszewski , Dirk Leipold , Wei Chen
发明人： Robert Bogdan Staszewski , Dirk Leipold , Wei Chen
IPC分类号： H03M1/12 , H03L7/06
CPC分类号： H03L7/091 , H03L2207/50
摘要： A time-to-digital converter (TDC), a system-on-chip including a TDC, a method of phase detection for use in synthesizing a clock signal and a non-linearity corrector for a TDC. In one embodiment, the TDC includes a chain of delay elements configured to receive a clock signal and generate delayed clock signals. Each one of the delay elements includes: (1) a non-inverting buffer configured to delay the clock signal by about twice a delay of an inverter to provide a buffer-delayed clock signal and (2) a first transmission gate coupled to the non-inverting buffer and configured to delay the clock signal by about the delay of an inverter to provide a first gate-delayed clock signal.
摘要翻译：时间数字转换器（TDC），包括TDC的片上系统，用于合成时钟信号的相位检测方法和用于TDC的非线性校正器。在一个实施例中，TDC包括被配置为接收时钟信号并产生延迟的时钟信号的延迟元件链。每个延迟元件包括：（1）非反相缓冲器，被配置为将时钟信号延迟约两倍的逆变器的延迟以提供缓冲器延迟的时钟信号，以及（2）耦合到非反相缓冲器的第一传输门反相缓冲器并且被配置为将时钟信号延迟大约逆变器的延迟以提供第一门延迟的时钟信号。

47. 发明授权

US07405685B2 Negative contributive offset compensation in a transmit buffer utilizing inverse clocking 有权
标题翻译：使用反向时钟的发送缓冲器中的负贡献偏移补偿
公开(公告)号：US07405685B2
公开(公告)日：2008-07-29
申请号：US11178993
申请日：2005-07-11
申请人： Sameh S. Rezeq , Dirk Leipold , Robert B. Staszewski , Chih-Ming Hung
发明人： Sameh S. Rezeq , Dirk Leipold , Robert B. Staszewski , Chih-Ming Hung
IPC分类号： H03M3/00
CPC分类号： H03F1/0205 , H03F1/3241 , H03F2200/331 , H03F2200/375 , H03M3/356 , H03M3/50 , H03M7/3026 , H03M7/3037 , H04L27/368
摘要： A novel method and apparatus for a negative contributive offset compensation mechanism for a transmit buffer adapted to compensate for the positive offset generated by higher order sigma-delta modulators used to amplitude modulate the transmit buffer. The positive outputs from the sigma-delta modulator are processed differently than the negative outputs. The inverters associated with the negative outputs in the sigma-delta modulator are removed and the clock signal used to drive the transistors corresponding to the negative outputs is negated or shifted 180 degrees from the clock used to drive the transistors corresponding to the positive outputs. A non-inverted version of the clock is used with the positive outputs and an inverse clock is used with the negative outputs. Use of the inverse clock causes a negative contributive offset to be generated that is added on the second half cycle of each clock. The result is an offset compensated RF output signal having zero offset.
摘要翻译：一种用于发射缓冲器的负贡献偏移补偿机制的新颖方法和装置，适用于补偿由用于幅度调制发射缓冲器的高阶Σ-Δ调制器产生的正偏移。来自Σ-Δ调制器的正输出的处理方式与负输出不同。与Σ-Δ调制器中的负输出相关联的反相器被去除，并且用于驱动对应于负输出的晶体管的时钟信号与用于驱动对应于正输出的晶体管的时钟相反或偏移180度。时钟的非反相版本与正输出一起使用，反向时钟与负输出一起使用。使用逆时钟将产生在每个时钟的第二个半周期上添加的负贡献偏移。结果是具有零偏移的偏移补偿RF输出信号。

48. 发明授权

US07254755B2 On-chip receiver sensitivity test mechanism 有权
标题翻译：片上接收机灵敏度测试机制
公开(公告)号：US07254755B2
公开(公告)日：2007-08-07
申请号：US10759911
申请日：2004-01-16
申请人： Elida Isabel de Obaldia , Dirk Leipold , Oren Eliezer , Ran Katz , Bogdan Staszewski
发明人： Elida Isabel de Obaldia , Dirk Leipold , Oren Eliezer , Ran Katz , Bogdan Staszewski
IPC分类号： H04B17/00
CPC分类号： H04B17/0085 , G01R31/2822 , H04B17/29 , H04L1/24
摘要： An on-chip receiver sensitivity test mechanism for use in an integrated RF transmitter wherein the transmitter and the receiver share the same oscillator. The mechanism obviates the need to use expensive RF signal generator test equipment with built-in modulation capability and instead permits the use of very low cost external RF test equipment. The invention utilizes circuitry already existing in the transceiver, namely the modulation circuitry and local oscillator, to perform sensitivity testing. The on-chip LO is used to generate the modulated test signal that otherwise would need to be provided by expensive external RF test equipment with modulation capability. The modulated LO signal is mixed with an externally generated unmodulated CW RF signal to generate a modulated signal at IF which is subsequently processed by the remainder of the receiver chain. The recovered data bits are compared using an on-chip BER meter or counter and a BER reading is generated. The BER reading is used either externally or by an on-chip processor or controller to establish a pass/fail indication for the chip.
摘要翻译：用于集成RF发射机的片上接收机灵敏度测试机构，其中发射机和接收机共享相同的振荡器。该机构避免了使用具有内置调制能力的昂贵的RF信号发生器测试设备的需要，并且允许使用非常低成本的外部RF测试设备。本发明利用已经存在于收发器中的电路，即调制电路和本地振荡器来执行灵敏度测试。片上LO用于产生调制测试信号，否则将需要由具有调制能力的昂贵的外部RF测试设备提供。调制的LO信号与外部产生的未调制的CW RF信号混合以在IF处产生调制信号，随后由接收机链的其余部分处理。恢复的数据位使用片上BER计或计数器进行比较，产生BER读数。 BER读取在外部使用或由片上处理器或控制器用于建立芯片的通过/失败指示。

49. 发明申请

US20060033582A1 Gain calibration of a digital controlled oscillator 有权
标题翻译：增益数字控制振荡器的校准
公开(公告)号：US20060033582A1
公开(公告)日：2006-02-16
申请号：US11149859
申请日：2005-06-10
申请人： Robert Staszewski , Gennady Feygin , Oren Eliezer , Dirk Leipold
发明人： Robert Staszewski , Gennady Feygin , Oren Eliezer , Dirk Leipold
IPC分类号： H03L7/00
CPC分类号： H03L7/0991 , H03L7/085 , H03L2207/50
摘要： A novel apparatus for and a method of estimating, calibrating and tracking in real-time the gain of a radio frequency (RF) digitally controlled oscillator (DCO) in an all-digital phase locked loop (ADPLL). Precise setting of the inverse DCO gain in the ADPLL modulating path allows direct wideband frequency modulation that is independent of the ADPLL loop bandwidth. The gain calibration technique is based on a steepest descent iterative algorithm wherein the phase ADPLL error is sampled and correlated with the modulating data to generate a gradient. The gradient is then scaled and added to the current value of the DCO gain multiplier.
摘要翻译：一种用于实时估计，校准和跟踪全数字锁相环（ADPLL）中的射频（RF）数字控制振荡器（DCO）的增益的新型装置和方法。 ADPLL调制路径中逆DCO增益的精确设置允许直接宽带频率调制，与ADPLL环路带宽无关。增益校准技术基于最速下降迭代算法，其中相位ADPLL误差被采样并与调制数据相关以产生梯度。然后将梯度缩放并添加到DCO增益乘数的当前值。

50. 发明申请

US20050264333A1 Efficient pulse amplitude modulation transmit modulation 有权
公开(公告)号：US20050264333A1
公开(公告)日：2005-12-01
申请号：US11195060
申请日：2005-08-02
申请人： Robert Staszewski , Dirk Leipold , Kenneth Maggio
发明人： Robert Staszewski , Dirk Leipold , Kenneth Maggio
IPC分类号： H03F1/02 , H03F1/06 , H03F3/217 , H03K3/00 , H03K3/017 , H03K5/06 , H03K7/02 , H04B1/04
CPC分类号： H03F1/02 , H03F1/0205 , H03F3/217 , H03F3/2171 , H03F3/2176 , H03F2200/331 , H03K5/06 , H03K7/02 , H04B1/0483 , H04B2001/0491
摘要： Efficient PAM transmit modulation is provided by a PAM modulator that includes an oscillator (404) that provides a clock signal, CKV, (408). The clock signal 408 and a delayed version (CKV_DLY) 420 of the clock signal are provided to a logic gate (414). The output of logic gate (414) is used as a power amplifier input signal (PA_IN) for radio frequency power amplifier (416). Depending on the relative time delay of the CKV clock signal (408) and the CKV_DLY delayed clock signal (420), the timing and duty cycle of the logic gate (414) duty cycle can be controlled. The duty cycle or pulse-width variation affects the turn-on time of the power amplifier (416); thereby establishing the RF output amplitude.

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