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1. 发明授权

US07983375B2 Variable delay oscillator buffer 有权
标题翻译：可变延迟振荡器缓冲器
公开(公告)号：US07983375B2
公开(公告)日：2011-07-19
申请号：US12021205
申请日：2008-01-28
申请人： Fikret Dulger , Robert B. Staszewski , Francis P. Cruise , Gennady Feygin
发明人： Fikret Dulger , Robert B. Staszewski , Francis P. Cruise , Gennady Feygin
IPC分类号： H03D3/24
CPC分类号： H03L7/1806 , H03L2207/50
摘要： A novel and useful variable delay digitally controlled crystal oscillator (DCXO) buffer (i.e. slicer). A conventional slicer following the DCXO is modified to introduce a controlled random variable delay into the buffered DCXO clock. The resultant output clock signal is then used as input to the TDC of an ADPLL circuit to alleviate the subharmonic mixing based deterioration caused by LO/TX coupling through the crystal pins, and to alleviate the dead-beat effects caused by the finite resolution of the TDC. Two mechanisms for introducing variable delay into the buffered DCXO output clock signal are presented: a first mechanism that creates variable delay in fine steps and a second mechanism that creates variable delay in coarse steps. In both mechanisms, switches are incorporated into the slicer circuitry and controlled using digital bit sequences which may comprise dithering signals. The switches are turned on and off via the digital bit sequences which varies the delay of the slicer clock output which serves to shift the rising and falling transition points of the resultant output clock signal. The jitter is shifted to higher frequencies where it is filtered out by the PLL loop filter.
摘要翻译：一种新颖有用的可变延迟数字控制晶体振荡器（DCXO）缓冲器（即切片器）。在DCXO之后的常规限幅器被修改以将受控的随机可变延迟引入缓冲的DCXO时钟。结果输出时钟信号然后被用作ADPLL电路的TDC的输入，以减轻由通过晶体管的LO / TX耦合引起的次谐波混合的劣化，并且减轻由于有限分辨率引起的死区效应 TDC。介绍了将可变延迟引入到缓冲DCXO输出时钟信号中的两种机制：第一种在精细步骤中产生可变延迟的机制，以及在粗略步骤中产生可变延迟的第二种机制。在这两种机制中，开关被合并到限幅器电路中，并使用可包括抖动信号的数字位序列进行控制。开关通过改变切片器时钟输出的延迟的数字位序列被导通和关断，其用于移位所产生的输出时钟信号的上升和下降转换点。抖动被转移到较高的频率，由PLL环路滤波器滤波。

2. 发明申请

US20100244976A1 Clock Spreading Systems and Methods 有权
标题翻译：时钟传播系统和方法
公开(公告)号：US20100244976A1
公开(公告)日：2010-09-30
申请号：US12415213
申请日：2009-03-31
申请人： Jeff Kerr , Gennady Feygin , Jose Fresquez
发明人： Jeff Kerr , Gennady Feygin , Jose Fresquez
IPC分类号： H03C3/00 , H03H11/16
CPC分类号： H04B15/02 , H03K7/06 , H04B2215/067
摘要： Clock spreading systems and methods are disclosed. In one embodiment of the invention, a clock spreading system is provided in an integrated transceiver system that comprises a base band control system and a transceiver coupled to the base band control system. The clock spreading system provides a spread clock output signal derived from a clock reference signal for clocking one of the base band control system and the transceiver. The clock spreading system is configured to provide a periodic phase modulated spread clock output signal during receiving of data in a receive mode and a pseudo-random phase modulated spread clock output signal during transmitting of data in a transmit mode.
摘要翻译：公开了时钟扩展系统和方法。在本发明的一个实施例中，在包括基带控制系统和耦合到基带控制系统的收发器的集成收发器系统中提供时钟扩展系统。时钟扩展系统提供从时钟参考信号导出的扩展时钟输出信号，用于对基带控制系统和收发机之一进行计时。时钟扩展系统被配置为在以发送模式发送数据期间接收接收模式下的数据和伪随机相位调制扩展时钟输出信号期间提供周期性相位调制扩展时钟输出信号。

3. 发明授权

US07647192B2 Active removal of aliasing frequencies in a decimating structure by changing a decimation ratio in time and space 有权
标题翻译：通过在时间和空间上改变抽取比例，在抽取结构中主动去除混叠频率
公开(公告)号：US07647192B2
公开(公告)日：2010-01-12
申请号：US10924297
申请日：2004-08-23
申请人： Khurram Muhammad , Robert B. Staszewski , Gennady Feygin
发明人： Khurram Muhammad , Robert B. Staszewski , Gennady Feygin
IPC分类号： G06F19/00
CPC分类号： H03D7/125 , H04B1/1036
摘要： When a sample stream is decimated, frequency components from outside of a desired frequency band are aliased into the desired band, causing interference and loss of information. Different decimating ratios result in different frequencies aliasing into the desired frequency band. A current-mode sampling mixer 800 with capacitor banks 811 and 812 that are controlled by a digital control unit 820 with a capability to integrate and decimate an RF current at different decimating ratios is able to measure the frequency spectrum with different decimating ratios. The measured frequency spectrum is then analyzed to detect the presence of interferers aliased into the desired frequency band. The interferers can then be eliminated or avoided.
摘要翻译：当采样流被抽取时，来自期望频带外部的频率分量被混叠成所需频带，导致信息的干扰和丢失。不同的抽取率导致不同的频率混叠成所需的频带。具有电容器组811和812的电流模式采样混频器800能够以不同的抽取率对能够集成和抽取RF电流的数字控制单元820进行控制，能够以不同的抽取率来测量频谱。然后分析测量的频谱以检测混叠到期望频带中的干扰源的存在。然后可以消除或避免干扰源。

4. 发明申请

US20080042755A1 Method and apparatus to provide digitally controlled crystal oscillators 有权
标题翻译：提供数字控制晶体振荡器的方法和装置
公开(公告)号：US20080042755A1
公开(公告)日：2008-02-21
申请号：US11500083
申请日：2006-08-07
申请人： Gennady Feygin , Khurram Muhammad , Chih-Ming Hung , Meng-Chang Lee
发明人： Gennady Feygin , Khurram Muhammad , Chih-Ming Hung , Meng-Chang Lee
IPC分类号： H03L7/00
CPC分类号： H03L7/24 , H03L1/026 , H03L3/00 , H03L7/0995
摘要： Methods and systems to provide digitally controlled crystal oscillators are disclosed. One example method includes determining a state of an oscillator system and selecting a first output of a digitally controlled crystal oscillator or a second output of a second oscillator based on the determination. In an example implementation, the second oscillator is a ring oscillator.
摘要翻译：公开了提供数字控制晶体振荡器的方法和系统。一个示例性方法包括基于该确定来确定振荡器系统的状态并选择数字控制的晶体振荡器的第一输出或第二振荡器的第二输出。在示例实现中，第二振荡器是环形振荡器。

5. 发明授权

US06259385B1 System for data transceiving using run-length constrained convolutional codes 有权
标题翻译：使用游程长度限制卷积码的数据收发系统
公开(公告)号：US06259385B1
公开(公告)日：2001-07-10
申请号：US09356388
申请日：1999-07-16
申请人： Gennady Feygin , Khurram Muhammad
发明人： Gennady Feygin , Khurram Muhammad
IPC分类号： H03M700
CPC分类号： H03M7/46
摘要： A method is disclosed for enforcing run-length limit constraints convolutional codes, comprising the steps of providing a desired run length limit constraint, providing a first convolutional code structure 202, processing data with the first convolutional code structure 202 such that convolutional code structure 202 applies a predetermined patterning to the data, evaluating and processing the data in reference to the desired run length limit constraint such that any of the data that is not compliant with the run length limit constraint is altered to become compliant, further processing said the data by a transceiver 206, providing a second convolutional code structure 204, evaluating the further processed data with convolutional code structure 204 in reference to the predetermined patterning such that data likely to have been previously altered is identified, and processing the further processed data with convolutional code structure 204 in reference to said predetermined patterning such that data identified as likely to have been previously altered is excluded.
摘要翻译：公开了一种用于执行游程长度限制约束卷积码的方法，包括以下步骤：提供期望的游程长度限制约束，提供第一卷积码结构202，使用第一卷积码结构202处理数据，使得卷积码结构202适用对数据进行预定的图案化，参考期望的游程长度限制约束来评估和处理数据，使得不符合游程长度限制约束的任何数据被改变以变得兼容，进一步处理所述数据收发器206，提供第二卷积码结构204，参考预定图案化，利用卷积码结构204评估进一步处理的数据，以便识别出可能已经改变的数据，并用卷积码结构204处理进一步处理的数据参考所述预定图案化确定可能已被更改的数据被排除在外。

6. 发明授权

US07183860B2 Gain calibration of a digital controlled oscillator 有权
标题翻译：增益数字控制振荡器的校准
公开(公告)号：US07183860B2
公开(公告)日：2007-02-27
申请号：US11149859
申请日：2005-06-10
申请人： Robert B. Staszewski , Gennady Feygin , Oren E. Eliezer , Dirk Leipold
发明人： Robert B. Staszewski , Gennady Feygin , Oren E. Eliezer , Dirk Leipold
IPC分类号： H03C3/06 , H03L7/091 , H03L7/099
CPC分类号： H03L7/0991 , H03L7/085 , H03L2207/50
摘要： A novel apparatus for and a method of estimating, calibrating and tracking in real-time the gain of a radio frequency (RF) digitally controlled oscillator (DCO) in an all-digital phase locked loop (ADPLL). Precise setting of the inverse DCO gain in the ADPLL modulating path allows direct wideband frequency modulation that is independent of the ADPLL loop bandwidth. The gain calibration technique is based on a steepest descent iterative algorithm wherein the phase ADPLL error is sampled and correlated with the modulating data to generate a gradient. The gradient is then scaled and added to the current value of the DCO gain multiplier.
摘要翻译：一种用于实时估计，校准和跟踪全数字锁相环（ADPLL）中的射频（RF）数字控制振荡器（DCO）的增益的新型装置和方法。 ADPLL调制路径中逆DCO增益的精确设置允许直接宽带频率调制，与ADPLL环路带宽无关。增益校准技术基于最速下降迭代算法，其中相位ADPLL误差被采样并与调制数据相关以产生梯度。然后将梯度缩放并添加到DCO增益乘数的当前值。

7. 发明授权

US06856925B2 Active removal of aliasing frequencies in a decimating structure by changing a decimation ratio in time and space 有权
公开(公告)号：US06856925B2
公开(公告)日：2005-02-15
申请号：US10269349
申请日：2002-10-11
申请人： Khurram Muhammad , Robert B. Staszewski , Gennady Feygin
发明人： Khurram Muhammad , Robert B. Staszewski , Gennady Feygin
IPC分类号： H03D7/12 , H04B1/10 , G06F19/00
CPC分类号： H03D7/125 , H04B1/1036
摘要： When a sample stream is decimated, frequency components from outside of a desired frequency band are aliased into the desired band, causing interference and loss of information. Different decimating ratios result in different frequencies aliasing into the desired frequency band. A current-mode sampling mixer 800 with capacitor banks 811 and 812 that are controlled by a digital control unit 820 with a capability to integrate and decimate an RF current at different decimating ratios is able to measure the frequency spectrum with different decimating ratios. The measured frequency spectrum is then analyzed to detect the presence of interferers aliased into the desired frequency band. The interferers can then be eliminated or avoided.

8. 发明申请

US20050025270A1 Active removal of aliasing frequencies in a decimating structure by changing a decimation ratio in time and space 有权
公开(公告)号：US20050025270A1
公开(公告)日：2005-02-03
申请号：US10924303
申请日：2004-08-23
申请人： Khurram Muhammad , Robert Staszewski , Gennady Feygin
发明人： Khurram Muhammad , Robert Staszewski , Gennady Feygin
IPC分类号： H03D7/12 , H04B1/10 , H03D3/22
CPC分类号： H03D7/125 , H04B1/1036
摘要： When a sample stream is decimated, frequency components from outside of a desired frequency band are aliased into the desired band, causing interference and loss of information. Different decimating ratios result in different frequencies aliasing into the desired frequency band. A current-mode sampling mixer 800 with capacitor banks 811 and 812 that are controlled by a digital control unit 820 with a capability to integrate and decimate an RF current at different decimating ratios is able to measure the frequency spectrum with different decimating ratios. The measured frequency spectrum is then analyzed to detect the presence of interferers aliased into the desired frequency band. The interferers can then be eliminated or avoided.

9. 发明授权

US06420983B1 On-line offset cancellation in flash A/D with interpolating comparator array 有权
标题翻译：带内插比较器阵列的闪存A / D中的在线偏移消除
公开(公告)号：US06420983B1
公开(公告)日：2002-07-16
申请号：US09578283
申请日：2000-05-25
申请人： Gennady Feygin , David A. Martin , Krishnasawamy Nagaraj
发明人： Gennady Feygin , David A. Martin , Krishnasawamy Nagaraj
IPC分类号： H03M106
CPC分类号： H03M1/1004 , H03M1/1023 , H03M1/204 , H03M1/365
摘要： A method for performing an auto-zero function in a flash analog to digital converter (“ADC”), the ADC including a reference voltage circuit, providing a plurality of evenly spaced analog reference voltages, and a plurality of system voltage comparators for comparing an input voltage against the reference voltages and providing an indication of which reference voltage corresponds to the input voltage. In the method the following steps are performed. A plurality of redundant voltage comparators are provided. A subset of the plurality of system voltage comparators are selected. Auto-zero is performed on the selected comparators, and the redundant comparators are used in the place of the selected comparators. The outputs of the main comparator array and the extra comparators are combined to produce a final digital output.
摘要翻译：一种用于在闪存模数转换器（“ADC”）中执行自动归零功能的方法，所述ADC包括提供多个均匀间隔的模拟参考电压的参考电压电路，以及多个系统电压比较器，用于将相对于参考电压的输入电压并且提供哪个参考电压对应于输入电压的指示。在该方法中，执行以下步骤。提供多个冗余电压比较器。选择多个系统电压比较器的子集。在所选择的比较器上执行自动归零，并使用冗余比较器代替所选的比较器。主比较器阵列和额外的比较器的输出被组合以产生最终的数字输出。

10. 发明授权

US06212664B1 Method and system for estimating an input data sequence based on an output data sequence and hard disk drive incorporating same 失效
标题翻译：用于基于输出数据序列和包含其的硬盘驱动器来估计输入数据序列的方法和系统
公开(公告)号：US06212664B1
公开(公告)日：2001-04-03
申请号：US09060918
申请日：1998-04-15
申请人： Gennady Feygin , Robert B. Staszewski , Michel Combes
发明人： Gennady Feygin , Robert B. Staszewski , Michel Combes
IPC分类号： H03M1303
CPC分类号： H03M13/39
摘要： A method for generating an updated path metric includes combining each of first and second provisional path metric first portions with an associated branch metric first portion to produce a first provisional updated path metric first portion candidate and a second provisional updated path metric first portion candidate, respectively. The method also includes selecting one of the provisional first portion updated path metric candidates to produce an updated path metric first portion candidate and combining any carry component of the selected updated path metric first portion candidate with a path metric second portion and a branch metric second portion to produce a first updated path metric second portion candidate. The method also includes comparing the updated path metric second portion candidate to at least one other updated path metric second portion candidate; and selecting one of the updated path metric second portion candidates to produce an updated path metric second portion.
摘要翻译：用于生成更新的路径量度的方法包括将第一和第二临时路径度量第一部分中的每一个与相关联的分支度量第一部分组合以分别产生第一临时更新路径度量第一部分候选和第二临时更新路径量度第一部分候选。该方法还包括选择临时第一部分更新路径度量候选之一以产生更新的路径量度第一部分候选，并将所选择的更新路径度量第一部分候选的任何进位分量与路径度量第二部分和分支度量第二部分以产生第一更新路径度量第二部分候选。该方法还包括将更新的路径度量第二部分候选与至少一个其他更新路径度量第二部分候选进行比较; 以及选择更新的路径度量第二部分候选中的一个，以产生更新的路径量度第二部分。

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