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51. 发明申请

US20070013351A1 Electric power unit operating in continuous and discontinuous conduction modes and control method therefor 失效
标题翻译：电力单元在连续和不连续导通模式下工作及其控制方法
公开(公告)号：US20070013351A1
公开(公告)日：2007-01-18
申请号：US11485466
申请日：2006-07-13
申请人： Toshiyuki Naka , Akio Nakagawa , Kazutoshi Nakamura
发明人： Toshiyuki Naka , Akio Nakagawa , Kazutoshi Nakamura
IPC分类号： G05F1/00
CPC分类号： H02M3/157 , H02M3/1588 , Y02B70/1466
摘要： An electronic power unit includes first and second MOS transistors and a digital control circuit. The first MOS transistor applies a voltage to the load. The second MOS transistor remains on while the first MOS transistor remains off and rectifies the current flowing in the load. The digital control circuit turns on the first transistor upon lapse of a first time interval from the time the second MOS transistor is turned off. The digital control circuit turns on the second MOS transistor upon lapse of a second time interval from the time the first MOS transistor is turned off. The digital control circuit controls the on-period of the first MOS transistor so that the voltage applied to the load is constant in a discontinuous conduction mode. The digital control circuit determines, while the voltage applied to the load is constant, an optimal value of the first time from the duty.
摘要翻译：电子功率单元包括第一和第二MOS晶体管和数字控制电路。第一个MOS晶体管向负载施加电压。第二MOS晶体管保持导通，而第一MOS晶体管保持关断并且对负载中流动的电流进行整流。数字控制电路在从第二MOS晶体管截止时起第一时间间隔开启第一晶体管。数字控制电路在从第一MOS晶体管截止时经过第二时间间隔开启第二MOS晶体管。数字控制电路控制第一MOS晶体管的导通周期，使得施加到负载的电压在不连续导通模式下是恒定的。数字控制电路在施加到负载的电压是恒定的情况下确定第一次从占空比的最佳值。

52. 发明授权

US07026214B2 Offset-gate-type semiconductor device 失效
公开(公告)号：US07026214B2
公开(公告)日：2006-04-11
申请号：US10957692
申请日：2004-10-05
申请人： Norio Yasuhara , Syotaro Ono , Kazutoshi Nakamura , Yusuke Kawaguchi , Shinichi Hodama , Akio Nakagawa
发明人： Norio Yasuhara , Syotaro Ono , Kazutoshi Nakamura , Yusuke Kawaguchi , Shinichi Hodama , Akio Nakagawa
IPC分类号： H01L21/00
CPC分类号： H01L29/402 , H01L21/26586 , H01L29/1045 , H01L29/1079 , H01L29/1083 , H01L29/41725 , H01L29/4175 , H01L29/41758 , H01L29/41766 , H01L29/41775 , H01L29/456 , H01L29/66636 , H01L29/66659 , H01L29/78 , H01L29/7835
摘要： A semiconductor device includes a first semiconductor region having a first conductivity type, a second semiconductor region formed on the first semiconductor region and having the first conductivity type, a third semiconductor region formed in a surface of the second semiconductor region and having a second conductivity type, a fourth semiconductor region formed in the surface of the second semiconductor region and having the second conductivity type, and a gate structure formed on the second and fourth semiconductor region. The semiconductor device further includes a conductive member arranged in the trench extending from a surface of the fourth semiconductor region to the first semiconductor region, the trench having one sidewall surface flush with a sidewall surface of the gate structure.

53. 再颁专利

USRE38907E1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：USRE38907E1
公开(公告)日：2005-12-06
申请号：US10452203
申请日：2003-06-02
申请人： Tomoko Matsudai , Tsutomu Kojima , Akio Nakagawa
发明人： Tomoko Matsudai , Tsutomu Kojima , Akio Nakagawa
IPC分类号： H03K5/22 , H03K5/24 , H03K17/082 , H03K17/10 , H03K17/14
CPC分类号： H03K17/102 , H03K5/2481 , H03K17/0828 , H03K17/145
摘要： The differential amplifier of a comparator circuit includes first and second n-type MOSFETs for receiving an input signal, first and second p-type MOSFETs of a current mirror circuit, and a third n-type MOSFET of a current source circuit. The output stage includes a third p-type MOSFET for transmitting a signal, and a fourth n-type MOSFET of the current source circuit. The differential amplifier further includes fifth and sixth n-type MOSFETs respectively series-connected to the first and second n-type MOSFETs. The output stage further includes a seventh n-type MOSFET series-connected to the fourth n-type MOSFET. The gates of the fifth, sixth, and seventh n-type MOSFETs are connected to voltage bias circuits. The fifth, sixth, and seventh n-type MOSFETs suppress variations in voltage at an output node caused by poor saturation characteristics of the first, second, and fourth main n-type MOSFETs.
摘要翻译：比较器电路的差分放大器包括用于接收输入信号的第一和第二n型MOSFET，电流镜电路的第一和第二p型MOSFET以及电流源电路的第三n型MOSFET。输出级包括用于传输信号的第三p型MOSFET和电流源电路的第四n型MOSFET。差分放大器还包括分别串联连接到第一和第二n型MOSFET的第五和第六n型MOSFET。输出级还包括与第四n型MOSFET串联连接的第七n型MOSFET。第五，第六和第七n型MOSFET的栅极连接到电压偏置电路。第五，第六和第七n型MOSFET抑制由于第一，第二和第四主n型MOSFET的饱和特性不良引起的输出节点的电压变化。

54. 发明授权

US06705574B2 Cable mounting structure 失效
标题翻译：电缆安装结构
公开(公告)号：US06705574B2
公开(公告)日：2004-03-16
申请号：US10238721
申请日：2002-09-11
申请人： Akio Nakagawa , Tetsuzo Nakazawa , Takashi Sato , Takaki Tsutsui
发明人： Akio Nakagawa , Tetsuzo Nakazawa , Takashi Sato , Takaki Tsutsui
IPC分类号： F16L300
CPC分类号： H01R13/5816
摘要： In a cable mounting structure, a casing body is formed with a through hole through which a cable is inserted. A first retainer is secured to a first part of the cable and fitted with the through hole. A second retainer is attached on the casing body while holding a second part of the cable. The first retainer is an elastic member having a groove fitted with an edge of the through hole. The second retainer includes a retaining member provided on the casing body while being formed with a guide groove, and a holding member detachably fitted into the guide groove.
摘要翻译：在电缆安装结构中，壳体形成有电缆插入通孔。第一保持器固定到电缆的第一部分并且装配有通孔。在保持电缆的第二部分的同时，第二保持器附接在壳体上。第一保持器是具有与通孔的边缘配合的槽的弹性构件。第二保持器包括设置在壳体上的保持构件，同时形成有引导槽，并且保持构件可拆卸地装配到引导槽中。

55. 发明授权

US06683343B2 High voltage semiconductor device having two buffer layer 失效
标题翻译：具有两个缓冲层的高电压半导体器件
公开(公告)号：US06683343B2
公开(公告)日：2004-01-27
申请号：US10084051
申请日：2002-02-28
申请人： Tomoko Matsudai , Akio Nakagawa
发明人： Tomoko Matsudai , Akio Nakagawa
IPC分类号： H01L2976
CPC分类号： H01L29/66333 , H01L29/66348 , H01L29/7397
摘要： In an IGBT, an n buffer layer is formed under an n− high resistance layer in which a MOS gate structure is formed. An n+ buffer layer is formed between the n buffer layer and a p+ drain layer. Since the p+ drain layer is doped at a low dose, the efficiency of carrier injection can be reduced and a high-speed operation is possible without lifetime control. Since no lifetime control is performed, the on-state voltage can be low. Since the n buffer layer does not immediately stop the extension of the depletion layer during a turn-off period, oscillation of the current and voltage is prevented. The n+ buffer layer maintains a sufficient withstand voltage when a reverse bias is applied.
摘要翻译：在IGBT中，n型缓冲层形成在形成有MOS栅极结构的n +高电阻层的下方。在n缓冲层和p +漏极层之间形成n + +缓冲层。由于p +漏极层以低剂量掺杂，所以可以降低载流子注入的效率，并且可以在没有寿命的情况下进行高速操作。由于不进行寿命控制，因此导通电压可以低。由于n缓冲层在关断期间不会立即停止耗尽层的延伸，所以防止了电流和电压的振荡。当施加反向偏压时，n + +缓冲层保持足够的耐受电压。

56. 发明授权

US5780887A Conductivity modulated MOSFET 失效
公开(公告)号：US5780887A
公开(公告)日：1998-07-14
申请号：US261254
申请日：1994-06-14
申请人： Akio Nakagawa , Hiromichi Ohashi , Yoshihiro Yamaguchi , Kiminori Watanabe , Thuneo Thukakoshi
发明人： Akio Nakagawa , Hiromichi Ohashi , Yoshihiro Yamaguchi , Kiminori Watanabe , Thuneo Thukakoshi
IPC分类号： H01L29/06 , H01L29/10 , H01L29/739 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L29/1095 , H01L29/0619 , H01L29/0696 , H01L29/7393 , H01L29/7395
摘要： A conductivity modulated MOSFET, having a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type formed on the semiconductor substrate and having a high resistance, a base layer of the first conductivity type formed in the semiconductor layer, a source layer of the second conductivity type formed in the base layer, a gate electrode formed on a gate insulating film which is formed on a channel region, the channel region being formed in a surface of the base layer between the semiconductor layer and the source layer, a source electrode ohmic-contacting the source layer and the base layer, and a drain electrode formed on the surface of the semiconductor substrate opposite to the semiconductor layer, characterized in that the conductivity modulated MOSFET has a saturation current smaller than a latch-up current when a predetermined gate voltage is applied to the gate electrode.

57. 发明授权

US5689121A Insulated-gate semiconductor device 失效
标题翻译：绝缘栅半导体器件
公开(公告)号：US5689121A
公开(公告)日：1997-11-18
申请号：US480389
申请日：1995-06-07
申请人： Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa , Norio Yasuhara , Tomoki Inoue
发明人： Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa , Norio Yasuhara , Tomoki Inoue
IPC分类号： H01L29/06 , H01L29/423 , H01L29/739 , H01L29/745 , H01L29/74 , H01L31/111
CPC分类号： H01L29/7455 , H01L29/7394 , H01L29/7397 , H01L29/7398 , H01L29/0696 , H01L29/4236
摘要： An insulated-gate semiconductor device comprises a P type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.
摘要翻译：绝缘栅半导体器件包括P型发射极层，形成在P型发射极层上的N-高电阻基极层和与N型高电阻基极层接触的P型基极层。形成从P型基底层到达N个高电阻基底层的深度的多个沟槽。覆盖有栅极绝缘膜的栅电极被埋在每个沟槽中。在一些沟槽之间的沟道区域中，在P型基极层的表面形成有与阴极连接的N型源极层，从而形成用于导通工作的N沟道MOS晶体管。连接到P基极层的P沟道MOS晶体管形成在其它沟槽之间的沟道区域中，以便在关断操作时将器件的孔排出。

58. 发明授权

US5536961A High breakdown voltage semiconductor device 失效
公开(公告)号：US5536961A
公开(公告)日：1996-07-16
申请号：US396794
申请日：1995-03-01
申请人： Akio Nakagawa , Norio Yasuhara , Tomoko Matsudai
发明人： Akio Nakagawa , Norio Yasuhara , Tomoko Matsudai
IPC分类号： H01L21/336 , H01L21/74 , H01L21/762 , H01L27/06 , H01L27/092 , H01L27/12 , H01L29/06 , H01L29/40 , H01L29/739 , H01L29/74 , H01L29/745 , H01L29/749 , H01L29/78 , H01L29/786 , H01L29/861 , H01L29/76
CPC分类号： H01L29/404 , H01L21/74 , H01L21/76264 , H01L21/76297 , H01L27/0623 , H01L27/0922 , H01L27/1203 , H01L29/402 , H01L29/405 , H01L29/407 , H01L29/408 , H01L29/66772 , H01L29/7394 , H01L29/7436 , H01L29/7455 , H01L29/749 , H01L29/7824 , H01L29/7835 , H01L29/78624 , H01L29/8611 , H01L21/76275 , H01L21/76286
摘要： A high breakdown voltage semiconductor device comprising a semiconductor substrate an insulating layer formed on the semiconductor substrate, a high resistance semiconductor layer formed on the insulating layer, an isolation region formed in the high resistance semiconductor layer, an element region formed in the high resistance semiconductor layer isolated by the isolation region in a lateral direction, a first low resistance region of a first conductivity type formed in a central surface portion of the element region, and a second low resistance region of a second conductivity type formed in a peripheral surface portion of the element region. Dose of impurities in the element region is set such that a portion of the element region between the first low resistance region and the second low resistance region is completely depleted when voltage is applied between the first and second low resistance regions.

59. 发明授权

US5477065A Lateral thin film thyristor with bevel 失效
标题翻译：横向薄膜晶闸管与斜面
公开(公告)号：US5477065A
公开(公告)日：1995-12-19
申请号：US191132
申请日：1994-01-24
申请人： Akio Nakagawa , Tsuneo Ogura
发明人： Akio Nakagawa , Tsuneo Ogura
IPC分类号： H01L21/8234 , H01L21/98 , H01L23/433 , H01L23/538 , H01L25/065 , H01L25/07 , H01L25/16 , H01L25/18 , H01L27/00 , H01L27/01 , H01L27/082 , H01L27/088 , H01L27/12 , H01L27/15 , H01L29/73 , H01L29/739 , H01L29/74 , H01L29/78 , H01L29/786 , H01L31/12 , H01L29/749
CPC分类号： H01L29/7317 , H01L23/4334 , H01L23/5389 , H01L24/24 , H01L24/25 , H01L24/73 , H01L24/82 , H01L25/16 , H01L25/18 , H01L25/50 , H01L27/082 , H01L27/1203 , H01L29/7436 , H01L2224/05567 , H01L2224/05568 , H01L2224/05573 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/24051 , H01L2224/24137 , H01L2224/24147 , H01L2224/24225 , H01L2224/24226 , H01L2224/24227 , H01L2224/48463 , H01L2224/73227 , H01L24/48 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01033 , H01L2924/01046 , H01L2924/014 , H01L2924/10253 , H01L2924/12036 , H01L2924/12041 , H01L2924/12043 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/18161 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107
摘要： A composite integrated circuit device includes a semiconductor element chip, a positioning guide formed on the semiconductor element chip, and an electronic element set in a preset position on the semiconductor element chip in a self-alignment manner by means of the positioning guide and mounted thereon. Also disclosed is are lateral, thin film devices with tapered shapes to reduce breakdown.
摘要翻译：复合集成电路器件包括半导体元件芯片，形成在半导体元件芯片上的定位引导件和通过定位引导件以自对准方式设置在半导体元件芯片上的预设位置的电子元件并安装在其上。还公开了具有锥形形状以减少击穿的横向薄膜装置。

60. 发明授权

US5463231A Method of operating thyristor with insulated gates 失效
公开(公告)号：US5463231A
公开(公告)日：1995-10-31
申请号：US353385
申请日：1994-12-02
申请人： Tsuneo Ogura , Kiminori Watanabe , Akio Nakagawa , Yoshihiro Yamaguchi , Norio Yasuhara , Tomoko Matsudai , Shigeru Hasegawa , Kazuya Nakayama
发明人： Tsuneo Ogura , Kiminori Watanabe , Akio Nakagawa , Yoshihiro Yamaguchi , Norio Yasuhara , Tomoko Matsudai , Shigeru Hasegawa , Kazuya Nakayama
IPC分类号： H01L27/06 , H01L29/74 , H01L29/745 , H01L29/749 , H01L31/111
CPC分类号： H01L27/0617 , H01L29/7436 , H01L29/7455 , H01L29/749
摘要： A thyristor with insulated gates includes turn-off and turn-on MOSFETs. The turn-on MOSFET has a turn-on gate employing a p-type base as a channel and extending over an n-type base and an n-type emitter. The turn-off MOSFET has n-type drain and source layers formed in a p-type base layer, and a turn-off gate extending over the drain and source layers. The n-type drain layer is short-circuited with the p-type base layer via a drain electrode. The drain electrode is formed near an n-type emitter layer. When the thyristor is to be turned off, the first voltage is applied to the turn-on gate, and the second voltage is applied to the turn-off gate while the first voltage is applied to the turn-on gate. After the application of the second voltage continues for a predetermined period of time, the application of the first voltage to the turn-on gate is stopped. With this operation, the thyristor can be turned off even with a large current.

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