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51. 发明授权

US5834342A Self-aligned silicidation of TFT source-drain region 失效
标题翻译： TFT源极 - 漏极区域的自对准硅化物
公开(公告)号：US5834342A
公开(公告)日：1998-11-10
申请号：US884917
申请日：1997-06-30
申请人： Kan-Yuan Lee , Shou-Gwo Wuu , Dun-Nian Yang
发明人： Kan-Yuan Lee , Shou-Gwo Wuu , Dun-Nian Yang
IPC分类号： H01L21/336 , H01L21/8244 , H01L29/417 , H01L29/786 , H01L21/265
CPC分类号： H01L29/66765 , H01L27/11 , H01L29/41733 , H01L29/78624
摘要： A process for manufacturing a thin film transistor for use in a CMOS SRAM circuit is described. A key feature is the formation of two different photoresist masks from the same optical mask. The first photoresist mask is generated using a normal amount of actinic radiation during exposure and is used to protect the gate region during source and drain formation through ion implantation. The second photoresist mask is aligned relative to the gate in exactly the same orientation as the first mask but is given a reduced exposure of actinic radiation. This results, after development, in a slightly larger mask which is used during etching to form the oxide cap that will protect the channel area during the subsequent silicidation step. Making the cap slightly wider than the channel ensures that small lengths of the source and the drain regions that abut the channel are not converted to silicide. Thus, the finished device continues to act as a thin film transistor, but has greatly reduced source and drain resistances.
摘要翻译：描述用于制造用于CMOS SRAM电路的薄膜晶体管的工艺。一个关键特征是从相同的光学掩模形成两种不同的光刻胶掩模。在曝光期间使用正常量的光化辐射产生第一光致抗蚀剂掩模，并且用于通过离子注入在源极和漏极形成期间保护栅极区域。第二光致抗蚀剂掩模相对于栅极以与第一掩模完全相同的取向对准，但被给予光化辐射的减少的曝光。这在显影之后产生了在蚀刻期间用于形成氧化物盖的稍大的掩模，其将在随后的硅化步骤期间保护沟道区域。使帽子比通道略宽，确保抵靠通道的源极和漏极区域的较小长度不会转化为硅化物。因此，成品器件继续作为薄膜晶体管，但是极大地降低了源极和漏极电阻。

52. 发明授权

US5731232A Method for concurrently making thin-film-transistor (TFT) gate electrodes and ohmic contacts at P/N junctions for TFT-static random 失效
标题翻译：同时制造薄膜晶体管（TFT）栅电极和欧姆接触的P / N结用于TFT-静态随机的方法
公开(公告)号：US5731232A
公开(公告)日：1998-03-24
申请号：US745639
申请日：1996-11-08
申请人： Shou-Gwo Wuu , Mong-Song Liang
发明人： Shou-Gwo Wuu , Mong-Song Liang
IPC分类号： H01L21/84 , H01L21/00
CPC分类号： H01L21/84 , Y10S257/903
摘要： A method is achieved for making TFT-load static random access memory (SRAM) cells where the thin film transistor (TFT) gate electrodes are made from an electrical conductor. At the same time, portions of the conductor between P and N doped polysilicon interconnections eliminate the P/N junction. Ohmic contacts are formed while avoiding additional processing steps. N-channel FET gate electrodes are formed from an N.sup.+ doped first polysilicon layer having a first insulating layer thereon. Second polySi interconnections are formed with a second insulating layer thereon. First contact openings are etched in the first and second insulating layers to the N.sup.+ doped FET gate electrodes, and a patterned conductor (TiN, TiSi.sub.2) forms the P-channel TFT gate electrodes and concurrently forms portions over and in the first contact openings. A TFT gate oxide is formed and second contact openings are etched over the first contact openings to the conductor. An N.sup.- doped third polySi layer is deposited, selectively doped P.sup.+ and patterned to form the TFT N.sup.- doped channel, the P.sup.+ doped source/drains, and the interconnection in the contact openings to the N-FET gate electrodes. The conductor at the interface between the P/N polySi forms essentially ohmic contacts, thereby eliminating the P/N junction and improving circuit performance.
摘要翻译：实现了薄膜晶体管（TFT）栅电极由电导体制成的TFT负载静态随机存取存储器（SRAM）单元的方法。同时，P和N掺杂多晶硅互连之间的导体部分消除了P / N结。在避免额外的处理步骤的同时形成欧姆接触。 N沟道FET栅极由其上具有第一绝缘层的N +掺杂的第一多晶硅层形成。第二多晶硅互连在其上形成有第二绝缘层。第一接触开口在第一和第二绝缘层中蚀刻到N +掺杂FET栅电极，并且图案化导体（TiN，TiSi 2）形成P沟道TFT栅电极，同时在第一接触开口上并在其中形成部分。形成TFT栅极氧化物，并且第二接触开口在第一接触开口上蚀刻到导体。沉积N-掺杂的第三多晶硅层，选择性掺杂P +并图案化以形成TFT N掺杂沟道，P +掺杂源极/漏极以及在N-FET栅电极的接触开口中的互连。在P / N多晶硅之间的界面处的导体形成基本的欧姆接触，从而消除P / N结并提高电路性能。

53. 发明授权

US5607879A Method for forming buried plug contacts on semiconductor integrated circuits 失效
公开(公告)号：US5607879A
公开(公告)日：1997-03-04
申请号：US496019
申请日：1995-06-28
申请人： Shou-Gwo Wuu , Chen-Jong Wang , Mong-Song Liang , Chung-Hui Su
发明人： Shou-Gwo Wuu , Chen-Jong Wang , Mong-Song Liang , Chung-Hui Su
IPC分类号： H01L21/311 , H01L21/60 , H01L21/768 , H01L23/485 , H01L21/28
CPC分类号： H01L21/76897 , H01L21/31116 , H01L21/76801 , H01L23/485 , H01L2924/0002
摘要： A method for fabricating buried metal plug structures for multi-polysilicon layer interconnects and for concurrently making metal plugs on semiconductor integrated circuits, such as DRAM and SRAM, was achieved. The method involved forming contact opening in an insulating layer over opening in a patterned polysilicon layer. The opening in the polysilicon layer aligned over source/drain contact areas on the substrate and providing a means for forming self-aligned contact openings. Buried metal plugs in the contact openings form interconnects between the polysilicon layer and the source/drains. And, by merging the process steps, concurrently forming metal plug interconnects for contacts to semiconductor devices and first level metal. The process is applicable to the formation of bit line contacts on DRAM and SRAM circuits and simultaneously form the peripheral contact on the chip.

54. 发明授权

US5587696A High resistance polysilicon resistor for integrated circuits and method of fabrication thereof 失效
标题翻译：用于集成电路的高电阻多晶硅电阻器及其制造方法
公开(公告)号：US5587696A
公开(公告)日：1996-12-24
申请号：US496018
申请日：1995-06-28
申请人： Chung-Hui Su , Mong-Song Liang , Shou-Gwo Wuu , Chen-Jong Wang
发明人： Chung-Hui Su , Mong-Song Liang , Shou-Gwo Wuu , Chen-Jong Wang
IPC分类号： H01L21/02 , H01C1/012
CPC分类号： H01L28/20 , Y10T29/49082
摘要： A multi-layer polysilicon resistor and a method by which the multi-layer polysilicon resistor is formed. A minimum of two polysilicon layers is formed upon an insulating layer, the insulating layer in turn being formed upon a semiconductor substrate. The first polysilicon layer is formed to a first thickness at a first deposition temperature. The second polysilicon layer is formed directly upon the first polysilicon layer. The second polysilicon layer is formed to a second thickness at a second deposition temperature. The two deposition temperatures are in the range of about 450 degrees centigrade to about 620 degrees centigrade, and the difference in temperature between the first deposition temperature and the second deposition temperature is a minimum of 10 degrees centigrade.
摘要翻译：多层多晶硅电阻器和形成多层多晶硅电阻器的方法。在绝缘层上形成至少两个多晶硅层，绝缘层依次形成在半导体衬底上。第一多晶硅层在第一沉积温度下形成第一厚度。第二多晶硅层直接形成在第一多晶硅层上。第二多晶硅层在第二沉积温度下形成第二厚度。两个沉积温度在约450摄氏度至约620摄氏度的范围内，并且第一沉积温度和第二沉积温度之间的温度差最小为10摄氏度。

55. 发明授权

US09257463B2 Self-aligned implantation process for forming junction isolation regions 有权
标题翻译：用于形成结隔离区域的自对准注入工艺
公开(公告)号：US09257463B2
公开(公告)日：2016-02-09
申请号：US13588879
申请日：2012-08-17
申请人： Chien-Hsien Tseng , Shou-Gwo Wuu , Chia-Chan Chen , Kuo-Yu Wu , Dao-Hong Yang , Ming-Hao Chung
发明人： Chien-Hsien Tseng , Shou-Gwo Wuu , Chia-Chan Chen , Kuo-Yu Wu , Dao-Hong Yang , Ming-Hao Chung
IPC分类号： H01L21/336 , H01L27/146
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/1461 , H01L27/14612 , H01L27/1463
摘要： A device includes a semiconductor substrate, a well region in the semiconductor substrate, and a Metal-Oxide-Semiconductor (MOS) device. The MOS device includes a gate dielectric overlapping the well region, a gate electrode over the gate dielectric, and a source/drain region in the well region. The source/drain region and the well region are of opposite conductivity types. An edge of the first source drain region facing away from the gate electrode is in contact with the well region to form a junction isolation.
摘要翻译：一种器件包括半导体衬底，半导体衬底中的阱区和金属氧化物半导体（MOS）器件。 MOS器件包括与阱区重叠的栅极电介质，栅极电介质上的栅电极和阱区中的源极/漏极区。源/漏区和阱区具有相反的导电类型。第一源漏区域背离栅电极的边缘与阱区域接触以形成结隔离。

56. 发明授权

US08669133B2 Crosstalk improvement through P on N structure for image sensor 有权
标题翻译：通过P on N结构对图像传感器进行串扰改善
公开(公告)号：US08669133B2
公开(公告)日：2014-03-11
申请号：US12780625
申请日：2010-05-14
申请人： Chung-Wei Chang , Han-Chi Liu , Chun-Yao Ko , Shou-Gwo Wuu
发明人： Chung-Wei Chang , Han-Chi Liu , Chun-Yao Ko , Shou-Gwo Wuu
IPC分类号： H01L21/00
CPC分类号： H01L27/1463 , H01L21/761 , H01L27/14603 , H01L27/14609 , H01L27/14621 , H01L27/14627 , H01L27/14643 , H01L27/14689 , H01L31/035272
摘要： The present disclosure provides an image sensor semiconductor device. The semiconductor device includes a semiconductor substrate having a first type of dopant; a semiconductor layer having a second type of dopant different from the first type of dopant and disposed on the semiconductor substrate; and an image sensor formed in the semiconductor layer.
摘要翻译：本公开提供了一种图像传感器半导体器件。半导体器件包括具有第一类掺杂剂的半导体衬底; 半导体层，其具有不同于所述第一类型掺杂剂的第二类型的掺杂剂并且设置在所述半导体衬底上; 以及形成在半导体层中的图像传感器。

57. 发明申请

US20130320418A1 Self-Aligned Implantation Process for Forming Junction Isolation Regions 有权
标题翻译：用于形成接合隔离区域的自对准植入过程
公开(公告)号：US20130320418A1
公开(公告)日：2013-12-05
申请号：US13588879
申请日：2012-08-17
申请人： Chien-Hsien Tseng , Shou-Gwo Wuu , Chia-Chan Chen , Kuo-Yu Wu , Dao-Hong Yang , Ming-Hao Chung
发明人： Chien-Hsien Tseng , Shou-Gwo Wuu , Chia-Chan Chen , Kuo-Yu Wu , Dao-Hong Yang , Ming-Hao Chung
IPC分类号： H01L31/113 , H01L21/336
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/1461 , H01L27/14612 , H01L27/1463
摘要： A device includes a semiconductor substrate, a well region in the semiconductor substrate, and a Metal-Oxide-Semiconductor (MOS) device. The MOS device includes a gate dielectric overlapping the well region, a gate electrode over the gate dielectric, and a source/drain region in the well region. The source/drain region and the well region are of opposite conductivity types. An edge of the first source drain region facing away from the gate electrode is in contact with the well region to form a junction isolation.
摘要翻译：一种器件包括半导体衬底，半导体衬底中的阱区和金属氧化物半导体（MOS）器件。 MOS器件包括与阱区重叠的栅极电介质，栅极电介质上的栅电极和阱区中的源极/漏极区。源/漏区和阱区具有相反的导电类型。第一源漏区域背离栅电极的边缘与阱区域接触以形成结隔离。

58. 发明申请

US20130320397A1 Fully Isolated LIGBT and Methods for Forming the Same 有权
公开(公告)号：US20130320397A1
公开(公告)日：2013-12-05
申请号：US13601229
申请日：2012-08-31
申请人： Jhy-Jyi Sze , Biay-Cheng Hseih , Shou-Gwo Wuu
发明人： Jhy-Jyi Sze , Biay-Cheng Hseih , Shou-Gwo Wuu
IPC分类号： H01L29/739 , H01L21/332
CPC分类号： H01L29/66325 , H01L21/265 , H01L21/304 , H01L21/76 , H01L21/761 , H01L21/76224 , H01L29/0696 , H01L29/7393 , H01L29/7394
摘要： A device includes a dielectric layer, and a heavily doped semiconductor layer over the dielectric layer. The heavily doped semiconductor layer is of a first conductivity type. A semiconductor region is over the heavily doped semiconductor layer, wherein the semiconductor region is of a second conductivity type opposite the first conductivity type. A Lateral Insulated Gate Bipolar Transistor (LIGBT) is disposed at a surface of the semiconductor region.

59. 发明授权

US08546860B2 Stress engineering to reduce dark current of CMOS image sensors 有权
标题翻译：应力工程可以减少CMOS图像传感器的暗电流
公开(公告)号：US08546860B2
公开(公告)日：2013-10-01
申请号：US13494769
申请日：2012-06-12
申请人： Ru-Shang Hsiao , Nai-Wen Cheng , Chung-Te Lin , Chien-Hsien Tseng , Shou-Gwo Wuu
发明人： Ru-Shang Hsiao , Nai-Wen Cheng , Chung-Te Lin , Chien-Hsien Tseng , Shou-Gwo Wuu
IPC分类号： H01L31/113 , H01L31/173
CPC分类号： H01L27/1463 , H01L21/324 , H01L21/823878 , H01L22/34 , H01L27/14689 , H01L29/7842
摘要： This disclosure relates to an active pixel cell including a shallow trench isolation (STI) structure. The active pixel cell further includes a photodiode neighboring the STI structure, where a first stress resulted from substrate processing prior to deposition of a pre-metal dielectric layer increases dark current and white cell counts of a photodiode of the active pixel cell. The active pixel cell further includes a transistor, where the transistor controls the operation of the active pixel cell. The active pixel cell further includes a stress layer over the photodiode, the STI structure, and the transistor, and the stress layer has a second stress that counters the first stress exerted on the substrate, and the second stress reduces the dark current and the white cell counts caused by the first stress.
摘要翻译：本公开涉及包括浅沟槽隔离（STI）结构的有源像素单元。有源像素单元还包括与STI结构相邻的光电二极管，其中在沉积预金属介电层之前由衬底处理产生的第一应力增加了有源像素单元的光电二极管的暗电流和白细胞计数。有源像素单元还包括晶体管，其中晶体管控制有源像素单元的操作。有源像素单元还包括光电二极管上的应力层，STI结构和晶体管，并且应力层具有对施加在衬底上的第一应力进行反映的第二应力，并且第二应力减小暗电流和白色细胞计数由第一次压力引起。

60. 发明授权

US08383440B2 Light shield for CMOS imager 有权
标题翻译： CMOS成像器的屏蔽
公开(公告)号：US08383440B2
公开(公告)日：2013-02-26
申请号：US13081120
申请日：2011-04-06
申请人： Wen-De Wang , Dun-Nian Yaung , Shou-Gwo Wuu , Chung-Yi Yu
发明人： Wen-De Wang , Dun-Nian Yaung , Shou-Gwo Wuu , Chung-Yi Yu
IPC分类号： H01L21/00
CPC分类号： H01L27/14654 , H01L27/14623 , H01L27/14636 , H01L2924/0002 , H01L2924/00
摘要： System and method for providing a light shield for a CMOS imager is provided. The light shield comprises a structure formed above a point between a photo-sensitive element and adjacent circuitry. The structure is formed of a light-blocking material, such as a metal, metal alloy, metal compound, or the like, formed in dielectric layers over the photo-sensitive elements.
摘要翻译：提供了一种用于为CMOS成像器提供遮光罩的系统和方法。光屏蔽包括形成在感光元件和相邻电路之间的点之上的结构。该结构由光敏元件上的电介质层中形成的诸如金属，金属合金，金属化合物等的遮光材料形成。

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