专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明授权

US5999355A Gain and phase constrained adaptive equalizing filter in a sampled amplitude read channel for magnetic recording 失效
标题翻译：用于磁记录的采样振幅读通道中的增益和相位约束自适应均衡滤波器
公开(公告)号：US5999355A
公开(公告)日：1999-12-07
申请号：US640410
申请日：1996-04-30
申请人： Richard T. Behrens , William G. Bliss , Li Du , Mark S. Spurbeck , German S. Feyh , Trent O. Dudley
发明人： Richard T. Behrens , William G. Bliss , Li Du , Mark S. Spurbeck , German S. Feyh , Trent O. Dudley
IPC分类号： G11B5/012 , G11B5/035 , G11B5/09 , G11B20/10 , G11B20/14 , G11B20/18 , H03H15/00 , H03H17/02 , H03H17/06 , H04L7/00 , H04L7/02 , H04L25/03
CPC分类号： G11B20/10055 , G11B20/10009 , G11B20/10037 , G11B20/1403 , G11B5/09 , G11B5/012 , G11B5/035 , H04L7/0029 , H04L7/0062
摘要： A sampled amplitude read channel for magnetic disk recording which asynchronously samples the analog read signal, adaptively equalizes the resulting discrete time sample values according to a target partial response, extracts synchronous sample values through interpolated timing recovery, and detects digital data from the synchronous sample values using a Viterbi sequence detector is disclosed. To minimize interference from the timing and gain control loops, the phase and magnitude response of the adaptive equalizer filter are constrained at a predetermined frequency using an optimal orthogonal projection operation as a modification to a least mean square (LMS) adaptation algorithm. Further, with interpolated timing recovery, the equalizer filter and its associated latency are removed from the timing recovery loop, thereby allowing a higher order discrete time filter and a lower order analog filter.
摘要翻译：用于磁盘记录的采样幅度读取通道，其异步采样模拟读取信号，根据目标部分响应对所得离散时间采样值进行自适应均衡，通过内插定时恢复提取同步采样值，并从同步采样值检测数字数据公开了使用维特比序列检测器。为了最小化来自定时和增益控制环路的干扰，使用最佳正交投影操作将自适应均衡器滤波器的相位和幅度响应约束在预定频率，作为对最小均方（LMS）适配算法的修改。此外，通过内插定时恢复，均衡器滤波器及其相关等待时间从定时恢复环路中移除，从而允许较高阶离散时间滤波器和较低阶模拟滤波器。

72. 发明授权

US5844911A Disc storage system with spare sectors dispersed at a regular interval around a data track to reduced access latency 失效
标题翻译：具有备用扇区的盘存储系统以规则的间隔围绕数据轨道分散以减少访问延迟
公开(公告)号：US5844911A
公开(公告)日：1998-12-01
申请号：US761993
申请日：1996-12-12
申请人： John Schadegg , Neal Glover , Laura Droege Shellhamer , William L. Witt , Richard T. Behrens
发明人： John Schadegg , Neal Glover , Laura Droege Shellhamer , William L. Witt , Richard T. Behrens
IPC分类号： G11B7/007 , G11B20/18 , G01R31/28 , G11B7/00
CPC分类号： G11B20/1883 , G11B2220/20 , G11B7/007
摘要： A defect management system is disclosed for disc storage systems which avoids the access latency associated with conventional linear replacement techniques by dispersing spare segments throughout each track at a regular interval and buffering sectors inbetween a defective sector and the corresponding spare segment during read and write operations. In one embodiment, a spare segment is an entire sector which replaces a defective data sector; and in an alternative embodiment, a spare segment stores only the defective portion of a data sector which is more efficient, but also more complicated in implementation. In both embodiments, the defect management system comprises a defect locator for locating a defective segment within a data sector. Once located, the defect management system maps the defective sector (or the defective portion thereof) to the nearest available spare segment. Then when accessing the track that comprises the defective sector, the data sectors between the defective segment and corresponding spare segment are buffered in a data buffer, and an area in the data buffer is reserved for storing the data associated with the spare segment. In this manner, data can be written to and read from the track in a contiguous sequence without requiring an extra revolution of latency as in the conventional linear replacement defect mapping techniques.
摘要翻译：公开了一种用于盘存储系统的缺陷管理系统，其避免了与常规线性替换技术相关联的访问延迟，通过以常规间隔分散每个磁道上的备用段，并在读写操作期间缓冲缺陷扇区与相应备用段之间的扇区。在一个实施例中，备用段是替换有缺陷的数据扇区的整个扇区; 并且在替代实施例中，备用段仅存储更有效的数据扇区的缺陷部分，而且在实现中更复杂。在两个实施例中，缺陷管理系统包括用于定位数据扇区内的缺陷段的缺陷定位器。一旦定位，缺陷管理系统将缺陷扇区（或其缺陷部分）映射到最近的可用备用段。然后，当访问包括缺陷扇区的轨迹时，将缺陷段与相应的备用段之间的数据扇区缓冲在数据缓冲器中，并且数据缓冲区中的区域被保留用于存储与备用段相关联的数据。以这种方式，可以以连续的顺序将数据写入轨道并从轨道读取数据，而不需要象传统的线性替换缺陷映射技术那样的等待时间的额外旋转。

73. 发明授权

US5796535A Sampled amplitude read channel employing a user data frequency synthesizer and a servo data frequency synthesizer 失效
标题翻译：采用用户数据频率合成器和伺服数据频率合成器的采样幅度读取通道
公开(公告)号：US5796535A
公开(公告)日：1998-08-18
申请号：US440515
申请日：1995-05-12
申请人： Tyson Tuttle , Diwakar Vishakhadatta , Jerrel P. Hein , David R. Welland , David E. Reed , Richard T. Behrens , William G. Bliss , Paul M. Romano , Trent O. Dudley , Christopher P. Zook
发明人： Tyson Tuttle , Diwakar Vishakhadatta , Jerrel P. Hein , David R. Welland , David E. Reed , Richard T. Behrens , William G. Bliss , Paul M. Romano , Trent O. Dudley , Christopher P. Zook
IPC分类号： G11B5/012 , G11B5/09 , G11B5/55 , G11B5/58 , G11B5/596 , G11B19/28 , G11B20/10 , G11B20/12 , G11B20/14
CPC分类号： G11B20/10055 , G11B19/28 , G11B20/10009 , G11B20/10037 , G11B20/1403 , G11B5/012 , G11B5/09 , G11B5/5526 , G11B5/553 , G11B5/5547 , G11B5/58 , G11B5/59605 , G11B5/59622 , G11B5/59633 , G11B5/59688 , G11B20/1258 , G11B5/5534 , G11B5/5965
摘要： A sampled amplitude read channel incorporated within a magnetic disk storage system for reading data recorded in concentric tracks on a magnetic medium, where the data comprises user data sectors recorded at varying data rates across a plurality of predefined zones and embedded servo data sectors recorded at the same data rate across the zones. The sampled amplitude read channel comprises a timing recovery component for synchronous sampling of a read signal from a magnetic read head positioned over the magnetic medium, a gain control component for adjusting the amplitude of the read signal, and a DC offset component for cancelling a DC offset in the read signal. These components are dynamically configured to operate according to whether the read channel is processing user data or embedded servo data. A user data frequency synthesizer and a servo data frequency synthesizer lock the timing recovery component to a reference frequency and provide a coarse center frequency control signal corresponding to the user data or servo data mode. The read channel further employs pipelined reads to reduce the physical gap between sectors on the medium. In addition, an improved sync mark detector and an improved asynchronous servo address mark detector increase the accuracy and reliability of the read channel.
摘要翻译：一个结合在磁盘存储系统内的采样幅度读取通道，用于读取记录在磁介质上的同心磁道中的数据，其中数据包括以多个预定义区域中记录的不同数据速率记录的用户数据扇区，以及记录在相同的数据速率跨区域。采样振幅读通道包括定时恢复组件，用于对位于磁介质上的磁读头进行读信号的同步采样，用于调整读信号振幅的增益控制部件和用于消除DC的直流偏移分量在读信号中偏移。这些组件被动态配置为根据读通道是处理用户数据还是嵌入式伺服数据进行操作。用户数据频率合成器和伺服数据频率合成器将定时恢复组件锁定到参考频率，并提供对应于用户数据或伺服数据模式的粗略的中心频率控制信号。读通道还采用流水线读取来减少介质上扇区之间的物理差距。此外，改进的同步标记检测器和改进的异步伺服地址标记检测器增加读取通道的精度和可靠性。

74. 发明授权

US5754352A Synchronous read channel employing an expected sample value generator for acquiring a preamble 失效
标题翻译：采用预期采样值发生器的同步读通道用于获取前导码
公开(公告)号：US5754352A
公开(公告)日：1998-05-19
申请号：US701572
申请日：1996-08-22
申请人： Richard T. Behrens , Trent Dudley , William G. Bliss
发明人： Richard T. Behrens , Trent Dudley , William G. Bliss
IPC分类号： G11B20/10 , G11B20/14 , H03L7/085 , H03L7/091 , H04L7/02 , H04L7/033 , H04L7/10 , G11B5/09
CPC分类号： H04L7/0062 , G11B20/10009 , G11B20/10055 , G11B20/1403 , H03L7/085 , H03L7/091 , H04L7/0334 , H04L7/10
摘要： An improved timing recovery phase-locked loop in a partial response recording channel comprising a means for generating a frequency error and a means for generating a phase error represented by a timing gradient. The frequency error is not affected by a DC offset in the input reference signal and is less susciptible to noise due to an increase in sensitivity. A state machine for generating expected samples is used to generate the timing gradient, rather than estimated signal samples, which results in a shorter acquisition preamble. When tracking arbitrary user data, the timing gradient is smoothed to reduce variations in the gain of the loop.
摘要翻译：部分响应记录通道中的改进的定时恢复锁相环，包括用于产生频率误差的装置和用于产生由定时梯度表示的相位误差的装置。频率误差不受输入参考信号中的直流偏移影响，并且由于灵敏度的增加而对噪声不太敏感。用于产生预期样本的状态机用于产生定时梯度，而不是估计的信号样本，这导致较短的采集前导码。当跟踪任意用户数据时，平滑定时梯度以减少环路增益的变化。

75. 发明授权

US5329554A Digital pulse detector 失效
标题翻译：数字脉冲检测器
公开(公告)号：US5329554A
公开(公告)日：1994-07-12
申请号：US879938
申请日：1992-05-08
申请人： Richard T. Behrens , Trent Dudley , Neal Glover
发明人： Richard T. Behrens , Trent Dudley , Neal Glover
IPC分类号： G11B20/10 , G11B20/14 , H03K5/1532 , H03K5/19 , H04L25/08 , H04L27/00 , H04L27/06
CPC分类号： G11B20/10037 , G11B20/10009 , G11B20/1403 , H03K5/19
摘要： Disclosed is a pulse detector that uses four samples of an analog signal to detect a pulse as soon as one sample beyond the time of the peak of the signal level at the pulse. The pulse detector can detect pulses by sampling at the center of a peak of the pulse or by sampling at either side of the peak of the pulse. The pulse detector detects pulses while tracking data, and it uses an alternate detection system for detecting pulses while acquiring timing and gain lock on a signal having a known data pattern. The detector uses either the sampled signal levels directly, or a moving average of two samples to perform the detection.
摘要翻译：公开了一种使用四个模拟信号样本的脉冲检测器，一旦超过脉冲信号电平峰值时间的一个采样就检测脉冲。脉冲检测器可以通过在脉冲峰值的中心采样或通过在脉冲峰值的任一侧进行采样来检测脉冲。脉冲检测器在跟踪数据的同时检测脉冲，并且在采集具有已知数据模式的信号的定时和增益锁定的同时使用用于检测脉冲的替代检测系统。检测器使用采样信号电平或两个采样的移动平均值进行检测。

76. 发明授权

US5291499A Method and apparatus for reduced-complexity viterbi-type sequence detectors 失效
标题翻译：复杂度维特比型序列检测器的方法和装置
公开(公告)号：US5291499A
公开(公告)日：1994-03-01
申请号：US852015
申请日：1992-03-16
申请人： Richard T. Behrens , Kent D. Anderson , Neal Glover
发明人： Richard T. Behrens , Kent D. Anderson , Neal Glover
IPC分类号： G06F11/30 , G06F11/10 , G11B20/14 , G11B20/18 , H03H15/00 , H03H17/00 , H03H21/00 , H03M7/14 , H03M13/23 , H03M13/41 , H04B3/04 , H04L25/08 , H04L25/49 , H04L25/497 , H04L27/00 , G06F11/00
CPC分类号： G11B20/1426 , G11B20/1833 , H03M13/41 , H03M13/4107 , H04L25/4906 , H04L25/497
摘要： A Viterbi detector is modified to reduce its implementation complexity. A partial-response signal may be viewed as a sequence of expected samples generated from a finite-state-machine model. In a typical Viterbi demodulator implemented using the add, compare, select (ACS) method, each state in the expected sample sequence model is associated with a hardware module to perform the functions of adding new branch error metrics to path error metrics, comparing path error metrics, and selecting the path having the lowest path error metric. In this invention, an ACS module may have two or more sequence-model states dynamically associated with it, such that at some times one sequence-model state is associated with it and at other times another sequence-model state is associated with it. This reduces the number of ACS modules required and also reduces the size/complexity of the demodulator's path memories which must store one path for each ACS module. Groups of sequence-model states may be chosen to share an ACS module without significant loss in performance as compared to the original, unreduced Viterbi demodulator. The invention supports a wide range of sample models by making the expected sample sequence of an isolated medium transition programmable. The invention reduces the speed at which the detector circuitry must operate relative to the sample rate by allowing multiple samples to be processed simultaneously. Several reduced detectors for specific sample sequence models are presented for particular applications. The invention is applicable to other types of Viterbi detectors, such as decoders for convolutional codes.
摘要翻译：修改维特比检测器以减少其实现复杂度。部分响应信号可以被视为从有限状态机模型生成的预期样本的序列。在使用加法，比较，选择（ACS）方法实现的典型维特比解调器中，预期采样序列模型中的每个状态与硬件模块相关联，以执行向路径误差度量添加新的分支误差度量的功能，比较路径误差度量，并选择具有最低路径错误度量的路径。在本发明中，ACS模块可以具有与其动态相关联的两个或更多个序列模型状态，使得在某些时候一个序列模型状态与其相关联，并且在其他时间，另一个序列模型状态与其相关联。这减少了所需的ACS模块的数量，并且还降低了解调器的路径存储器的大小/复杂性，这些存储器必须存储每个ACS模块的一个路径。与原始的未导通的维特比解调器相比，可以选择一组序列模型状态来共享ACS模块而没有显着的性能损失。本发明通过使分离的介质跃迁的预期采样序列可编程化来支持范围广泛的样本模型。本发明通过允许同时处理多个采样来降低检测器电路相对于采样率运行的速度。针对特定应用提出了特定样品序列模型的几种降低检测器。本发明可应用于其它类型的维特比检测器，例如用于卷积码的解码器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式