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    • 4. 发明授权
    • Filtering a read signal to attenuate secondary pulses caused by pole
tips of a thin film magnetic read head
    • 滤除读取信号以衰减由薄膜磁头读取头的极尖引起的次脉冲
    • US5623377A
    • 1997-04-22
    • US222666
    • 1994-04-04
    • Richard T. BehrensNeal GloverTrent O. DudleyAlan J. ArmstrongChristopher P. ZookWilliam G. Bliss
    • Richard T. BehrensNeal GloverTrent O. DudleyAlan J. ArmstrongChristopher P. ZookWilliam G. Bliss
    • G11B5/09G11B20/10H03H17/02H03H17/06H04B3/06G11B5/035
    • H03H17/06G11B20/10009G11B5/09H03H17/02
    • A filter for compensating discrete secondary pulse formations associated with a data stream of discrete main pulses produced from data read from magnetic media. The filter's impulse response comprises a center coefficient with side compensating coefficients for attenuating the secondary pulses when the input signal is convolved with the impulse response. The magnitude and delay of the compensation coefficients are programmable and are adaptively adjusted to optimize the impulse response for a given environment. In a traditional FIR embodiment, two delay lines are used to generate the two programmable delays between the center coefficient and side compensation coefficients. In the preferred embodiment, an IIR filter provides the two programmable delays using only one delay line thereby reducing the size and cost of the circuit. Also in the preferred embodiment, the data stream is interleaved into an even and odd data stream and processed in parallel by two filters in order to double the throughput. Further, the pre-cursor correcting portion of the filter can be disabled in order to avoid delaying the data stream while still canceling the post-cursor secondary pulses. The filter also comprises attenuation and adder means to match the coincident sample values in amplitude and add them to substantially eliminate the effect of the secondary pulses in the discrete data stream.
    • 用于补偿与从磁介质读取的数据产生的离散主脉冲的数据流相关联的离散次级脉冲形成的滤波器。 滤波器的脉冲响应包括具有侧补偿系数的中心系数,用于当输入信号与脉冲响应卷积时衰减次级脉冲。 补偿系数的幅度和延迟可编程,并进行自适应调整,以优化给定环境的脉冲响应。 在传统的FIR实施例中,使用两条延迟线来产生中心系数和侧面补偿系数之间的两个可编程延迟。 在优选实施例中,IIR滤波器仅使用一个延迟线提供两个可编程延迟,从而减小电路的尺寸和成本。 同样在优选实施例中,数据流被交织成偶数和奇数数据流,并且由两个滤波器并行处理,以使吞吐量翻倍。 此外,可以禁用滤波器的前光标校正部分,以避免在仍然取消后光标次级脉冲的同时延迟数据流。 滤波器还包括衰减和加法器装置,以使幅度上重合的采样值相匹配,并将它们相加,以基本上消除离散数据流中次级脉冲的影响。
    • 5. 发明授权
    • Method and apparatus for calibrating an analog filter in a sampled
amplitude read channel
    • 用于校准采样振幅读通道中的模拟滤波器的方法和装置
    • US5903857A
    • 1999-05-11
    • US751832
    • 1996-11-18
    • Richard T. BehrensTyson TuttleKent D. AndersonTrent O. DudleyWilliam G. Bliss
    • Richard T. BehrensTyson TuttleKent D. AndersonTrent O. DudleyWilliam G. Bliss
    • G11B20/10G06F17/10G11B5/035
    • G11B20/10055G11B20/10009G11B20/10037G11B20/10481
    • A method and apparatus for calibrating an analog equalizer in a sampled amplitude read channel is disclosed wherein the filter's frequency response is measured and calibrated directly. This is accomplished by injecting a known periodic signal into the analog filter and measuring a spectrum value at a predetermined frequency. The filter parameters are adjusted accordingly until the spectrum reaches a predetermined target value. In the preferred embodiment, the analog filter comprises at least one second order low pass filter (referred to as a biquad filter), and the filter's spectrum is adjusted relative to the well known parameters f.sub.o and Q. Specifically, the parameters f.sub.o and Q are optimized relative to a power measurement at predetermined harmonics of the input signal. In this manner, the present invention enables auto-calibration of the analog equalizer without reading any data from the disc. Furthermore, the calibration process can be executed during the storage system's normal operation without significantly degrading its overall performance.
    • 公开了一种用于校准采样振幅读通道中的模拟均衡器的方法和装置,其中滤波器的频率响应被直接测量和校准。 这是通过将已知的周期信号注入模拟滤波器并以预定频率测量频谱值来实现的。 相应地调整滤波器参数,直到频谱达到预定的目标值。 在优选实施例中,模拟滤波器包括至少一个二阶低通滤波器(称为双二阶滤波器),并且相对于众所周知的参数fo和Q调节滤波器的频谱。具体地,参数fo和Q是 相对于输入信号的预定谐波处的功率测量而优化。 以这种方式,本发明能够在不从盘读取任何数据的情况下自动校准模拟均衡器。 此外,可以在存储系统的正常操作期间执行校准过程,而不会显着降低其整体性能。
    • 8. 发明授权
    • Disk storage system employing error detection and correction of channel
coded data, interpolated timing recovery, and retroactive/split-segment
symbol synchronization
    • 磁盘存储系统采用通道编码数据的错误检测和校正,内插定时恢复和追溯/分段符号同步
    • US6009549A
    • 1999-12-28
    • US856885
    • 1997-05-15
    • William G. BlissChristopher P. ZookRichard T. Behrens
    • William G. BlissChristopher P. ZookRichard T. Behrens
    • G11B5/012G11B20/10G11B20/14G11B20/18G11B27/30C11C29/00G11B5/09
    • G11B20/10055G11B20/10009G11B20/1426G11B20/1833G11B27/3027G11B2020/1476G11B5/012
    • A disk storage system is disclosed wherein user data received from a host system is first encoded according to a first channel code having a high code rate, and then encoded according to an ECC code, such as a Reed-Solomon code, wherein the ECC redundancy symbols are encoded according to a second channel code having low error propagation. In the preferred embodiment, the first channel code is a RLL (d,k) code having a long k constraint which allows for longer block lengths (and higher code rates). During read back, a synchronous read channel samples the analog read signal a synchronously and interpolates the asynchronous sample values to generate sample values substantially synchronized to the baud rate. In contrast to conventional synchronous-sampling timing recovery, interpolated timing recovery can tolerate a longer RLL k constraint because it is less sensitive to noise in the read signal and not affected by process variations in fabrication. Additionally, a trellis sequence detector detects an estimated binary sequence from the synchronous sample values, wherein a state transition diagram of the trellis detector is configured according to the code constraints of the first and second channel codes. The estimated binary sequence output by the sequence detector is buffered in a data buffer to facilitate the error detection and correction process, and to allow for retroactive and split-segment symbol synchronization using multiple sync marks.
    • 公开了一种磁盘存储系统,其中根据具有高码率的第一信道码首先对从主机系统接收的用户数据进行编码,然后根据诸如Reed-Solomon码的ECC码进行编码,其中ECC冗余 符号根据具有低误差传播的第二信道码进行编码。 在优选实施例中,第一信道码是具有长k约束的RLL(d,k)码,其允许更长的码块长度(和较高码率)。 在读回期间,同步读通道同步地对模拟读取信号进行采样,并内插异步采样值,以生成基本上与波特率同步的采样值。 与传统的同步采样定时恢复相比,内插定时恢复可以容忍较长的RLL k约束,因为它对读取信号中的噪声不太敏感,并且不受制造过程变化的影响。 另外,网格序列检测器根据同步采样值检测估计的二进制序列,其中根据第一和第二信道码的编码约束配置网格检测器的状态转移图。 由序列检测器输出的估计的二进制序列被缓冲在数据缓冲器中,以便于错误检测和校正过程,并允许使用多个同步标记进行追溯和分段符号同步。
    • 10. 发明授权
    • Sampled amplitude read channel employing interpolated timing recovery
and a remod/demod sequence detector
    • 采用内插定时恢复的采样幅度读取通道和重构/解调序列检测器
    • US5771127A
    • 1998-06-23
    • US681678
    • 1996-07-29
    • David E. ReedWilliam R. Foland, Jr.William G. BlissRichard T. BehrensLisa C. Sundell
    • David E. ReedWilliam R. Foland, Jr.William G. BlissRichard T. BehrensLisa C. Sundell
    • G11B20/10G11B20/14G11B5/09
    • G11B20/10055G11B20/10009G11B20/10037G11B20/1426
    • In a computer disk storage system for recording binary data, a sampled amplitude read channel comprises a sampling device for asynchronously sampling pulses in an analog read signal from a read head positioned over a disk storage medium, interpolated timing recovery for generating synchronous sample values, and a sequence detector for detecting the binary data from the synchronous sample values. The sequence detector comprises a demodulator for detecting a preliminary binary sequence which may contain bit errors, a remodulator for remodulating to estimated sample values, a means for generating sample error values, an error pattern detector for detecting the bit errors, an error detection validator, and an error corrector for correcting the bit errors. The remodulator comprises a partial erasure circuit which compensates for the non-linear reduction in amplitude of a primary pulse caused by secondary pulses located near the primary pulse. The error pattern detector comprises a peak error pattern detector and, if an error pattern is detected, a means for disabling the error pattern detector until the detected error pattern has been fully processed. The error detection validator checks the validity of a detected error event and, if valid, enables operation of the error corrector.
    • 在用于记录二进制数据的计算机磁盘存储系统中,采样幅度读取通道包括用于从位于盘存储介质上的读取头的模拟读取信号中异步采样脉冲的采样装置,用于产生同步采样值的内插定时恢复,以及 序列检测器,用于从同步样本值检测二进制数据。 序列检测器包括用于检测可能包含位错误的初步二进制序列的解调器,用于重新调制到估计样本值的再调制器,用于产生采样误差值的装置,用于检测位错误的误差模式检测器,错误检测验证器, 以及用于校正位错误的纠错器。 再调制器包括部分擦除电路,其补偿由位于主脉冲附近的次级脉冲引起的初级脉冲的幅度的非线性减小。 误差模式检测器包括峰值误差模式检测器,并且如果检测到错误模式,则用于禁止错误模式检测器的装置,直到检测到的错误模式被完全处理为止。 错误检测验证器检查检测到的错误事件的有效性,如果有效,则允许错误校正器的操作。