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81. 发明申请

US20210288667A1 ENCODING METHOD AND DEVICE, DECODING METHOD AND DEVICE, AND STORAGE MEDIUM 有权
公开(公告)号：US20210288667A1
公开(公告)日：2021-09-16
申请号：US16325030
申请日：2017-08-01
申请人： ZTE CORPORATION
发明人： Jin Xu , Jun Xu , Liguang Li
IPC分类号： H03M13/11 , H03M13/00 , G06F7/40 , G06F7/42 , G06F7/499
摘要： Provided are an encoding method and device, a decoding method and device, and a storage medium. The encoding method comprises: encoding an initial to-be-encoded bit sequence with a low density parity check code LDPC having a code rate R1, to obtain an encoded first bit sequence, where 0≤R1≤1; linearly combining at least two bit sequence segments in the first bit sequence to obtain a second bit sequence; and cascading the first bit sequence and the second bit sequence to obtain a target bit sequence having a code rate R2, where 0≤R2≤R1≤1.

82. 发明授权

US10191749B2 Scatter reduction instruction 有权
公开(公告)号：US10191749B2
公开(公告)日：2019-01-29
申请号：US15301206
申请日：2015-12-24
申请人： INTEL CORPORATION
发明人： Jun Jin , Elmoustapha Ould-Ahmed-Vall
IPC分类号： G06F7/42 , G06F9/302 , G06F15/80 , G06F9/38 , G06F9/30 , G06F7/498 , G06F7/485
摘要： Single Instruction, Multiple Data (SIMD) technologies are described. A processing device can include a processor core and a memory. The processor core can receive, from a software application, a request to perform an operation on a first set of variables that includes a first input value and a register value and perform the operation on a second set of variables that includes a second input value and the first register value. The processor core can vectorize the operation on the first set of variables and the second set of variables. The processor core can perform the operation on the first set of variables and the second set of variables in parallel to obtain a first operation value and a second operation value. The processor core can perform a horizontal add operation on the first operation value and the second operation value and write the result to memory.

83. 发明授权

US09685975B2 Distributed combiner for parallel discrete-to-linear converters 有权
公开(公告)号：US09685975B2
公开(公告)日：2017-06-20
申请号：US14996497
申请日：2016-01-15
申请人： Syntropy Systems, LLC
发明人： Christopher Pagnanelli
IPC分类号： G06F7/42 , H03M1/66 , H03F3/21 , H03M1/08 , H03M3/00
CPC分类号： H03M1/661 , H03F3/211 , H03M1/08 , H03M1/0836 , H03M1/662 , H03M3/30 , H03M3/50
摘要： Provided are, among other things, systems, apparatuses methods and techniques for providing a complete output signal from a set of partial signals, which in turn have been generated by parallel processing paths in the time-interleaved and/or frequency-interleaved conversion of discrete signals to linear signals (i.e., discrete-to-linear conversion). One such apparatus includes a distributed network comprising a plurality of ladder networks through which input signals propagate before being combined to form an output signal.

84. 发明授权

US08898214B2 Method and apparatus to perform floating point operations 有权
标题翻译：执行浮点运算的方法和装置
公开(公告)号：US08898214B2
公开(公告)日：2014-11-25
申请号：US13453056
申请日：2012-04-23
申请人： Leonid Dubrovin , Alexander Rabinovitch
发明人： Leonid Dubrovin , Alexander Rabinovitch
IPC分类号： G06F7/42
CPC分类号： G06F7/485
摘要： A method of subtracting floating-point numbers includes determining whether a first sign associated with a first floating-point number is unequal to a second sign associated with a second floating-point number, determining whether a first exponent associated with the first floating-point number is less than a second exponent associated with the second floating-point number, negating a first mantissa associated with the first floating-point number when the first sign is unequal to the second sign and determining that the first exponent is less than the second exponent, and adding the first mantissa to a second mantissa associated with the second floating-point number when the first sign is unequal to the second sign and determining that the first exponent is less than the second exponent. Embodiments of a corresponding computer-readable medium and device are also provided.
摘要翻译：减去浮点数的方法包括确定与第一浮点数相关联的第一符号是否不等于与第二浮点数相关联的第二符号，确定是否与第一浮点数相关联的第一指数小于与第二浮点数相关联的第二指数，当第一符号不等于第二符号并且确定第一指数小于第二指数时，否定与第一浮点数相关联的第一尾数，以及当所述第一符号不等于所述第二符号并且确定所述第一指数小于所述第二指数时，将所述第一尾数添加到与所述第二浮点数相关联的第二尾数。还提供了相应的计算机可读介质和设备的实施例。

85. 发明授权

US08713081B2 Look up table (LUT) structure supporting exclusive OR (XOR) circuitry configured to allow for generation of a result using quaternary adders 有权
标题翻译：查找表（LUT）结构，支持异或（XOR）电路，配置为允许使用四进制加法器生成结果
公开(公告)号：US08713081B2
公开(公告)日：2014-04-29
申请号：US13865891
申请日：2013-04-18
申请人： Altera Corporation
发明人： Martin Langhammer
IPC分类号： G06F7/42
CPC分类号： G06F17/10 , G06F7/5057 , G06F7/506 , G06F7/509
摘要： A lookup table structure having multiple lookup tables is configured to include a quaternary adder. In particular examples, an adaptive logic module (ALM) including a fracturable lookup table (LUT) is configured to include a quaternary (4-1) adder. In some examples, only an XOR gate, an AND gate, two single bit 2-1 multiplexers, and minor connectivity changes to a LUT structure supporting a ternary (3-1) adder are needed to support 4-1 adders. Binary (2-1) and ternary adders are still supported using the original signal flows, as the ternary adder feature can be easily multiplexed out.
摘要翻译：具有多个查找表的查找表结构被配置为包括四进制加法器。在具体示例中，包括可分解查找表（LUT）的自适应逻辑模块（ALM）被配置为包括四进制（4-1）加法器。在一些示例中，仅需要XOR门，AND门，两个单位2-1多路复用器以及支持三进制（3-1）加法器的LUT结构的次要连接性改变以支持4-1加法器。二进制（2-1）和三进制加法器仍然支持使用原始信号流，因为三进制加法器特征可以容易地多路复用。

86. 发明授权

US08549054B2 Arithmetic processing apparatus and arithmetic processing method 失效
标题翻译：算术处理装置和算术处理方法
公开(公告)号：US08549054B2
公开(公告)日：2013-10-01
申请号：US12230029
申请日：2008-08-21
申请人： Ryuji Kan
发明人： Ryuji Kan
IPC分类号： G06F7/00 , G06F7/42
CPC分类号： G06F7/38
摘要： In an arithmetic processing apparatus, a dividing unit divides a second bit string into a low-order bit part having a bit width equal to a first bit width and a high-order bit part which is higher than the low-order bit part, a first arithmetic unit performs arithmetic operations for a carry to and a borrow from the high-order bit part; and a second arithmetic unit performs addition of absolute values of the low-order bit part and the first bit string. Finally, a selecting unit selects an output of the first arithmetic unit from among an arithmetic operation result with a carry, an arithmetic operation result with a borrow, and the high-order bit part itself, according to information about the high-order bit part, sign information of the first bit string and the second bit string, and an intermediate result of the addition of the absolute values by the second arithmetic unit.
摘要翻译：在算术处理装置中，分割单元将第二比特串分为具有等于第一比特宽度的比特宽度的低位比特部分和高于低位比特部分的高位比特部分，第一算术单元对从高位位进行进位和借位执行算术运算; 并且第二运算单元执行所述低位位部分和所述第一位串的绝对值的相加。最后，选择单元根据有关高位位部分的信息，从具有进位的算术运算结果，借位运算结果和高阶位部分本身中选择第一算术单元的输出，第一位串和第二位串的符号信息，以及由第二运算单元添加绝对值的中间结果。

87. 发明授权

US08471621B2 Circuit and method for performing arithmetic operations on current signals 有权
标题翻译：对电流信号执行算术运算的电路和方法
公开(公告)号：US08471621B2
公开(公告)日：2013-06-25
申请号：US13458118
申请日：2012-04-27
申请人： Marko Mailand , Stefan Getzlaff
发明人： Marko Mailand , Stefan Getzlaff
IPC分类号： G06F7/42
CPC分类号： G06G7/14
摘要： A circuit for performing arithmetic operations includes a differential capacitive transimpedance amplifier (CTIA) and a cross-multiplexer. The cross multiplexer forwards the current to be integrated out of a plurality of current sources either to the positive input port of the differential CTIA for positive integration in direct mode or to the negative input port of the differential CTIA for negative integration in reverse mode.
摘要翻译：用于执行算术运算的电路包括差分电容互阻抗放大器（CTIA）和交叉多路复用器。交叉多路复用器将要从多个电流源中集成的电流转发到差分CTIA的正输入端口，以便在直接模式下进行积分积分，或将差分CTIA的负输入端口反向反向转换。

88. 发明授权

US08447798B2 Look up table (LUT) structure supporting exclusive or (XOR) circuitry configured to allow for generation of a result using quaternary adders 有权
标题翻译：查找表（LUT）结构，支持独占或（XOR）电路，配置为允许使用四进制加法器生成结果
公开(公告)号：US08447798B2
公开(公告)日：2013-05-21
申请号：US12732104
申请日：2010-03-25
申请人： Martin Langhammer
发明人： Martin Langhammer
IPC分类号： G06F7/42
CPC分类号： G06F17/10 , G06F7/5057 , G06F7/506 , G06F7/509
摘要： A lookup table structure having multiple lookup tables is configured to include a quaternary adder. In particular examples, an adaptive logic module (ALM) including a fracturable lookup table (LUT) is configured to include a quaternary (4-1) adder. In some examples, only an XOR gate, an AND gate, two single bit 2-1 multiplexers, and minor connectivity changes to a LUT structure supporting a ternary (3-1) adder are needed to support 4-1 adders. Binary (2-1) and ternary adders are still supported using the original signal flows, as the ternary adder feature can be easily multiplexed out.
摘要翻译：具有多个查找表的查找表结构被配置为包括四进制加法器。在具体示例中，包括可分解查找表（LUT）的自适应逻辑模块（ALM）被配置为包括四进制（4-1）加法器。在一些示例中，仅需要XOR门，AND门，两个单位2-1多路复用器以及支持三进制（3-1）加法器的LUT结构的次要连接性改变以支持4-1加法器。二进制（2-1）和三进制加法器仍然支持使用原始信号流，因为三进制加法器特征可以容易地多路复用。

89. 发明申请

US20120259906A1 ARITHMETIC CIRCUIT, ARITHMETIC PROCESSING APPARATUS AND METHOD OF CONTROLLING ARITHMETIC CIRCUIT 失效
标题翻译：算术电路，算术处理装置和控制算术电路的方法
公开(公告)号：US20120259906A1
公开(公告)日：2012-10-11
申请号：US13441020
申请日：2012-04-06
申请人： Ryuji Kan , Hideyuki Unno , Kenichi Kitamura
发明人： Ryuji Kan , Hideyuki Unno , Kenichi Kitamura
IPC分类号： G06F7/42
CPC分类号： G06F7/483 , G06F7/49942
摘要： An arithmetic circuit calculates a correction value for a value that is obtained by an add-subtract operation of two values and that is expressed in a predetermined fixed precision.
摘要翻译：算术电路计算通过两个值的加减运算获得的并以预定的固定精度表示的值的校正值。

90. 发明申请

US20120259905A1 ARITHMETIC CIRCUIT, ARITHMETIC PROCESSING APPARATUS AND METHOD OF CONTROLLING ARITHMETIC CIRCUIT 有权
标题翻译：算术电路，算术处理装置和控制算术电路的方法
公开(公告)号：US20120259905A1
公开(公告)日：2012-10-11
申请号：US13437969
申请日：2012-04-03
申请人： Ryuji KAN , Hideyuki UNNO , Kenichi Kitamura
发明人： Ryuji KAN , Hideyuki UNNO , Kenichi Kitamura
IPC分类号： G06F7/42
CPC分类号： G06F7/49942 , G06F7/483
摘要： An arithmetic circuit for quantizing pre-quantized data includes a first input register to store first-format pre-quantized data that includes a mantissa and an exponent, a second input register to store a quantization target exponent, an exponent-correction-value indicating unit to indicate an exponent correction value, an exponent generating unit to generate a quantized exponent obtained by subtracting the exponent correction value from the quantization target exponent, a shift amount generating unit to generate a shift amount obtained by subtracting the exponent of the pre-quantized data and the exponent correction value from the quantization target exponent, a shift unit to generate a quantized mantissa obtained by shifting the mantissa of the pre-quantized data by the shift amount generated by the shift amount generating unit, and an output register to store quantized data that includes the quantized exponent generated by the exponent generating unit and the quantized mantissa generated by the shift unit.
摘要翻译：用于量化预量化数据的算术电路包括：第一输入寄存器，用于存储包括尾数和指数的第一格式的预量化数据;存储量化目标指数的第二输入寄存器;指数校正值指示单元指示指数校正值，指数生成单元，用于生成通过从量化目标指数中减去指数校正值而获得的量化指数;移位量生成单元，生成通过减去预量化数据的指数得到的移位量以及来自量化目标指数的指数校正值，用于生成通过将预量化数据的尾数移位由移位量产生单元生成的移位量而获得的量化尾数的移位单元和存储量化数据的输出寄存器其包括由指数生成单元生成的量化指数和量化的尾数gen 由换档单元擦除。

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