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81. 发明授权

US06963238B2 Level shift circuit 失效
标题翻译：电平移位电路
公开(公告)号：US06963238B2
公开(公告)日：2005-11-08
申请号：US10849200
申请日：2004-05-20
申请人： Kouji Mochizuki
发明人： Kouji Mochizuki
IPC分类号： H03M1/74 , H03F3/45 , H03K5/08 , H03L5/00 , H03M1/10 , H03M1/66 , H03M1/70
CPC分类号： H03F3/45475 , H03F3/45941 , H03F3/45959 , H03F2203/45212 , H03F2203/45588
摘要： A high-precision and high-performance level shift circuit, which is not adversely influenced by an offset error owned by an operational amplifier. Two sets of resistors (4o) and (4p) having the same resistance values, which are connected between differential output terminals and an operational amplifier (4r) for performing a level shift control are provided. A feedback operation is carried out in such a manner that an average voltage of each of differential outputs (4i) and (4m) is continuously made coincident with a DC reference potential (4q) irrespective of an offset error of an output-purpose operational amplifier, and a level shift function having a small error is realized. Two resistors (4h and 4l) are series-connected between a differential output of a digital/analog converter (4a) and a level shift circuit to output a voltage outside an output dynamic range of the digital/analog converter (4a).
摘要翻译：高精度，高性能的电平移位电路，不受运算放大器拥有偏移误差的不利影响。提供两组具有相同电阻值的电阻器（4o）和（4p），其连接在差分输出端子和用于执行电平转换控制的运算放大器（4r）之间。执行反馈操作，使得差分输出（4i）和（4m）中的每一个的平均电压连续地与DC参考电位（4q）一致，而不管输出 - 输出的偏移误差如何，实现了目的运算放大器和具有小误差的电平移位功能。两个电阻器（4h和4l）串联连接在数/模转换器（4a）的差分输出端和电平移位电路之间，以输出数/模转换器（4a）的输出动态范围之外的电压）。

82. 发明申请

US20050225465A1 Current-steering digital-to-analog converter having a minimum charge injection latch 有权
标题翻译：具有最小电荷注入锁存器的电流转向数模转换器
公开(公告)号：US20050225465A1
公开(公告)日：2005-10-13
申请号：US10823046
申请日：2004-04-13
申请人： Weibiao Zhang , Bertan Bakkaloglu
发明人： Weibiao Zhang , Bertan Bakkaloglu
IPC分类号： H03M1/06 , H03M1/66 , H03M1/74
CPC分类号： H03M1/0624 , H03M1/747
摘要： A latch architecture for driving unit current cell of a current-steering digital-to-analog converter (DAC) which reduces the drain-source voltage variation of the output current-source transistors and reduces the coupling of unwanted injection of input digital signals as well as clock signals is presented herein. Moreover, this latch helps to achieve lower glitch during code transition with improved dynamic performance. The latch effectively uses the intrinsic RC delay of most transistors within the latch architecture in order to achieve optimal crossing points of complementary control signals. Unwanted input injection or cross-talk is reduced by introducing transistors (904, 906, 932 and 934) that are off during code transitions without compromising the DAC update speed. Conflicts between currently held and new inputs are avoided in an effort to reduce the harmonic distortion. Furthermore, the distortion as a result of the clock signal fed through each transistor in the first and second subcircuit portions cancel each other.
摘要翻译：用于驱动电流转向数模转换器（DAC）的单元电流单元的锁存架构，其减小输出电流源晶体管的漏源电压变化，并减少输入数字信号的不期望的注入的耦合因为这里呈现时钟信号。此外，该锁存器有助于在代码转换期间实现较低的毛刺，并提高动态性能。锁存器有效地使用锁存器架构内大多数晶体管的固有RC延迟，以实现互补控制信号的最佳交叉点。通过引入在代码转换期间关闭而不损害DAC更新速度的晶体管（904,906,932和934）来减少不需要的输入注入或串扰。为了减少谐波失真，避免了当前持有的和新的输入之间的冲突。此外，作为通过第一和第二子电路中的每个晶体管馈送的时钟信号的结果的失真彼此抵消。

83. 发明授权

US06954473B2 Optoelectronic device employing at least one semiconductor heterojunction thyristor for producing variable electrical/optical delay 有权
标题翻译：使用至少一个半导体异质结晶闸管产生可变电/光延迟的光电器件
公开(公告)号：US06954473B2
公开(公告)日：2005-10-11
申请号：US10280892
申请日：2002-10-25
申请人： Rohinton Dehmubed , Geoff W. Taylor , Daniel C. Upp , Jianhong Cai
发明人： Rohinton Dehmubed , Geoff W. Taylor , Daniel C. Upp , Jianhong Cai
IPC分类号： H01L21/331 , H01L21/335 , H01L29/15 , H01L29/80 , H03K17/79 , H03M1/66 , H03M1/74 , H03M1/80 , H01S3/10
CPC分类号： H01L29/66318 , H01L29/155 , H01L29/66462 , H01L29/802 , H03K17/79 , H03M1/667 , H03M1/74 , H03M1/808
摘要： An optoelectronic integrated circuit includes a resonant cavity formed on a substrate. A heterojunction thyristor device is formed in the resonant cavity and operates to detect an input optical pulse (or input electrical pulse) and produce an output optical pulse via laser emission in response to the detected input pulse. The heterojunction thyristor device includes a channel region that is coupled to a current source that draws current from the channel region. Time delay between the input pulse and output optical pulse may be varied by configuring the current source to draw constant current from the channel region and modulating the intensity of the input pulse, or by varying the amount of current drawn from the channel region by the current source. The heterojunction thyristor device may be formed from a multilayer structure of group III-V materials, or from a multilayer structure of strained silicon materials. A plurality of such heterojunction thyristor based optoelectronic integrated circuits can be used to provide variable pulse delay over a plurality of channels. In addition, the heterojunction thyristor device is easily integrated with other optoelectronic devices formed from the same growth structure to form monolithic optoelectronic integrated circuits suitable for many diverse applications, including phased array communication systems.
摘要翻译：光电集成电路包括形成在基板上的谐振腔。异相结晶闸管器件形成在谐振腔中，用于检测输入光脉冲（或输入电脉冲），并响应于检测到的输入脉冲通过激光发射产生输出光脉冲。异质结晶闸管器件包括耦合到电流源的沟道区，其从沟道区抽取电流。输入脉冲和输出光脉冲之间的时间延迟可以通过配置电流源来从通道区域抽取恒定电流并调制输入脉冲的强度，或者通过改变从通道区域引出的电流量来改变电流资源。异质结晶闸管器件可以由III-V族材料的多层结构或者由应变硅材料的多层结构形成。可以使用多个这样的异质结晶闸管的光电集成电路来在多个通道上提供可变的脉冲延迟。此外，异质结晶闸管器件容易与由相同生长结构形成的其它光电器件集成，以形成适用于许多不同应用的单片光电集成电路，包括相控阵通信系统。

84. 发明申请

US20050200509A1 CURRENT CELL MATRIX TYPE DIGITAL-TO-ANALOG CONVERTER 有权
标题翻译：电流矩阵型数字到模拟转换器
公开(公告)号：US20050200509A1
公开(公告)日：2005-09-15
申请号：US10983644
申请日：2004-11-09
申请人： Masaru Sekiguchi
发明人： Masaru Sekiguchi
IPC分类号： H03M1/74 , H03M1/06 , H03M1/66 , H03M1/68
CPC分类号： H03M1/0607 , H03M1/685 , H03M1/687 , H03M1/745 , H03M1/747
摘要： A converter 10 selects desired unit current cells from unit current cells 16, 18, 20, 22 in accordance with an input code 102, and supplies currents from the selected cells to a load resistor 24 to generate an analog voltage Vdac. By supplying the constant current comprised of the currents from the selected cells and currents from non-selected cells to an offset adjuster circuit 26 including an adjusting resister 28 to generate an offset voltage Vos, the converter 10 can output a voltage Vout which is the sum of the analog voltage Vdac and the offset voltage Vos.
摘要翻译： A转换器10根据输入代码102从单位当前单元16,18,20,22选择所需的单位电流单元，并且将来自所选单元的电流提供给负载电阻器24以产生模拟电压Vdac。通过将来自所选择的单元的电流和来自未选择的单元的电流的恒定电流提供给包括调整电阻器28的偏移调整器电路26以产生偏移电压Vos，转换器10可输出作为总和的电压Vout 的模拟电压Vdac和偏移电压Vos。

85. 发明授权

US06940434B2 Methods and systems for digital dither 有权
标题翻译：数字抖动的方法和系统
公开(公告)号：US06940434B2
公开(公告)日：2005-09-06
申请号：US10861377
申请日：2004-06-07
申请人： Todd Lee Brooks
发明人： Todd Lee Brooks
IPC分类号： H03M1/06 , H03M1/74 , H03M3/04 , H03M1/20
CPC分类号： H03M1/0641 , H03M1/74 , H03M3/332 , H03M3/424
摘要： Methods and systems for applying digital dither includes methods and systems for applying digital dither in data converters, such as, for example, delta-sigma data converters. In an embodiment, an analog signal from a first path of a delta-sigma modulator is quantized to an m-bit digital signal and an n-bit dithered digital feedback signal is generated from at least a portion of the m-bit digital signal. The n-bit dithered digital feedback signal is converted to an analog feedback signal and fed back to a second path of the delta-sigma modulator. In an embodiment, the n-bit dithered digital feedback signal is generated by selecting one of a plurality of sets of n-bits from the m-bit digital signal depending upon a state of a dither control signal. The dither control signal can alternate between a plurality of states or pseudo-randomly switch between a plurality of states. In an embodiment, the m-bit digital signal is an m-bit thermometer code signal and the n-bit dithered digital feedback signal is generated by selecting between bits 0 through m-2 and bits 1 through m-1 of the m-bit digital signal. In an alternative embodiment, the m-bit digital signal is an m-bit thermometer code signal and the n-bit dithered digital feedback signal is generated by selecting between even and odd bits of the m-bit digital signal.
摘要翻译：应用数字抖动的方法和系统包括在数据转换器（例如，Δ-Σ数据转换器）中应用数字抖动的方法和系统。在一个实施例中，来自Δ-Σ调制器的第一路径的模拟信号被量化为m位数字信号，并且从m位数字信号的至少一部分产生n位抖动数字反馈信号。 n位抖动数字反馈信号被转换成模拟反馈信号并反馈到Δ-Σ调制器的第二路径。在一个实施例中，根据抖动控制信号的状态，通过从m位数字信号中选择多个n位组中的一个产生n位抖动数字反馈信号。抖动控制信号可以在多个状态之间交替，或者在多个状态之间进行伪随机切换。在一个实施例中，m位数字信号是m位温度计代码信号，并且n位抖动数字反馈信号是通过在位0至m-2和m位的位1至m-1之间进行选择而产生的数字信号。在替代实施例中，m位数字信号是m位温度计代码信号，并且通过在m位数字信号的偶数位和奇数位之间进行选择来产生n位抖动数字反馈信号。

86. 发明申请

US20050190086A1 Digital to analog conversion 有权
标题翻译：数模转换
公开(公告)号：US20050190086A1
公开(公告)日：2005-09-01
申请号：US10511974
申请日：2003-03-19
申请人： Jan Westra
发明人： Jan Westra
IPC分类号： H03M1/74 , H03K17/041 , H03K17/693 , H03M1/08 , H03M1/00
CPC分类号： H03K17/04106 , H03K17/693
摘要： A unit cell for a digital to analog conversion circuit comprising; a current source (CS); a first data switch (S1) coupled to the circuit source (CS); a second data switch (S2) coupled to the current source (CS); a first phase switch (Phi 1) coupled between the current source (CS) and the first data switch (S1); a second phase switch (Phi2) coupled between the current source (CS) and the second data switch (S2); a controller arranged to switch between the first (Phi1) and second (Phi2) phase switches in a Break Before Make alternating sequence, and to switch the first (S1) and second (S2) data switches in a Make Before Break sequence. A digital to analog convector circuit constructed using unit cells according to the invention is more area and power efficient than the previously known circuit because it uses only one current source, yet it succeeds in preventing short-circuit error currents between the outputs and solves the problems caused by pulse asymmetry and the influence of switch-charge injection, and provides more linear and better quality output signals.
摘要翻译：一种用于数模转换电路的单元，包括：电流源（CS）; 耦合到电路源（CS）的第一数据开关（S1）; 耦合到电流源（CS）的第二数据开关（S 2）; 耦合在电流源（CS）和第一数据开关（S1）之间的第一相位开关（Phi 1）; 耦合在电流源（CS）和第二数据开关（S 2）之间的第二相位开关（Phi2）; 控制器，其布置成在进行交替间隔之前在第一（Phi 1）和第二（Phi 2）相位开关之间切换，并且在第一（S1）和第二（S2）数据开关中断序列。使用根据本发明的单元单元构建的数模对流对数电路比以前已知的电路具有更多的面积和功率效率，因为它仅使用一个电流源，但它成功地防止了输出之间的短路误差电流并解决了问题引起脉冲不对称和开关电荷注入的影响，并提供更线性和更好质量的输出信号。

87. 发明授权

US06919834B2 Circuit, display device, and electronic device 有权
标题翻译：电路，显示设备和电子设备
公开(公告)号：US06919834B2
公开(公告)日：2005-07-19
申请号：US10747693
申请日：2003-12-30
申请人： Kazutaka Inukai
发明人： Kazutaka Inukai
IPC分类号： G02F1/133 , G09G3/32 , G09G3/36 , H03M1/08 , H03M1/66 , H03M1/74
CPC分类号： G09G3/3283 , G09G3/3241 , H03M1/0863 , H03M1/742
摘要： An object of the present invention is to provide a method for shortening a setting time of an analog current to be outputted in a DA converter circuit which reads in digital voltage value data and outputs analog current value data. The present invention can be used for a data driver circuit in an AM type OLED display device. The present invention provides a function of applying a constant voltage exceptionally in the case where data to be inputted takes a predetermined value for a current output DA converter circuit. Consequently, a setting time of an analog current to be outputted for low current data and the like can be shortened.
摘要翻译：本发明的目的是提供一种缩短在DA转换器电路中输出的模拟电流的设定时间的方法，该DA转换器电路读入数字电压值数据并输出模拟电流值数据。本发明可用于AM型OLED显示装置中的数据驱动电路。本发明提供了在输入数据对于电流输出DA转换器电路具有预定值的情况下特别施加恒定电压的功能。因此，可以缩短针对低电流数据等输出的模拟电流的设定时间。

88. 发明授权

US06917322B2 I/V converter circuit and D/A converter 有权
标题翻译： I / V转换器电路和D / A转换器
公开(公告)号：US06917322B2
公开(公告)日：2005-07-12
申请号：US10801812
申请日：2004-03-17
申请人： Masayuki Ueno , Masatoshi Takada , Hiroshi Ogasawara
发明人： Masayuki Ueno , Masatoshi Takada , Hiroshi Ogasawara
IPC分类号： H03M1/74 , H03F3/343 , H03M1/00 , H03M1/06 , H03M1/66
CPC分类号： H03M1/0604 , H03M1/742
摘要： In an I/V converter circuit and a D/A converter, a wide pass band for signal can be obtained and current consumption can be reduced. A current is supplied through an input terminal to a first node, and a first bias current is supplied from a first bias-current generating circuit to the first node. The current supplied to the first node is mirrored to a second node, and a second bias current is supplied from a second bias-current generating circuit to the second node. A first control circuit controls first and second elements of a current mirror circuit so that the voltage of the first node is substantially equal to a bias voltage, a third element converts a current flowing therethrough to a voltage by using the bias voltage as reference, and a second control circuit controls the voltage output from an output terminal so that the voltage of the second node is substantially equal to the bias voltage.
摘要翻译：在I / V转换器电路和D / A转换器中，可以获得用于信号的宽通带，并且可以降低电流消耗。电流通过输入端子提供给第一节点，并且第一偏置电流从第一偏置电流产生电路提供给第一节点。提供给第一节点的电流被镜像到第二节点，并且第二偏置电流从第二偏置电流产生电路提供给第二节点。第一控制电路控制电流镜电路的第一和第二元件，使得第一节点的电压基本上等于偏置电压，第三元件通过使用偏置电压作为参考，将流过其中的电流转换为电压，以及第二控制电路控制从输出端子输出的电压，使得第二节点的电压基本上等于偏置电压。

89. 发明授权

US06906652B2 High dynamic linearity current-mode digital-to-analog converter architecture 有权
标题翻译：高动态线性度电流模式数模转换器架构
公开(公告)号：US06906652B2
公开(公告)日：2005-06-14
申请号：US10653710
申请日：2003-09-02
申请人： Alexander Bugeja
发明人： Alexander Bugeja
IPC分类号： H03M1/06 , H03M1/68 , H03M1/74 , H03M1/66 , H03M1/80
CPC分类号： H03M1/0643 , H03M1/682 , H03M1/747
摘要： The present invention dramatically reduces dynamic mismatches between the different current segments of a segmented current-mode DAC. By providing substantially the same local architecture for each of the individual current segments, parasitic effects of any physical realization can be controlled. In one embodiment, the most-significant-bit (MSB) current segments and the least-significant-bit (LSB) current segments each have the same number of multiple internal current branches. In the MSB segments, the multiple internal current branches are combined at a source node; whereas, in the LSB segment, a portion of the segment current is dumped, or wasted, through at least some of the internal current branches.
摘要翻译：本发明大大减少了分段电流模式DAC的不同电流段之间的动态失配。通过为每个单独的当前段提供基本上相同的本地架构，可以控制任何物理实现的寄生效应。在一个实施例中，最高有效位（MSB）电流段和最低有效位（LSB）电流段各自具有相同数量的多个内部电流分支。在MSB段中，多个内部电流分支在源节点处组合; 而在LSB段中，段电流的一部分通过至少一些内部电流分支被转储或浪费。

90. 发明申请

US20050110665A1 D/A converter circuit, organic EL drive circuit and organic EL display device 有权
公开(公告)号：US20050110665A1
公开(公告)日：2005-05-26
申请号：US10994293
申请日：2004-11-23
申请人： Jun Maede , Shinichi Abe , Masanori Fujisawa
发明人： Jun Maede , Shinichi Abe , Masanori Fujisawa
IPC分类号： G09G3/30 , G09G3/32 , H03M1/00 , H03M1/66 , H03M1/74 , H05B33/00
CPC分类号： G09G3/3283 , G09G2300/0417 , G09G2310/0251 , G09G2310/027 , G09G2320/0233 , H03M1/747
摘要： In a D/A converter circuit including a current mirror circuit constructed with an input side transistor circuit and an output side transistor circuit, the input side transistor circuit comprises a series circuit of a first MOS transistor and a second MOS transistor and a first switch circuit connected in parallel to the first MOS transistor. Gates of the first and second MOS transistors are connected commonly and a source of either one of the first and second MOS transistors is connected to a drain of the other of the first and second MOS transistors and the second MOS transistor has a gate length shorter than a gate length of the first MOS transistor.

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