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1. 发明授权

US09236967B1 Methods of packet-based synchronization in non-stationary network environments 有权
标题翻译：非平稳网络环境中基于分组的同步方法
公开(公告)号：US09236967B1
公开(公告)日：2016-01-12
申请号：US13799086
申请日：2013-03-13
申请人： Integrated Device Technology, Inc.
发明人： Frederic Mustiere , Russell Smiley , Felix Duong , Alain Trottier , Durrey Farooqui , Peng Xiao
IPC分类号： H04J3/06
CPC分类号： H04J3/0661 , H04J3/0667
摘要： Methods of packet-based synchronization in non-stationary network environments can include accumulating timestamps transmitted in packets between master and slave devices that are separated from each other by a packet network. Operations are also performed to determine whether first timestamps accumulated in a first direction across the packet network demonstrate that a first packet delay variation (PDV) sequence observed from the first timestamps is stationary. Thereafter, estimates of at least one of frequency skew and phase offset between the master and slave clocks are acquired using a first algorithm, from the first timestamps accumulated in the first direction. These operations of determining further include determining whether second timestamps accumulated in a second direction demonstrate that a second packet delay variation (PDV) sequence observed from the second timestamps is stationary.
摘要翻译：在非固定网络环境中基于分组的同步的方法可以包括在通过分组网络彼此分离的主设备和从设备之间的分组中累积传输的时间戳。还执行操作以确定跨分组网络在第一方向上累积的第一时间戳是否显示从第一时间戳观察到的第一分组延迟变化（PDV）序列是静止的。此后，从第一方向累积的第一时间戳，使用第一算法获取主时钟与从时钟之间的频率偏移和相位偏移中的至少一个的估计。进一步确定的这些操作还包括确定在第二方向上累积的第二时间戳是否表明从第二时间戳观察到的第二分组延迟变化（PDV）序列是静止的。

2. 发明授权

US09065459B1 Clock generation circuits using jitter attenuation control circuits with dynamic range shifting 有权
标题翻译：使用具有动态范围移位的抖动衰减控制电路的时钟发生电路
公开(公告)号：US09065459B1
公开(公告)日：2015-06-23
申请号：US13829202
申请日：2013-03-14
申请人： Integrated Device Technology, Inc.
发明人： Brian Buell
IPC分类号： H03L7/087 , H03L7/197 , H03L7/22
CPC分类号： H03L7/087 , H03L7/1974 , H03L7/1976 , H03L7/235
摘要： An apparatus includes a phase locked loop (PLL) circuit configured to generate a PLL output signal from an oscillator signal and a control circuit configured to generate a measure of a difference between the PLL output signal and an input clock signal at a control output thereof. The apparatus further includes a dynamic range shifter circuit coupling the control output of the control circuit to a control input (e.g., a feedback divider control input) of the PLL circuit and configured to shift a dynamic range of the control output of the control circuit with respect to a dynamic range of the control input of the PLL circuit. The apparatus may be implemented with an oscillator, such as a MEMs oscillator, in a single chip.
摘要翻译：一种装置包括：锁相环（PLL）电路，被配置为从振荡器信号产生PLL输出信号;以及控制电路，被配置为在其控制输出处产生PLL输出信号与输入时钟信号之间的差值的量度。该装置还包括动态范围移动器电路，其将控制电路的控制输出耦合到PLL电路的控制输入（例如，反馈分配器控制输入），并被配置为将控制电路的控制输出的动态范围与相对于PLL电路的控制输入的动态范围。该装置可以用单个芯片中的诸如MEM振荡器的振荡器来实现。

3. 发明授权

US08826057B1 Multiple time domain synchronizer circuits 有权
标题翻译：多个时域同步器电路
公开(公告)号：US08826057B1
公开(公告)日：2014-09-02
申请号：US13538643
申请日：2012-06-29
申请人： Bruce Lorenz Chin , David Stuart Gibson
发明人： Bruce Lorenz Chin , David Stuart Gibson
IPC分类号： G06F1/12 , G06F13/42 , H04L5/00
CPC分类号： G11C7/1084 , G06F13/4054 , G11C7/109 , G11C7/1093 , H04L7/0045
摘要： A multiple time domain synchronizer includes a data pipeline containing a plurality of serially-connected delay elements therein. A latency selection circuit is provided, which has a plurality of inputs electrically coupled to outputs of a corresponding plurality of delay elements in the data pipeline. The latency selection circuit is configured to pass a data pipeline signal from an output of a selected one of the plurality of delay elements in response to a latency control signal. A synchronization circuit is provided, which is electrically coupled to an output of the latency selection circuit. This synchronization circuit, which includes first and second unequal timing paths therein, is responsive to a clock that synchronizes capture of the data pipeline signal selected by the latency selection circuit and a destination code that selects one of the first and second unequal timing paths to be traversed by the captured data pipeline signal as active.
摘要翻译：多时域同步器包括其中包含多个串联连接的延迟元件的数据流水线。提供了一种等待时间选择电路，其具有电耦合到数据流水线中对应的多个延迟元件的输出的多个输入。等待时间选择电路被配置为响应于等待时间控制信号而从多个延迟元件中选择的一个的输出传递数据流水线信号。提供同步电路，其电连接到等待时间选择电路的输出端。该同步电路包括其中的第一和第二不相等的定时路径，其响应于等待时间选择电路选择的数据流水线信号的捕获与选择第一和第二不等时序路径之一的目的地代码的时钟被捕获的数据流水线信号遍历为活动状态。

4. 发明授权

US08742854B1 Periodic signal generators having microelectromechanical resonators therein that support generation of high frequency low-TCF difference signals 有权
标题翻译：其中具有支持产生高频低TCF差分信号的微机电谐振器的周期信号发生器
公开(公告)号：US08742854B1
公开(公告)日：2014-06-03
申请号：US13186332
申请日：2011-07-19
申请人： Seungbae Lee , Harmeet Bhugra , Ashwin Samarao
发明人： Seungbae Lee , Harmeet Bhugra , Ashwin Samarao
IPC分类号： H03B21/01 , H03B5/30
CPC分类号： H03H9/02448 , H03H9/02259 , H03H9/2405 , H03H9/2463 , H03H2009/0244 , H03H2009/02496 , H03H2009/2415
摘要： A periodic signal generator is configured to generate high frequency signals characterized by relatively low temperature coefficients of frequency (TCF). A microelectromechanical resonator, such as concave bulk acoustic resonator (CBAR) supporting capacitive and piezoelectric transduction, may be geometrically engineered as a signal generator that produces two periodic signals having unequal resonant frequencies with unequal temperature coefficients. Circuitry is also provided for combining the two periodic signals using a mixer to thereby yield a high frequency low-TCF periodic difference signal at an output of the periodic signal generator.
摘要翻译：周期性信号发生器被配置为产生由频率相对较低的温度系数（TCF）表征的高频信号。支持电容和压电转换的诸如凹体积声共振器（CBAR）的微电子机械谐振器可以被几何地设计为信号发生器，其产生具有不等于具有不等温度系数的不等谐振频率的两个周期信号。还提供电路用于使用混频器组合两个周期信号，从而在周期信号发生器的输出处产生高频低TCF周期性差分信号。

5. 发明授权

US08559587B1 Fractional-N dividers having divider modulation circuits therein with segmented accumulators 有权
标题翻译：分数N分频器，其中具有分段累加器的分频器调制电路
公开(公告)号：US08559587B1
公开(公告)日：2013-10-15
申请号：US13425761
申请日：2012-03-21
申请人： Brian Buell , Benedykt Mika , Chen-Wei Huang
发明人： Brian Buell , Benedykt Mika , Chen-Wei Huang
IPC分类号： H03K21/00
CPC分类号： H03K23/662 , H03K23/68
摘要： Fractional-N divider circuits include a multi-modulus divider, which is configured to perform at least /N and /N+1 frequency division of a first reference signal received at a first input thereof. This division is performed in response to an overflow signal received at a second input thereof, where N is an integer greater than one. A phase correction circuit is configured to generate a second reference signal in response to a divider output signal generated by the multi-modulus divider. A divider modulation circuit is provided, which is configured to generate the overflow signal in response to a code that specifies a plurality of division moduli to be used by the multi-modulus divider. The divider modulation circuit includes a segmented accumulator, which is configured to generate a plurality of segments of a count value having at least one period of latency therebetween.
摘要翻译：分数N分频器电路包括多模式分频器，其被配置为对在其第一输入处接收的第一参考信号执行至少/ N和/ N + 1分频。响应于在其第二输入处接收的溢出信号执行该除法，其中N是大于1的整数。相位校正电路被配置为响应于由多模式分频器产生的分频器输出信号而产生第二参考信号。提供了一种分频器调制电路，其被配置为响应于指定由多模式分频器使用的多个分频模块的代码产生溢出信号。分频器调制电路包括分段累加器，其被配置为生成具有至少一个等待时间段的计数值的多个段。

6. 发明授权

US07825777B1 Packet processors having comparators therein that determine non-strict inequalities between applied operands 有权
标题翻译：其中具有比较器的分组处理器确定应用操作数之间的非严格不等式
公开(公告)号：US07825777B1
公开(公告)日：2010-11-02
申请号：US11393489
申请日：2006-03-30
申请人： Tingjun Wen , David Walter Carr , Tadeusz Kwasniewski
发明人： Tingjun Wen , David Walter Carr , Tadeusz Kwasniewski
IPC分类号： G05B1/00 , H03K19/20 , H03K19/094 , G06F7/00
CPC分类号： G06F7/026
摘要： An integrated circuit comparator is provided that determines non-strict inequalities between operands applied thereto. Each comparator includes at least one n-bit comparator cell. This comparator cell is configured to determine a non-strict inequality between a first n-bit operand (e.g., A[n−1, . . . , 0]) and a second n-bit operand (e.g., B[n−1, . . . , 0]). The comparator cell determines the non-strict inequality by computing a control output signal Co (or its complement), where: C o = ( … ⁡ ( ( C i ⁡ ( A 0 + B 0 _ ) + A 0 ⁢ B 0 _ ) ⁢ ( A 1 + B 1 _ ) + A 1 ⁢ B 1 _ ) ⁢ … ⁡ ( A n - 2 + B n - 2 _ ) + A n - 2 ⁢ B n - 2 _ ) ⁢ ( A n - 1 + B n - 1 _ ) + A n - 1 ⁢ B n - 1 _ , “n” is a positive integer greater than one and Ci is a control input signal that specifies an interpretation to be given to the control output signal Co.
摘要翻译：提供集成电路比较器，其确定施加到其上的操作数之间的非严格不等式。每个比较器包括至少一个n位比较器单元。该比较器单元被配置为确定第一n位操作数（例如，A [n-1，...，0]）和第二n位操作数之间的非严格不等式（例如，B [n-1 ，...，0]）。比较器单元通过计算控制输出信号Co（或其补码）来确定非严格不等式，其中：C o =（...⁡（（C 0⁡（A 0 + B 0 _）+ A 0 B 0 _ ）（A 1 + B 1 _）+ A 1 B 1 _）...⁡（A n-2 + B n-2 _）+ A n-2 B n-2 _）（A n- 1 + B n - 1 _）+ A n - 1 B n - 1 _，“n”是大于1的正整数，Ci是指定给予控制输出信号Co的解释的控制输入信号。

7. 发明授权

US09236873B1 Fractional divider based phase locked loops with digital noise cancellation 有权
标题翻译：具有数字噪声消除的基于分数分频器的锁相环
公开(公告)号：US09236873B1
公开(公告)日：2016-01-12
申请号：US14573146
申请日：2014-12-17
申请人： Integrated Device Technology, Inc.
发明人： Brian Buell
IPC分类号： H03L7/06 , H03L7/099 , H03L7/093
CPC分类号： H03L7/0992 , H03K21/02 , H03K23/68 , H03L7/0802 , H03L7/085 , H03L7/093 , H03L7/18 , H03L7/1806 , H03L7/193 , H03L7/1974 , H03L7/1976 , H03L2207/50
摘要： A PLL includes a fractional divider to generate a periodic PLL output signal in response to REFHF. The fractional divider includes a digital control circuit (DDC) responsive to a digital control input signal and a multi-modulus divider (MMD), which is responsive to REFHF and a first digital control output signal generated by the DDC. A feedback divider (FD) is provided to generate a FD output signal in response to an MMD output signal generated by the MMD. A phase detector (PD) is provided to generate a PD output signal in response to the FD output signal and REF_CLK. A loop filter is provided to generate the digital control input signal in response to the PD output signal as modified by a noise cancellation signal (NCS). The NCS is generated to at least partially compensate for non-random deterministic noise in the MMD output signal.
摘要翻译： PLL包括分数分频器，以响应于REFHF产生周期性PLL输出信号。小数分频器包括响应于数字控制输入信号的数字控制电路（DDC）和响应于REFHF的多模除法器（MMD）和由DDC产生的第一数字控制输出信号。提供反馈分频器（FD）以响应由MMD产生的MMD输出信号而产生FD输出信号。提供相位检测器（PD）以响应于FD输出信号和REF_CLK产生PD输出信号。提供环路滤波器以响应由噪声消除信号（NCS）修改的PD输出信号来产生数字控制输入信号。产生NCS以至少部分补偿MMD输出信号中的非随机确定性噪声。

8. 发明授权

US09118333B1 Self-adaptive multi-modulus dividers containing div2/3 cells therein 有权
标题翻译：在其中包含div2 / 3单元的自适应多模式分频器
公开(公告)号：US09118333B1
公开(公告)日：2015-08-25
申请号：US14013599
申请日：2013-08-29
申请人： Integrated Device Technology, Inc.
发明人： Benedykt Mika , Pengfei Hu
IPC分类号： H03K21/00 , H03K23/00 , H03K23/70 , H03K23/68 , H03K23/66
CPC分类号： H03K23/70 , H03K21/00 , H03K21/023 , H03K21/38 , H03K23/00 , H03K23/667 , H03K23/68
摘要： Integrated circuit devices include programmable dividers, such as fractional-N dividers, which can utilize multi-modulus dividers (MMD) therein. A multi-modulus divider includes a cascaded chain of div2/3 cells configured to support a chain length control operation that precludes generation of an intermediate divisor in response to a change in value of a chain length control byte P during an update time interval and may even fully turn off one or more of the div2/3 cells not participating in a divide-by-N operation, where N is a positive integer greater than one. The div2/3 cells are configured to include a modulus input terminal and a modulus output terminal and the chain length control operation is independent of the magnitude of the signals provided to the modulus input terminals of the div2/3 cells.
摘要翻译：集成电路设备包括可以使用其中的多模式分频器（MMD）的可编程分频器，例如分数N分频器。多模式分配器包括一个分级链div2 / 3单元，其被配置为支持链长控制操作，该操作排除在响应于链长度控制字节P 的值的变化期间产生中间除数更新时间间隔，甚至可以完全关闭不参与除N运算的一个或多个div2 / 3单元，其中N是大于1的正整数。 div2 / 3单元被配置为包括模数输入端和模输出端，并且链长控制操作与提供给div2 / 3单元的模输入端的信号的幅度无关。

9. 发明授权

US09090451B1 Microelectromechanical resonators having offset [100] and [110] crystal orientations 有权
标题翻译：具有偏移[100]和[110]晶体取向的微机电谐振器
公开(公告)号：US09090451B1
公开(公告)日：2015-07-28
申请号：US13837854
申请日：2013-03-15
申请人： Integrated Device Technology, Inc.
发明人： Wanling Pan , Harmeet Bhugra , Maryam Ziaei-Moayyed
IPC分类号： H03B5/32 , H01L41/08 , B81B3/00 , H01L41/083
CPC分类号： B81B3/0021 , H01L41/083 , H03B21/01 , H03H9/02228 , H03H9/02448 , H03H2009/241
摘要： A TPoS resonator includes a substrate and a resonator body suspended over the substrate by at least a first pair of fixed supports (e.g., tethers) that attach to first and second ends of the resonator body. The resonator body includes monocrystalline silicon, which has a [100] crystallographic orientation that is offset by ±α degrees relative to a nodal line of the resonator body (e.g., tether-to-tether axis) when the resonator body is operating at a resonant frequency, where a is a real number in a range from about 5 to about 19 and, more preferably, in a range from about 7 to about 17. The resonator may be an extensional-mode resonator and the resonator body may be rectangular-shaped with unequal length and width dimensions.
摘要翻译： TPoS谐振器包括衬底和谐振器体，所述谐振器体通过附接到谐振器本体的第一和第二端的至少第一对固定支撑件（例如系绳）悬挂在衬底上。谐振器主体包括单晶硅，当谐振器主体以谐振器工作时，其具有相对于谐振器主体的节点线（例如，系绳至系绳轴线）偏移±α度的[100]晶体取向频率，其中a是在约5至约19的范围内的实数，更优选在约7至约17的范围内。谐振器可以是延伸模式谐振器，并且谐振器体可以是矩形具有不等长度和宽度尺寸。

10. 发明授权

US09000853B1 Packaged MEMS-based oscillator circuits that support frequency margining and methods of operating same 有权
标题翻译：封装的基于MEMS的振荡器电路，支持频率裕度和操作方法
公开(公告)号：US09000853B1
公开(公告)日：2015-04-07
申请号：US13849999
申请日：2013-03-25
申请人： Integrated Device Technology, Inc.
发明人： Nelson Arata , Harmeet Bhugra
IPC分类号： H03B5/30 , H03L7/16 , H03B5/18
CPC分类号： H03B5/1852 , H03B5/30 , H03L7/197
摘要： Integrated circuit devices include a packaged MEMS-based oscillator circuit, which is configured to support bidirectional frequency margining of a periodic output signal. This bidirectional frequency margining is achieved using a first signal to synchronize changes in a frequency of the periodic output signal and a second signal to control whether the changes in the frequency of the periodic output signal are incremental or decremental. In particular, the oscillator circuit may be configured so that each change in the frequency of the periodic output signal is synchronized to a corresponding first voltage transition of the first signal and a voltage level of the second signal may be used to control whether the changes in the frequency of the periodic output signal are incremental or decremental.
摘要翻译：集成电路器件包括封装的基于MEMS的振荡器电路，其被配置为支持周期性输出信号的双向频率裕度。使用第一信号来实现该双向频率裕度，以使周期性输出信号的频率的变化同步第二信号，以控制周期性输出信号的频率的变化是递增的还是递减的。特别地，振荡器电路可以被配置为使得周期性输出信号的频率的每个变化被同步到第一信号的对应的第一电压转换，并且第二信号的电压电平可以用于控制是否改变周期性输出信号的频率是递增或递减的。

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