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1. 发明授权

US10417339B2 Suggestion of alternate user input using different user interface 有权
公开(公告)号：US10417339B2
公开(公告)日：2019-09-17
申请号：US15681069
申请日：2017-08-18
申请人： KYOCERA Document Solutions Inc.
发明人： Allan Sahagun
IPC分类号： G06F17/27 , G06F3/0488
摘要： Method(s) and apparatus(es) relating generally to an electronic device having a display and a touch-sensitive input device are disclosed. In such a method, a first keypad is displayed on the display. Obtained is sensed information from the touch-sensitive input device responsive to user input in association with the first keypad. The user input is determined to be for a second keypad different from the first keypad. A corresponding input to the user input is determined using the sensed information in association with the second keypad. The corresponding input is displayed on the display.

2. 发明授权

US08804792B1 Intermediary signal conditioning device with interruptible detection mode 有权
标题翻译：具有可中断检测模式的中间信号调理装置
公开(公告)号：US08804792B1
公开(公告)日：2014-08-12
申请号：US13766647
申请日：2013-02-13
申请人： Pericom Semiconductor
发明人： Hung-Yan Cheung , Michael Yimin Zhang
IPC分类号： H04L25/00
CPC分类号： H04L25/20 , H04L25/03885
摘要： Disclosed are embodiments for an intermediary signal conditioning device with an input adaptable detection mode. In one embodiment, an intermediary signal conditioning device has a control module, an input module, and an output module. The input module and the control module are for receiving an input signal. The control module is configured to interrupt the output module within a duration of time to allow at least a minimum pulse length of the input signal to be output as an output signal from the output module. The intermediary signal conditioning device is configured to condition the input signal for retransmission as the output signal.
摘要翻译：公开了具有输入适应性检测模式的中间信号调节装置的实施例。在一个实施例中，中间信号调节装置具有控制模块，输入模块和输出模块。输入模块和控制模块用于接收输入信号。控制模块被配置为在一段持续时间内中断输出模块，以允许将输入信号的至少最小脉冲长度输出为来自输出模块的输出信号。中间信号调节装置被配置为将用于重传的输入信号调节为输出信号。

3. 发明授权

US08174046B1 Reducing effects of parasitic transistors in thyristor-based memory using local thinning or implanting 失效
标题翻译：使用局部变薄或植入，减少寄生晶体管在基于晶闸管的存储器中的影响
公开(公告)号：US08174046B1
公开(公告)日：2012-05-08
申请号：US11362285
申请日：2006-02-23
申请人： Marc Laurent Tarabbia , Maxim Ershov , Rajesh N. Gupta
发明人： Marc Laurent Tarabbia , Maxim Ershov , Rajesh N. Gupta
IPC分类号： H01L29/74
CPC分类号： H01L29/66393 , H01L27/1027 , H01L27/105 , H01L29/7436
摘要： Method and apparatus for an integrated circuit having memory including thyristor-based memory cells is described. A pair of the thyristor-based memory cells are commonly coupled via a bitline region, where a parasitic bipolar junction transistor is defined therebetween responsive to the bitline region being common. In another implementation, the pair of the thyristor-based memory cells are commonly coupled via the anode region, where a parasitic bipolar junction transistor is defined therebetween responsive to the anode region being common. The common bitline or anode region, respectively, has a locally thinned region to inhibit charge transfer between the pair via the parasitic bipolar junction transistor. Moreover, a method for forming a field-effect transistor on a silicon-on-insulator wafer is described, where charge transfer facilitated by a parasitic bipolar transistor is reduced responsive to an increase in dopants at least proximate to an insulator layer.
摘要翻译：描述了具有包括基于晶闸管的存储器单元的存储器的集成电路的方法和装置。一对基于晶闸管的存储单元通常经由位线区域耦合，其中响应于位线区域是共同的，限定了寄生双极结型晶体管。在另一个实施方案中，一对基于晶闸管的存储单元通常经由阳极区耦合，其中响应于阳极区域是共同的，限定了寄生双极结型晶体管。公共位线或阳极区域分别具有局部变薄的区域，以通过寄生双极结型晶体管抑制该对之间的电荷转移。此外，描述了在绝缘体上硅晶片上形成场效应晶体管的方法，其中响应于至少接近绝缘体层的掺杂剂的增加，由寄生双极晶体管促进电荷转移。

4. 发明授权

US07969777B1 Thyristor-based memory array having lines with standby voltages 失效
标题翻译：具有备用电压线路的基于晶闸管的存储器阵列
公开(公告)号：US07969777B1
公开(公告)日：2011-06-28
申请号：US12326027
申请日：2008-12-01
申请人： Hyun-Jin Cho , Farid Nemati
发明人： Hyun-Jin Cho , Farid Nemati
IPC分类号： G11C11/39
CPC分类号： G11C11/39
摘要： A new memory cell can contain only a single thyristor. There is no need to include an access transistor in the cell. In one embodiment, the thyristor is a thin capacitively coupled thyristor. The new memory cell can be connected to word, bit, and control lines in several ways to form different memory arrays. Timing and voltage levels of word, bit and control lines are disclosed.
摘要翻译：新的存储单元只能包含一个晶闸管。不需要在电池中包括存取晶体管。在一个实施例中，晶闸管是薄电容耦合晶闸管。新的存储单元可以以多种方式连接到字，位和控制线，以形成不同的存储器阵列。公开了字，位和控制线的时序和电压电平。

5. 发明授权

US07915923B1 Serial link driver interface for a communication system 有权
标题翻译：用于通信系统的串行链路驱动程序接口
公开(公告)号：US07915923B1
公开(公告)日：2011-03-29
申请号：US12400708
申请日：2009-03-09
申请人： Tony Yeung , Michael Yimin Zhang
发明人： Tony Yeung , Michael Yimin Zhang
IPC分类号： H03K19/0175
CPC分类号： H04L25/0264
摘要： Method and apparatus for a communication system (100) using a driver block (200) are described. The driver block includes memory having programmable non-volatile memory cells for storing configuration settings associated with operation of the driver block (200). The driver block (200) is programmable for a selected interface protocol for operation in an adaptive equalization mode to obtain an adaptive equalization value. The adaptive equalization value is stored as a fixed equalization value for operating the driver block in a fixed equalization mode. The driver block may be used as a serial link driver interface.
摘要翻译：描述使用驱动块（200）的通信系统（100）的方法和装置。驱动器块包括具有用于存储与驱动器块（200）的操作相关联的配置设置的可编程非易失性存储器单元的存储器。驱动器块（200）可编程为用于在自适应均衡模式下操作的选定接口协议以获得自适应均衡值。自适应均衡值被存储为用于以固定均衡模式操作驱动器块的固定均衡值。驱动程序块可以用作串行链路驱动程序接口。

6. 发明授权

US07859929B1 Sense amplifiers 失效
标题翻译：感应放大器
公开(公告)号：US07859929B1
公开(公告)日：2010-12-28
申请号：US12422152
申请日：2009-04-10
申请人： Richard Roy
发明人： Richard Roy
IPC分类号： G11C7/02
CPC分类号： G11C7/065 , G11C11/39
摘要： Sense logic, and associated signaling, for dynamic thyristor-based memory cells is described. A first supply voltage level is greater than a second supply voltage level. In an embodiment, cross-coupled inverters of a sense amplifier are operatively coupled between a ground node and the second supply for sensing voltage. The first supply voltage is pass gate coupled to a first sense node and a second sense node. The pass gating is responsive to sample signaling. A first supply transistor is gated by a transfer bus. A second supply transistor is gated by a sense reference voltage that is between the first supply voltage level and the second supply voltage level. Each of the first supply transistor and the second supply transistor is back body biased with a write voltage level that is between the second supply voltage level and the ground voltage level.
摘要翻译：描述了用于基于动态可控硅的存储器单元的检测逻辑和相关联的信号。第一电源电压电平大于第二电源电压电平。在一个实施例中，读出放大器的交叉耦合反相器可操作地耦合在接地节点和第二电源之间以感测电压。第一电源电压是通过栅极耦合到第一感测节点和第二感测节点。通过门控对样本信号进行响应。第一电源晶体管由传输总线门控。第二电源晶体管由位于第一电源电压电平和第二电源电压电平之间的感测参考电压门控。第一电源晶体管和第二电源晶体管中的每一个都以在第二电源电压电平和接地电压电平之间的写入电压电平进行背部主体偏置。

7. 发明授权

US07804107B1 Thyristor semiconductor device and method of manufacture 失效
标题翻译：晶闸管半导体器件及其制造方法
公开(公告)号：US07804107B1
公开(公告)日：2010-09-28
申请号：US11906619
申请日：2007-10-03
申请人： Andrew E. Horch , Fred Hause
发明人： Andrew E. Horch , Fred Hause
IPC分类号： H01L31/111
CPC分类号： H01L21/84 , H01L21/823814 , H01L21/823835 , H01L27/1027 , H01L27/1203 , H01L29/66378
摘要： In a method of processing a semiconductor device, a silicide-blocking layer may be formed over a semiconductor material. After defining the silicide-blocking layer, impurities may be implanted into portions of the semiconductor material as defined by the silicide-blocking layer. After the implant, silicide may be formed in a surface region of the semiconductor material as permitted by the silicide-blocking layer. Regions of the impurity implant may comprise boundaries that are related to the outline of the silicide formed thereover. In a further embodiment, the implant may define a base region to a thyristor device. The implant may be performed with an angle of incidence to extend portions of the base region beneath a peripheral edge of the blocking mask. Next, an anode-emitter region may be formed using an implant of a substantially orthogonal angle of incidence and self-aligned to the mask. Epitaxial material may then be formed selectively over exposed regions of the semiconductor material as defined by the silicide-blocking mask. Silicide might also be formed after select exposed regions as defined by the silicide-blocking mask. The silicide-blocking mask may thus be used for alignment of implants, and also for defining epitaxial and silicide alignments.
摘要翻译：在半导体器件的处理方法中，可以在半导体材料上形成硅化物阻挡层。在限定硅化物阻挡层之后，可以将杂质注入半导体材料的部分，如由硅化物阻挡层所限定的。在植入之后，硅化物可以形成在半导体材料的表面区域，如硅化物阻挡层所允许的。杂质植入物的区域可以包括与其上形成的硅化物的轮廓相关的边界。在另一实施例中，植入物可以限定到晶闸管器件的基极区域。可以以入射角来执行植入物，以将阻挡掩模的外围边缘下方的基底区域的部分延伸。接下来，可以使用基本上正交的入射角并与掩模自对准的植入物形成阳极 - 发射极区域。然后可以在由硅化物阻挡掩模限定的半导体材料的暴露区域上选择性地形成外延材料。也可以在由硅化物阻挡掩模定义的选择的暴露区域之后形成硅化物。硅化物阻挡掩模因此可用于植入物的对准，并且还用于限定外延和硅化物对准。

8. 发明授权

US07464282B1 Apparatus and method for producing dummy data and output clock generator using same 失效
标题翻译：用于产生伪数据的装置和方法以及使用其的输出时钟发生器
公开(公告)号：US07464282B1
公开(公告)日：2008-12-09
申请号：US10654322
申请日：2003-09-03
申请人： Shahram Abdollahi-Alibeik , Chaofeng Huang
发明人： Shahram Abdollahi-Alibeik , Chaofeng Huang
IPC分类号： G06F1/12
CPC分类号： G11C7/22 , G11C7/222 , G11C2207/2254 , H03L7/0814
摘要： An apparatus and method for producing dummy data is based on timing paths co-located with the address/data paths of the memory. An output clock generator uses the dummy data. The technique for producing dummy data is particularly important for memory systems in which the output of memory cells do not normally provide large voltage swings, making them less practical for self timing approaches to dummy data generation.
摘要翻译：用于产生伪数据的装置和方法基于与存储器的地址/数据路径共同定位的定时路径。输出时钟发生器使用虚拟数据。用于产生虚拟数据的技术对于其中存储器单元的输出通常不提供大的电压摆动的存储器系统是特别重要的，使得它们对于伪数据生成的自定时方法不太实用。

9. 发明授权

US10378884B1 Fiber optic voltage conditioning 有权
公开(公告)号：US10378884B1
公开(公告)日：2019-08-13
申请号：US16017737
申请日：2018-06-25
申请人： iSenseCloud, Inc.
发明人： An-Dien Nguyen , An H. Nguyen
IPC分类号： H01S5/0687 , G01B11/16 , H01S5/062 , H01S5/06 , H01S5/0683
摘要： A fiber optic voltage conditioner, and method therefor, generally relate to voltage conditioning. In such a fiber optic voltage conditioner, there is a laser, and an optical circulator is coupled to receive a light signal from the laser. A controller is coupled to the laser and is configured to generate first control information for wavelength-drift control of the laser. A data acquisition module is coupled to the controller and is configured to generate second control information for the controller for adjustment of the first control information. A photodetector is coupled to the optical circulator to receive a returned optical signal and is coupled to the data acquisition module to provide an analog output signal thereto. The photodetector is configured to generate the analog output signal responsive to the returned optical signal. The data acquisition module is configured to generate the second control information using the analog output signal.

10. 发明授权

US10209060B1 Fiber-optic sensors in a rosette or rosette-like pattern for structure monitoring 有权
公开(公告)号：US10209060B1
公开(公告)日：2019-02-19
申请号：US15458311
申请日：2017-03-14
申请人： iSenseCloud, Inc.
发明人： An-Dien Nguyen
IPC分类号： G01B11/16
摘要： An apparatus, and related method, relates generally to a fiber-optic sensing system. In such a system, fiber-optic sensors are in a rosette or rosette-like pattern. An optical circulator is coupled to receive a light signal from a broadband light source, to provide the light signal to the fiber-optic sensors, and to receive a returned optical signal from the fiber-optic sensors. A spectral engine is coupled to the optical circulator to receive the returned optical signal and configured to provide an output signal.

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