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1. 发明授权

US08941094B2 Methods for adjusting the conductivity range of a nanotube fabric layer 有权
标题翻译：调整纳米管织物层电导率范围的方法
公开(公告)号：US08941094B2
公开(公告)日：2015-01-27
申请号：US12874501
申请日：2010-09-02
申请人： C. Rinn Cleavelin , Thomas Rueckes , H. Montgomery Manning , Darlene Hamilton , Feng Gu
发明人： C. Rinn Cleavelin , Thomas Rueckes , H. Montgomery Manning , Darlene Hamilton , Feng Gu
IPC分类号： H01L45/00 , B82Y30/00 , B82Y40/00 , H01B1/24 , H01L29/78 , H01L51/00 , H01L51/44
CPC分类号： H01L45/149 , B82Y10/00 , B82Y30/00 , B82Y40/00 , H01B1/24 , H01L29/78 , H01L51/0015 , H01L51/0048 , H01L51/444 , Y02E10/549
摘要： Methods for adjusting and/or limiting the conductivity range of a nanotube fabric layer are disclosed. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via wet chemistry techniques. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via plasma treatment. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via CVD treatment. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via an inert ion gas implant.
摘要翻译：公开了调整和/或限制纳米管织物层的电导率范围的方法。在一些方面，通过湿法化学技术使织物层内的纳米管元件功能化来调节纳米管织物层的导电性。在一些方面，通过等离子体处理使织物层内的纳米管元件功能化来调节纳米管织物层的导电性。在一些方面，通过CVD处理使织物层内的纳米管元件功能化来调节纳米管织物层的导电性。在一些方面，纳米管织物层的导电性通过惰性离子注入物官能化织物层内的纳米管元件来调节。

2. 发明申请

US20120175710A1 INTEGRATED CIRCUITS WITH ALIGNED (100) NMOS AND (110) PMOS FINFET SIDEWALL CHANNELS 有权
标题翻译：具有对准（100）NMOS和（110）PMOS FinFET平台通道的集成电路
公开(公告)号：US20120175710A1
公开(公告)日：2012-07-12
申请号：US13425082
申请日：2012-03-20
申请人： Weize Xiong , Cloves Rinn Cleavelin , Angelo Pinto , Rick L. Wise
发明人： Weize Xiong , Cloves Rinn Cleavelin , Angelo Pinto , Rick L. Wise
IPC分类号： H01L27/092
CPC分类号： H01L27/0886 , G11C11/412 , H01L21/823807 , H01L21/823821 , H01L27/0207 , H01L27/092 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L29/045 , Y10S257/90 , Y10S438/973 , Y10S438/982
摘要： An integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS MuGFETs are formed through amorphization and crystal regrowth on a direct silicon bonded (DSB) hybrid orientation technology (HOT) substrate. PMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (110) crystal orientations. NMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (100) crystal orientations in a Manhattan layout with the sidewall channels of the different PMOS and NMOS MuGFETs aligned at 0° or 90° rotations.
摘要翻译：公开了一种包括多个多栅极FinFET（MuGFET）的集成电路器件。通过在直接硅键合（DSB）混合取向技术（HOT）衬底上的非晶化和晶体再生长形成用于PMOS和NMOS MuGFET的不同晶体取向的晶片。 PMOS MuGFET翅片由具有（110）晶体取向的翅片侧壁表面限定的通道形成。 NMOS MuGFET翅片由曼哈顿布局具有（100）晶体取向的翅片侧壁表面限定的通道形成，其中不同PMOS和NMOS MuGFET的侧壁通道以0°或90°旋转对准。

3. 发明申请

US20120056149A1 METHODS FOR ADJUSTING THE CONDUCTIVITY RANGE OF A NANOTUBE FABRIC LAYER 有权
标题翻译：调整纳米纤维层电导率范围的方法
公开(公告)号：US20120056149A1
公开(公告)日：2012-03-08
申请号：US12874501
申请日：2010-09-02
申请人： C. Rinn CLEAVELIN , Thomas RUECKES , H. Montgomery MANNING , Darlene HAMILTON , Feng GU
发明人： C. Rinn CLEAVELIN , Thomas RUECKES , H. Montgomery MANNING , Darlene HAMILTON , Feng GU
IPC分类号： H01L45/00 , H01L21/04 , B82Y40/00 , B82Y30/00
CPC分类号： H01L45/149 , B82Y10/00 , B82Y30/00 , B82Y40/00 , H01B1/24 , H01L29/78 , H01L51/0015 , H01L51/0048 , H01L51/444 , Y02E10/549
摘要： Methods for adjusting and/or limiting the conductivity range of a nanotube fabric layer are disclosed. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via wet chemistry techniques. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via plasma treatment. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via CVD treatment. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via an inert ion gas implant.
摘要翻译：公开了调整和/或限制纳米管织物层的电导率范围的方法。在一些方面，通过湿法化学技术使织物层内的纳米管元件功能化来调节纳米管织物层的导电性。在一些方面，通过等离子体处理使织物层内的纳米管元件功能化来调节纳米管织物层的导电性。在一些方面，通过CVD处理使织物层内的纳米管元件功能化来调节纳米管织物层的导电性。在一些方面，纳米管织物层的导电性通过惰性离子注入物官能化织物层内的纳米管元件来调节。

4. 发明授权

US07122442B2 Method and system for dopant containment 有权
公开(公告)号：US07122442B2
公开(公告)日：2006-10-17
申请号：US10897634
申请日：2004-07-22
申请人： Cloves Rinn Cleavelin
发明人： Cloves Rinn Cleavelin
IPC分类号： H01L21/76
CPC分类号： H01L21/26506 , H01L21/76254 , H01L29/7833
摘要： According to one embodiment, a semiconductor device is provided. The semiconductor device includes an oxide layer. The semiconductor device also includes a silicon layer disposed outwardly from the oxide layer and having at least one region comprising a dopant. The semiconductor device also includes a dielectric layer disposed outwardly from the silicon layer. The semiconductor device also includes a gate disposed outwardly from the dielectric layer. The semiconductor device also includes a blocking layer disposed between the oxide layer and the silicon layer. The blocking layer is operable to at least partially block a transfer of the dopant from the at least one region of the silicon layer to the oxide layer.

5. 发明授权

US06246787B1 System and method for knowledgebase generation and management 失效
标题翻译：知识库生成和管理的系统和方法
公开(公告)号：US06246787B1
公开(公告)日：2001-06-12
申请号：US08866771
申请日：1997-05-30
申请人： A. Kathleen Hennessey , YouLing Lin , Rajasekar Reddy , C. Rinn Cleavelin , Howard V. Hastings, II , Pinar Kinokoglu , Wan S. Wong
发明人： A. Kathleen Hennessey , YouLing Lin , Rajasekar Reddy , C. Rinn Cleavelin , Howard V. Hastings, II , Pinar Kinokoglu , Wan S. Wong
IPC分类号： G06K900
CPC分类号： H01L22/20 , G01N21/95607 , G06T7/001 , G06T2207/10056 , G06T2207/30148 , H01L22/12 , H01L2924/014
摘要： A method and system for generating and managing a knowledgebase for use in identifying anomalies on a manufactured object, such as a semiconductor wafer, includes measures for adding, deleting, and organizing data from the knowledgebase.
摘要翻译：用于生成和管理知识库以用于识别诸如半导体晶片的制造对象上的异常的方法和系统包括用于从知识库添加，删除和组织数据的措施。

6. 发明授权

US08000127B2 Method for resetting a resistive change memory element 有权
标题翻译：用于复位电阻变化存储元件的方法
公开(公告)号：US08000127B2
公开(公告)日：2011-08-16
申请号：US12618448
申请日：2009-11-13
申请人： Darlene Hamilton , Rinn Cleavelin
发明人： Darlene Hamilton , Rinn Cleavelin
IPC分类号： G11C11/00 , G11C17/00
CPC分类号： G11C5/06 , B82Y10/00 , G11C5/147 , G11C11/5614 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0009 , G11C13/0011 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C13/0097 , G11C13/025 , G11C2013/0076 , G11C2013/0092 , G11C2213/71 , G11C2213/79
摘要： A method of resetting a resistive change memory element is disclosed. The method comprises performing a series of programming operations—for example, a programming pulse of a predetermined voltage level and pulse width—on a resistive change memory element in order to incrementally increase the resistance of the memory element above some predefined threshold. Prior to each programming operation, the resistive state of the memory element is measured and used to determine the parameters used in that programming operation. If this measured resistance value is above a first threshold value, the memory element is determined to already be in a reset state and no further programming operation is performed. If this measured resistance value is below a second threshold value, this second threshold value being less than the first threshold value, a first set of programming parameters are used within the programming operation. If this initial value is above the second threshold value but below the first threshold value, a second set of programming parameters are used within the programming operation.
摘要翻译：公开了一种复位电阻变化存储元件的方法。该方法包括执行一系列编程操作 - 例如，电阻变化存储器元件上的预定电压电平和脉冲宽度的编程脉冲，以便将存储器元件的电阻递增地增加到高于某个预定阈值。在每个编程操作之前，测量存储元件的电阻状态并用于确定在该编程操作中使用的参数。如果该测量的电阻值高于第一阈值，则确定存储元件已经处于复位状态，并且不执行进一步的编程操作。如果该测量的电阻值低于第二阈值，该第二阈值小于第一阈值，则在编程操作中使用第一组编程参数。如果该初始值高于第二阈值但低于第一阈值，则在编程操作中使用第二组编程参数。

7. 发明授权

US07960234B2 Multiple-gate MOSFET device and associated manufacturing methods 有权
标题翻译：多栅MOSFET器件及相关制造方法
公开(公告)号：US07960234B2
公开(公告)日：2011-06-14
申请号：US11726516
申请日：2007-03-22
申请人： Craig Henry Huffman , Weize Xiong , Cloves Rinn Cleavelin
发明人： Craig Henry Huffman , Weize Xiong , Cloves Rinn Cleavelin
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L29/785 , H01L29/7853
摘要： One embodiment of the present invention relates to a method of fabricating a multi-gate transistor. During the method a second gate electrode material is selectively removed from a semiconductor structure from which the multi-gate transistor is formed, thereby exposing at least one surface of a first gate electrode material. The exposed surface of the first gate electrode material is deglazed. Subsequently, the first gate electrode material is removed. Other methods and devices are also disclosed.
摘要翻译：本发明的一个实施例涉及一种制造多栅极晶体管的方法。在该方法期间，从形成多栅极晶体管的半导体结构中选择性地去除第二栅电极材料，从而暴露第一栅电极材料的至少一个表面。第一栅电极材料的暴露表面被去角质化。随后，去除第一栅电极材料。还公开了其它方法和装置。

8. 发明授权

US07683417B2 Memory device with memory cell including MuGFET and fin capacitor 有权
标题翻译：具有存储单元的存储器件包括MuGFET和鳍式电容器
公开(公告)号：US07683417B2
公开(公告)日：2010-03-23
申请号：US11924817
申请日：2007-10-26
申请人： Weize Xiong , Andrew Marshall , Cloves Rinn Cleavelin , Howard Lee Tigelaar
发明人： Weize Xiong , Andrew Marshall , Cloves Rinn Cleavelin , Howard Lee Tigelaar
IPC分类号： H01L27/108
CPC分类号： H01L29/94 , H01L27/10805 , H01L27/10823 , H01L27/10826 , H01L27/1085 , H01L28/60 , H01L29/785 , H01L29/7855
摘要： One embodiment of the present invention relates to a memory cell. The memory cell includes a multi-gate field effect transistor associated with a first region of a semiconductor fin. The memory cell also includes a fin capacitor coupled to a drain of the multi-gate field effect transistor and associated with a second region of the semiconductor fin, where the fin capacitor has an approximately degenerate doping concentration in the second region. Other devices and methods are also disclosed.
摘要翻译：本发明的一个实施例涉及一种存储单元。存储单元包括与半导体鳍片的第一区域相关联的多栅极场效应晶体管。存储单元还包括耦合到多栅极场效应晶体管的漏极并与半导体鳍片的第二区域相关联的散热片电容器，其中散热片电容器在第二区域中具有大致简并掺杂浓度。还公开了其它装置和方法。

9. 发明申请

US20080303095A1 VARYING MUGFET WIDTH TO ADJUST DEVICE CHARACTERISTICS 审中-公开
标题翻译：改变MUGFET宽度以调整设备特性
公开(公告)号：US20080303095A1
公开(公告)日：2008-12-11
申请号：US11759710
申请日：2007-06-07
申请人： Weize Xiong , Cloves Rinn Cleavelin
发明人： Weize Xiong , Cloves Rinn Cleavelin
IPC分类号： H01L29/76 , H01L21/8234
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L2029/7857
摘要： One embodiment of the present invention relates to an integrated circuit that includes a first multi-gate transistor that has a first fin width and a first threshold voltage. The integrated circuit also includes a second multi-gate transistor that has a second fin width that is greater than the first width and a second threshold voltage that is less than the first threshold voltage. Other circuits and methods are also disclosed.
摘要翻译：本发明的一个实施例涉及一种集成电路，其包括具有第一鳍宽度和第一阈值电压的第一多栅极晶体管。集成电路还包括具有大于第一宽度的第二鳍宽度和小于第一阈值电压的第二阈值电压的第二多栅极晶体管。还公开了其它电路和方法。

10. 发明授权

US06292582B1 Method and system for identifying defects in a semiconductor 失效
标题翻译：用于识别半导体缺陷的方法和系统
公开(公告)号：US06292582B1
公开(公告)日：2001-09-18
申请号：US08867154
申请日：1997-05-30
申请人： YouLing Lin , A. Kathleen Hennessey , Ramachandra R. Katragadda , Ramakrishna Pattikonda , Rajasekar Reddy , C. Rinn Cleavelin , Howard V. Hastings, II , Wan S. Wong
发明人： YouLing Lin , A. Kathleen Hennessey , Ramachandra R. Katragadda , Ramakrishna Pattikonda , Rajasekar Reddy , C. Rinn Cleavelin , Howard V. Hastings, II , Wan S. Wong
IPC分类号： G06K900
CPC分类号： G06T7/001 , G01N21/95607 , G06T2207/10056 , G06T2207/30148 , H01L23/544 , H01L2223/54466 , H01L2223/5448 , H01L2924/0002 , H01L2924/00
摘要： A system and method allow for associating a descriptive label with an anomaly on a manufactured object, such as a semiconductor wafer. The method includes placing the manufactured device on a moveable stage; capturing and preparing a digital-pixel-based representation of the image; symbolically decomposing the digital-pixel-based representation of the image to create a primitive-based representation of the image; analyzing the primitive-based representation of the image to detect and locate the anomaly; isolating primitives associated with the anomaly; comparing the isolated primitives associated with the anomaly with primitives in a knowledge base to locate a set of primitives in the knowledge base most like the isolated primitives associated with the anomaly; and assigning a label associated with the set of primitives in the knowledge base that was most similar to the isolated primitives associated with the anomaly. Different layers of semiconductor wafer may be analyzed to determine an appropriate label for a defect.
摘要翻译：系统和方法允许将描述性标签与制造对象（例如半导体晶片）上的异常相关联。该方法包括将制造的装置放置在可移动台上; 捕获和准备图像的基于数字像素的表示; 象征性地分解图像的基于数字像素的表示以创建图像的基于图元的表示; 分析图像的基于图元的表示以检测和定位异常; 隔离与异常相关的原语; 将与异常相关联的孤立原语与知识库中的原语进行比较，以定位知识库中的一组原语，最像是与异常相关联的孤立原语; 并且在与所述异常相关联的所述孤立原语最相似的知识库中分配与所述基元集相关联的标签。可以分析不同层的半导体晶片以确定缺陷的适当标签。

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