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1. 发明授权

US07499368B2 Variable clocking read capture for double data rate memory devices 有权
标题翻译：双数据速率存储器件的可变时钟读取捕获
公开(公告)号：US07499368B2
公开(公告)日：2009-03-03
申请号：US11052371
申请日：2005-02-07
申请人： Ashwin K. Rao , Sang-Won Song
发明人： Ashwin K. Rao , Sang-Won Song
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G11C7/1066 , G11C7/222
摘要： A system comprising a first double data rate (DDR) memory device, a second DDR memory device coupled to the first DDR memory device, the second DDR memory device not using a delay locked loop (DLL) device to synchronize clock signals. The system further comprises a logic coupled to the first and second DDR memory devices. The logic is adapted to receive data from the first and second DDR memory devices by way of a single conductive pathway.
摘要翻译：一种包括第一双数据速率（DDR）存储器设备，耦合到第一DDR存储器设备的第二DDR存储器设备，不使用延迟锁定环（DLL）设备来同步时钟信号的第二DDR存储器设备的系统。该系统还包括耦合到第一和第二DDR存储器件的逻辑。该逻辑适于通过单个导电路径从第一和第二DDR存储器设备接收数据。

2. 发明授权

US5860060A Method for left/right channel self-alignment 失效
标题翻译：左/右声道自对准方法
公开(公告)号：US5860060A
公开(公告)日：1999-01-12
申请号：US850404
申请日：1997-05-02
申请人： Stephen (Hsiao Yi) Li , James (Sang-Won) Song , Paul M. Look
发明人： Stephen (Hsiao Yi) Li , James (Sang-Won) Song , Paul M. Look
IPC分类号： G11B20/00 , G11B20/18 , H04B14/04 , H04S1/00 , G11B5/00
CPC分类号： H04B14/04 , G11B20/00992 , G11B20/18 , H04S1/007
摘要： A data processing device uses a portion of random access memory 121 as an output buffer 124 for holding a portion of a stream of PCM data which is to be output to a digital to analog converter 530. D/A 530 forms a left analog channel and a right analog channel for speaker subsystems 814 and 815. The PCM data stream is stored in the output buffer so that PCM data samples which pertain to the left channel are stored at even address and PCM data samples which pertain to the right channel are stored at odd address. Control circuitry 145 monitors direct memory access (DMA) transfers which transfer PCM data samples to PCM serializer 142. By comparing the address of each DMA transfer to a left/right channel signal from the D/A, the control circuitry can verify that channel synchronization is correct. If a synchronization error is detected, an channel synchronization error correction procedure is invoked.
摘要翻译：数据处理装置使用随机存取存储器121的一部分作为输出缓冲器124，用于保持要输出到数模转换器530的PCM数据流的一部分.D / A 530形成左模拟通道，用于扬声器子系统814和815的右模拟通道。PCM数据流存储在输出缓冲器中，使得与左声道相关的PCM数据采样被存储在偶数地址处，并且将与右声道相关的PCM数据样本存储在奇地址。控制电路145监视将PCM数据样本传送到PCM串行化器142的直接存储器访问（DMA）传送。通过将每个DMA传输的地址与来自D / A的左/右声道信号进行比较，控制电路可以验证信道同步是正确的。如果检测到同步错误，则调用信道同步纠错过程。

3. 发明申请

US20080307240A1 POWER MANAGEMENT ELECTRONIC CIRCUITS, SYSTEMS, AND METHODS AND PROCESSES OF MANUFACTURE 审中-公开
标题翻译：电力管理电子电路，系统及其制造方法和工艺
公开(公告)号：US20080307240A1
公开(公告)日：2008-12-11
申请号：US11760263
申请日：2007-06-08
申请人： Franck Dahan , Gilles Dubost , Gordon Gammie , Uming Ko , Hugh Mair , Sang-Won Song , Alice Wang , William D. Wilson
发明人： Franck Dahan , Gilles Dubost , Gordon Gammie , Uming Ko , Hugh Mair , Sang-Won Song , Alice Wang , William D. Wilson
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/06 , G06F1/08 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F21/79 , Y02D10/126 , Y02D10/128 , Y02D10/172 , Y02D50/20
摘要： An electronic circuit including a power managed circuit (2610), and a power management control circuit (3570) coupled to the power managed circuit (2610) and operable to select between at least a first operating performance point (OPP1) and a second higher operating performance point (OPP2) for the power managed circuit (2610), each performance point including a respective pair (Vn, Fn) of voltage and operating frequency, and the power management control circuit (3570) further operable to control dynamic power switching of the power managed circuit (2610) based on a condition wherein the power managed circuit (2610) at a given operating performance point has a static power dissipation (4820.1), and the dynamic power switching puts the power managed circuit in a lower static power state (4860.1) that dissipates less power than the static power dissipation (4820.1).
摘要翻译：一种电子电路，包括功率管理电路（2610）和耦合到功率管理电路（2610）的功率管理控制电路（3570），并且可操作以在至少第一操作性能点（OPP1）和第二较高操作功率管理电路（2610）的性能点（OPP2），每个性能点包括电压和工作频率的相应对（Vn，Fn），并且功率管理控制电路（3570）还可操作以控制功率管理电路功率管理电路（2610），其中在给定操作性能点处的功率管理电路（2610）具有静态功耗（4820.1），并且动态功率开关将功率管理电路置于较低的静态功率状态 4860.1），功耗比静态功耗（4820.1）要低。

4. 发明申请

US20060026530A1 DMA overlay addressing methodology for optimizing power and improving memory bandwidth for display engines 审中-公开
标题翻译： DMA覆盖寻址方法，用于优化功能并提高显示引擎的内存带宽
公开(公告)号：US20060026530A1
公开(公告)日：2006-02-02
申请号：US10903752
申请日：2004-07-30
申请人： Thomas Shepherd , Nishanth Rajan , Sang-Won Song , Moslema Sharif
发明人： Thomas Shepherd , Nishanth Rajan , Sang-Won Song , Moslema Sharif
IPC分类号： G06F17/00
CPC分类号： G09G5/397 , G09G5/14 , G09G5/395 , G09G2340/125
摘要： A method, comprising determining parameters for a first window and a second window on a display screen, said first window superimposed in front of the second window. The method further comprises determining which areas of the second window are not superimposed by the first window and dividing the areas into multiple portions, each portion abutting a separate side of the first window. For each of the portions, the method comprises fetching pixel data from a memory using an addressing mode suitable for said portion and displaying said pixel data on the display screen.
摘要翻译：一种方法，包括在显示屏幕上确定第一窗口和第二窗口的参数，所述第一窗口叠加在第二窗口的前面。该方法还包括确定第二窗口的哪些区域不被第一窗口叠加并且将区域划分成多个部分，每个部分邻接第一窗口的分开的一侧。对于每个部分，该方法包括使用适合于所述部分的寻址模式从存储器中取出像素数据，并在显示屏幕上显示所述像素数据。

5. 发明授权

US5500813A Circuit for adding multiple-bit binary numbers 失效
标题翻译：添加多位二进制数的电路
公开(公告)号：US5500813A
公开(公告)日：1996-03-19
申请号：US63785
申请日：1993-05-20
申请人： Sang-won Song , Chan-sik Kim
发明人： Sang-won Song , Chan-sik Kim
IPC分类号： G06F7/50 , G06F7/508
CPC分类号： G06F7/508 , G06F2207/4816 , G06F2207/5063
摘要： An adder includes carry generation & propagation circuits, a carry evaluation circuit and a final sum circuit, wherein the carry generation & propagation circuit and the sum circuit are composed of transmission gates, and the operation can be carried out having a reduced number of stages, thereby decreasing layout area and increasing speed.
摘要翻译：加法器包括进位产生和传播电路，进位评估电路和最终求和电路，其中进位产生和传播电路和和电路由传输门组成，并且可以执行具有减少的级数的操作，从而减少布局面积和增加速度。

6. 发明申请

US20060176759A1 Variable clocking read capture for double data rate memory devices 有权
公开(公告)号：US20060176759A1
公开(公告)日：2006-08-10
申请号：US11052371
申请日：2005-02-07
申请人： Ashwin Rao , Sang-Won Song
发明人： Ashwin Rao , Sang-Won Song
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G11C7/1066 , G11C7/222
摘要： A system comprising a first double data rate (DDR) memory device, a second DDR memory device coupled to the first DDR memory device, the second DDR memory device not using a delay locked loop (DLL) device to synchronize clock signals. The system further comprises a logic coupled to the first and second DDR memory devices. The logic is adapted to receive data from the first and second DDR memory devices by way of a single conductive pathway.

7. 发明申请

US20060022985A1 Preemptive rendering arbitration between processor hosts and display controllers 审中-公开
标题翻译：处理器主机和显示控制器之间的优先渲染仲裁
公开(公告)号：US20060022985A1
公开(公告)日：2006-02-02
申请号：US10903750
申请日：2004-07-30
申请人： Thomas Shepherd , Minh Chau , Prabha Atluri , Sang-Won Song
发明人： Thomas Shepherd , Minh Chau , Prabha Atluri , Sang-Won Song
IPC分类号： G06F13/18 , G09G5/36
CPC分类号： G09G5/001 , G06F13/1605 , G09G5/395
摘要： A system comprises a display controller adapted to monitor a first-in, first-out module (“FIFO”) data level, a memory controller coupled to said display controller, and a memory coupled to said display controller and said memory controller. The memory controller permits the display controller to immediately access the memory when the FIFO data level drops below a pre-determined threshold level and no display panel horizontal or vertical blanking periods are in progress.
摘要翻译：系统包括适于监视先入先出模块（“FIFO”）数据电平的显示控制器，耦合到所述显示控制器的存储器控制器以及耦合到所述显示控制器和所述存储器控制器的存储器。存储器控制器允许显示控制器在FIFO数据电平降低到预定的阈值水平以下且没有显示面板的水平或垂直消隐期正在进行时立即访问存储器。

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