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1. 发明申请

US20080307240A1 POWER MANAGEMENT ELECTRONIC CIRCUITS, SYSTEMS, AND METHODS AND PROCESSES OF MANUFACTURE 审中-公开
标题翻译：电力管理电子电路，系统及其制造方法和工艺
公开(公告)号：US20080307240A1
公开(公告)日：2008-12-11
申请号：US11760263
申请日：2007-06-08
申请人： Franck Dahan , Gilles Dubost , Gordon Gammie , Uming Ko , Hugh Mair , Sang-Won Song , Alice Wang , William D. Wilson
发明人： Franck Dahan , Gilles Dubost , Gordon Gammie , Uming Ko , Hugh Mair , Sang-Won Song , Alice Wang , William D. Wilson
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/06 , G06F1/08 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F21/79 , Y02D10/126 , Y02D10/128 , Y02D10/172 , Y02D50/20
摘要： An electronic circuit including a power managed circuit (2610), and a power management control circuit (3570) coupled to the power managed circuit (2610) and operable to select between at least a first operating performance point (OPP1) and a second higher operating performance point (OPP2) for the power managed circuit (2610), each performance point including a respective pair (Vn, Fn) of voltage and operating frequency, and the power management control circuit (3570) further operable to control dynamic power switching of the power managed circuit (2610) based on a condition wherein the power managed circuit (2610) at a given operating performance point has a static power dissipation (4820.1), and the dynamic power switching puts the power managed circuit in a lower static power state (4860.1) that dissipates less power than the static power dissipation (4820.1).
摘要翻译：一种电子电路，包括功率管理电路（2610）和耦合到功率管理电路（2610）的功率管理控制电路（3570），并且可操作以在至少第一操作性能点（OPP1）和第二较高操作功率管理电路（2610）的性能点（OPP2），每个性能点包括电压和工作频率的相应对（Vn，Fn），并且功率管理控制电路（3570）还可操作以控制功率管理电路功率管理电路（2610），其中在给定操作性能点处的功率管理电路（2610）具有静态功耗（4820.1），并且动态功率开关将功率管理电路置于较低的静态功率状态 4860.1），功耗比静态功耗（4820.1）要低。

2. 发明授权

US08051313B2 Apparatus, system and method of power state control 有权
标题翻译：电力状态控制的装置，系统和方法
公开(公告)号：US08051313B2
公开(公告)日：2011-11-01
申请号：US12110589
申请日：2008-04-28
申请人： Bixia Li , Hugh Mair , Minh Chau , Alice Wang , Uming Ko
发明人： Bixia Li , Hugh Mair , Minh Chau , Alice Wang , Uming Ko
IPC分类号： G06F1/00 , G05F1/10 , H03K3/02 , H03K17/16
CPC分类号： H03K3/0375
摘要： An apparatus, system and method for asynchronously reducing power in a power domain. In one embodiment, the method includes: (1) receiving a sleep command for the power domain, (2) receiving, upon receiving the sleep command, an affirmative retention status signal denoting that a retention area in the power domain has stored data, (3) receiving, upon receiving the sleep command, an affirmative isolation status signal that denotes that an isolation of the power domain has occurred and (4) providing a power domain off command to the power domain upon receiving at least the sleep command, the affirmative status retention signal and the affirmative status isolation signal. In another embodiment, multiple enable signals are employed to generate a “glitch-free” control for a power switch.
摘要翻译：用于在电力域中异步降低功率的装置，系统和方法。在一个实施例中，该方法包括：（1）接收功率域的睡眠命令，（2）在接收到睡眠命令时接收表示功率域中的保留区域已存储数据的肯定保持状态信号（ 3）在接收到睡眠命令时接收表示已经发生功率域隔离的肯定隔离状态信号，以及（4）至少在接收到睡眠命令时向功率域提供功率域关闭命令，肯定的状态保持信号和肯定状态隔离信号。在另一个实施例中，采用多个使能信号来产生功率开关的“无毛刺”控制。

3. 发明申请

US20090267638A1 Apparatus, System and Method of Power State Control 有权
标题翻译：电力状态控制的装置，系统和方法
公开(公告)号：US20090267638A1
公开(公告)日：2009-10-29
申请号：US12110589
申请日：2008-04-28
申请人： Bixia Li , Hugh Mair , Minh Chau , Alice Wang , Uming Ko
发明人： Bixia Li , Hugh Mair , Minh Chau , Alice Wang , Uming Ko
IPC分类号： H03K19/003 , H03K3/02
CPC分类号： H03K3/0375
摘要： An apparatus, system and method for asynchronously reducing power in a power domain. In one embodiment, the method includes: (1) receiving a sleep command for the power domain, (2) receiving, upon receiving the sleep command, an affirmative retention status signal denoting that a retention area in the power domain has stored data, (3) receiving, upon receiving the sleep command, an affirmative isolation status signal that denotes that an isolation of the power domain has occurred and (4) providing a power domain off command to the power domain upon receiving at least the sleep command, the affirmative status retention signal and the affirmative status isolation signal. In another embodiment, multiple enable signals are employed to generate a “glitch-free” control for a power switch.
摘要翻译：用于在电力域中异步降低功率的装置，系统和方法。在一个实施例中，该方法包括：（1）接收功率域的睡眠命令，（2）在接收到睡眠命令时接收表示功率域中的保留区域已存储数据的肯定保持状态信号（ 3）在接收到睡眠命令时接收表示已经发生功率域隔离的肯定隔离状态信号，以及（4）至少在接收到睡眠命令时向功率域提供功率域关闭命令，肯定的状态保持信号和肯定状态隔离信号。在另一个实施例中，采用多个使能信号来产生功率开关的“无毛刺”控制。

4. 发明申请

US20050194592A1 Adaptive voltage control for performance and energy optimization 有权
标题翻译：用于性能和能量优化的自适应电压控制
公开(公告)号：US20050194592A1
公开(公告)日：2005-09-08
申请号：US11045222
申请日：2005-01-28
申请人： Hugh Mair , Gordon Gammie , Alice Wang
发明人： Hugh Mair , Gordon Gammie , Alice Wang
IPC分类号： H01L29/04
CPC分类号： G11C5/147
摘要： A device for adaptively controlling a voltage supplied to circuitry in substantially close proximity to the device, comprising a processing module, a first tracking element coupled to the processing module and producing a first value indicative of a first estimated speed associated with the circuitry, and a second tracking element coupled to the processing module and producing a second value indicative of a second estimated speed associated with the circuitry. The processing module compares each of the first and second values to a target value and causes a voltage output to be adjusted based on said comparison.
摘要翻译：一种用于自适应地控制提供给基本上靠近设备的电路的电压的装置，包括处理模块，耦合到处理模块的第一跟踪元件，并产生指示与电路相关联的第一估计速度的第一值，以及第二跟踪元件耦合到所述处理模块并产生指示与所述电路相关联的第二估计速度的第二值。处理模块将第一和第二值中的每一个与目标值进行比较，并且基于所述比较使电压输出被调整。

5. 发明授权

US07091766B2 Retention register for system-transparent state retention 有权
标题翻译：保留注册表，用于系统透明状态保留
公开(公告)号：US07091766B2
公开(公告)日：2006-08-15
申请号：US10616207
申请日：2003-07-03
申请人： Uming Ko , David B. Scott , Sumanth Gururajarao , Hugh Mair
发明人： Uming Ko , David B. Scott , Sumanth Gururajarao , Hugh Mair
IPC分类号： H03K3/12 , H03K3/37 , H03K3/286 , H03K3/356
CPC分类号： H03K3/356008
摘要： State retention registers for use in low-power standby modes of digital IC operation are provided, wherein: a differential circuit (M1−M3; M1−M4) is used to load the shadow latch from the normal functional latch; the signal (REST, RESTZ) used to restore data from the shadow latch to the normal functional latch is a “don't care” signal while the shadow latch is retaining the data during low-power standby mode; retained data from the shadow latch is restored to the normal functional latch via a transistor gate connected to a node (N10) of the shadow latch where the retained data is provided; a power supply (VDD) other than the shadow latch's power supply (VRETAIN) powers the data restore operation; and the normal functional latch is operable independently of the operational states of the high Vt transistors (M1, M2, M5 and M6; M3, M4, M5 and M6) used to implement the state retention functionality. In addition, an isolation apparatus is provided to retain an output of a logic module while the logic module is powered-down.
摘要翻译：提供了用于数字IC操作的低功率待机模式的状态保持寄存器，其中：差分电路（M 1 -M 3; M 1 -M 4）用于从常规功能锁存器加载阴影锁存器; 用于将数据从阴影锁存器恢复到正常功能锁存器的信号（REST，RESTZ）是“无关”信号，而阴影锁存器在低功耗待机模式期间保留数据; 来自阴影锁存器的保留数据经由连接到提供保留数据的阴影锁存器的节点（N10）的晶体管栅极恢复到正常功能锁存器; 除了阴影锁存器电源（VRETAIN）之外的电源（VDD）为数据恢复操作供电; 并且正常功能锁存器可独立于高V 1晶体管（M 1，M 2，M 5和M 6; M 3，M 4，M 5和M 6）的工作状态工作，用于实现状态保留功能。此外，提供隔离装置以在逻辑模块断电时保持逻辑模块的输出。

6. 发明申请

US20060125470A1 System and method for IDDQ measurement in system on a chip (SOC) design 有权
标题翻译：系统芯片（SOC）设计中IDDQ测量的系统和方法
公开(公告)号：US20060125470A1
公开(公告)日：2006-06-15
申请号：US11010135
申请日：2004-12-10
申请人： Wei Chen , Hugh Mair , Uming Ko , David Scott
发明人： Wei Chen , Hugh Mair , Uming Ko , David Scott
IPC分类号： G01R31/28
CPC分类号： G01R31/3008 , G01R31/3012
摘要： System and method for detecting transistor failure in large-scale integrated circuits by measuring IDDQ. A preferred embodiment comprises a switch structure for an integrated circuit made up of a plurality of main switches (such as main switch 410) selectively coupling a power sub-domain to a power source pin, a plurality of pi-switches (such as pi-switch 415) selectively coupling pairs of power sub-domains, and a plurality of IDDQ switches (such as IDDQ switch 425) selectively coupling the power sub-domains to a VIDDQ pin. The pi-switches can decouple the power sub-domains while the IDDQ switches can enable the measurement of the quiescent current in the power sub-domains. The use of pi-switches and IDDQ switches can permit the measurement of the quiescent current in the power sub-domains without requiring the use of isolation buffers and needed to powering on and off the integrated circuit between current measurements in the different power sub-domains.
摘要翻译：通过测量IDDQ来检测大型集成电路中的晶体管故障的系统和方法。优选实施例包括由多个选择性地将电源子域耦合到电源引脚的多个主开关（例如主开关410）构成的集成电路的开关结构，多个pi开关（例如，开关415）选择性地耦合功率子域对，以及选择性地将功率子域耦合到VIDDQ引脚的多个IDDQ开关（例如IDDQ开关425）。 pi开关可以对功率子域进行去耦，而IDDQ开关可以测量电源子域中的静态电流。 pi开关和IDDQ开关的使用可以允许测量电源子域中的静态电流，而不需要使用隔离缓冲器，并且需要在不同功率子域中的电流测量之间为集成电路供电和关断。

7. 发明授权

US08812885B2 Detecting wake-up events for a chip based on an I/O power supply 有权
标题翻译：基于I / O电源检测芯片的唤醒事件
公开(公告)号：US08812885B2
公开(公告)日：2014-08-19
申请号：US11695304
申请日：2007-04-02
申请人： Philippe Royannez , Gilles Dubost , Christophe Vatinel , William Douglas Wilson , Vinod Menezes , Hugh Mair , James Sangwon Song
发明人： Philippe Royannez , Gilles Dubost , Christophe Vatinel , William Douglas Wilson , Vinod Menezes , Hugh Mair , James Sangwon Song
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： A device is provided that includes a chip having a processor and wake-up logic. The device also includes power management circuitry coupled to the chip. The power management circuitry selectively provides a core power supply and an input/output (I/O) power supply to the chip. Even if the power management circuitry cuts off the core power supply to the chip, the wake-up logic detects and responds to wake-up events based on power provided by the I/O power supply.
摘要翻译：提供了一种包括具有处理器和唤醒逻辑的芯片的设备。该装置还包括耦合到芯片的电源管理电路。电源管理电路选择性地向芯片提供核心电源和输入/输出（I / O）电源。即使电源管理电路切断芯片的核心电源，唤醒逻辑也会根据I / O电源提供的电源来检测和响应唤醒事件。

8. 发明申请

US20080162969A1 DETECTING WAKE-UP EVENTS FOR A CHIP BASED ON AN I/O POWER SUPPLY 有权
标题翻译：检测基于I / O电源的芯片的唤醒事件
公开(公告)号：US20080162969A1
公开(公告)日：2008-07-03
申请号：US11695304
申请日：2007-04-02
申请人： Philippe Royannez , Gilles Dubost , Christophe Vantinel , William Douglas Wilson , Vinod Menezes , Hugh Mair , James Sangwon Song
发明人： Philippe Royannez , Gilles Dubost , Christophe Vantinel , William Douglas Wilson , Vinod Menezes , Hugh Mair , James Sangwon Song
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： A device is provided that includes a chip having a processor and wake-up logic. The device also includes power management circuitry coupled to the chip. The power management circuitry selectively provides a core power supply and an input/output (I/O) power supply to the chip. Even if the power management circuitry cuts off the core power supply to the chip, the wake-up logic detects and responds to wake-up events based on power provided by the I/O power supply.
摘要翻译：提供了一种包括具有处理器和唤醒逻辑的芯片的设备。该装置还包括耦合到芯片的电源管理电路。电源管理电路选择性地向芯片提供核心电源和输入/输出（I / O）电源。即使电源管理电路切断芯片的核心电源，唤醒逻辑也会根据I / O电源提供的电源来检测和响应唤醒事件。

9. 发明授权

US07180208B2 Switch structure for reduced voltage fluctuation in power domains and sub-domains 有权
标题翻译：电源域和子域电压波动减小的开关结构
公开(公告)号：US07180208B2
公开(公告)日：2007-02-20
申请号：US10735943
申请日：2003-12-15
申请人： Wei Chen , Hugh Mair , Uming Ko , David Scott
发明人： Wei Chen , Hugh Mair , Uming Ko , David Scott
IPC分类号： H01H35/00 , H02B1/24
CPC分类号： G06F1/305 , H02J1/08 , H02J2001/008 , Y10T307/391 , Y10T307/766
摘要： System and method for reducing voltage fluctuations in an integrated circuit with multiple power domains and sub-domains. A preferred embodiment comprises a plurality of voltage sources and a switching network (such as switching network 320) wherein outputs from the plurality of voltage sources are inputs. The switching network can couple the outputs of voltage sources (based on a mapping) with the same output voltage levels to reduce voltage fluctuation amongst power domains coupled to the coupled outputs. The coupling may be performed by a switching structure (such as the switching structure 215) that can controllably electrically couple two outputs.
摘要翻译：用于减少具有多个电源域和子域的集成电路中的电压波动的系统和方法。优选实施例包括多个电压源和交换网络（例如交换网络320），其中来自多个电压源的输出是输入。开关网络可以将电压源的输出（基于映射）耦合到相同的输出电压电平，以减少耦合到耦合输出的功率域之间的电压波动。耦合可以由可控制地电耦合两个输出的开关结构（例如开关结构215）来执行。

10. 发明申请

US20050146228A1 Switch structure for reduced voltage fluctuation in power domains and sub-domains 有权
标题翻译：电源域和子域电压波动减小的开关结构
公开(公告)号：US20050146228A1
公开(公告)日：2005-07-07
申请号：US10735943
申请日：2003-12-15
申请人： Wei Chen , Hugh Mair , Uming Ko , David Scott
发明人： Wei Chen , Hugh Mair , Uming Ko , David Scott
IPC分类号： G06F1/30 , H02B1/24 , H02J1/08
CPC分类号： G06F1/305 , H02J1/08 , H02J2001/008 , Y10T307/391 , Y10T307/766
摘要： System and method for reducing voltage fluctuations in an integrated circuit with multiple power domains and sub-domains. A preferred embodiment comprises a plurality of voltage sources and a switching network (such as switching network 320) wherein outputs from the plurality of voltage sources are inputs. The switching network can couple the outputs of voltage sources (based on a mapping) with the same output voltage levels to reduce voltage fluctuation amongst power domains coupled to the coupled outputs. The coupling may be performed by a switching structure (such as the switching structure 215) that can controllably electrically couple two outputs.
摘要翻译：用于减少具有多个电源域和子域的集成电路中的电压波动的系统和方法。优选实施例包括多个电压源和交换网络（例如交换网络320），其中来自多个电压源的输出是输入。开关网络可以将电压源的输出（基于映射）耦合到相同的输出电压电平，以减少耦合到耦合输出的功率域之间的电压波动。耦合可以由可控制地电耦合两个输出的开关结构（例如开关结构215）来执行。

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