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1. 发明授权

US06323680B1 Programmable logic device configured to accommodate multiplication 有权
标题翻译：配置为适应乘法的可编程逻辑器件
公开(公告)号：US06323680B1
公开(公告)日：2001-11-27
申请号：US09517350
申请日：2000-03-02
申请人： Bruce B. Pedersen , Sergey Shumarayev , Wei-Jen Huang , Vinson Chan , Stephen Brown , Tony Ngai , James Park
发明人： Bruce B. Pedersen , Sergey Shumarayev , Wei-Jen Huang , Vinson Chan , Stephen Brown , Tony Ngai , James Park
IPC分类号： G06F738
CPC分类号： H03K19/17736 , G06F7/5443 , H03K19/1737 , H03K19/17728 , H03K19/17732
摘要： A programmable logic device is configured to accommodate multiplication by the provision in each logic region of specialized components to form and sum partial products. The specialized components are separate from the ordinary logic of the logic region, and their presence imposes little penalty on the performance of ordinary logic functions, while enhancing the speed at which multiplication is performed by minimizing the number of logic regions used for a particular multiplication operation, and also minimizing the use of the interconnection resources of the device to convey signals among those regions.
摘要翻译：可编程逻辑器件被配置为通过专用部件的每个逻辑区域中的提供来适应乘法，以形成和求和部分乘积。专门的部件与逻辑区域的普通逻辑分开，并且它们的存在对普通逻辑功能的性能施加了很小的损失，同时通过最小化用于特定乘法运算的逻辑区域的数量来提高执行乘法的速度并且还最小化设备的互连资源在这些区域之间传送信号的使用。

2. 发明授权

US06239615B1 High-performance interconnect 有权
标题翻译：高性能互连
公开(公告)号：US06239615B1
公开(公告)日：2001-05-29
申请号：US09235371
申请日：1999-01-20
申请人： Tony Ngai , Sergey Shumarayev , Sammy Cheung , Rakesh Patel , Vinson Chan
发明人： Tony Ngai , Sergey Shumarayev , Sammy Cheung , Rakesh Patel , Vinson Chan
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H01L23/5222 , H01L2924/0002 , H03K19/1778 , H03K19/17792 , H03K19/17796 , H01L2924/00
摘要： Techniques for providing high-performance interconnect for integrated circuits will improve overall integrated circuit performance. These techniques include arranging, laying out, and fabricating the signal conductors (e.g., 405, 720) so the parasitic coupling capacitances (e.g., 425) are minimized and parasitic resistance is reduced. The techniques will minimize effects of crosstalk noise between the conductors, and thus improve overall integrated circuit performance.
摘要翻译：为集成电路提供高性能互连的技术将提高整体集成电路性能。这些技术包括布置，布置和制造信号导体（例如，405,720），使得寄生耦合电容（例如425）最小化并且寄生电阻降低。这些技术将最小化导体之间串扰噪声的影响，从而提高整体集成电路性能。

3. 发明授权

US06281704B1 High-performance interconnect 有权
公开(公告)号：US06281704B1
公开(公告)日：2001-08-28
申请号：US09810116
申请日：2001-03-15
申请人： Tony Ngai , Sergey Shumarayev , Sammy Cheung , Rakesh Patel , Vinson Chan
发明人： Tony Ngai , Sergey Shumarayev , Sammy Cheung , Rakesh Patel , Vinson Chan
IPC分类号： H03K19177
摘要： Techniques for providing high-performance interconnect for integrated circuits will improve overall integrated circuit performance. These techniques include arranging, laying out, and fabricating the signal conductors (e.g., 405, 720) so the parasitic coupling capacitances (e.g., 425) are minimized and parasitic resistance is reduced. The techniques will minimize effects of crosstalk noise between the conductors, and thus improve overall integrated circuit performance.

4. 发明授权

US08488623B2 Scalable interconnect modules with flexible channel bonding 有权
公开(公告)号：US08488623B2
公开(公告)日：2013-07-16
申请号：US12845672
申请日：2010-07-28
申请人： Keith Duwel , Michael Menghui Zheng , Vinson Chan , Kalyan Kankipati
发明人： Keith Duwel , Michael Menghui Zheng , Vinson Chan , Kalyan Kankipati
IPC分类号： H04J3/16 , H04J3/22 , H04J3/06
CPC分类号： H04J3/1682 , H04J3/04 , H04J3/0685 , H04L5/22 , H04Q2213/13208 , H04Q2213/13322
摘要： The present application discloses apparatus and methods for increasing channel utilization for a high-speed serial interface of an integrated circuit (IC). A new circuit architecture is disclosed which provides circuitry that may be programmed flexibly to support a multitude of different channel bonding schemes. In accordance with one aspect of the invention, the new architecture decouples the granularity of control-signal channel bonding from the granularity of data-aggregation channel bonding. This advantageously allows optimization of configurations for both types of channel bonding. In another aspect of the invention, the logical boundaries of bonded user channels are decoupled from the physical boundaries of the PCS modules. This decoupling advantageously eliminates a rigid constraint of previous architectures.

5. 发明授权

US07362833B1 Dynamic special character selection for use in byte alignment circuitry 有权
标题翻译：用于字节对齐电路的动态特殊字符选择
公开(公告)号：US07362833B1
公开(公告)日：2008-04-22
申请号：US10609091
申请日：2003-06-27
申请人： Vinson Chan , Chong Lee , Rakesh Patel , Ramanand Venkata
发明人： Vinson Chan , Chong Lee , Rakesh Patel , Ramanand Venkata
IPC分类号： H04B1/10
CPC分类号： H04J3/0608
摘要： Circuitry for locating the boundaries of bytes in a data stream is provided. The data stream typically has comma or header information that provides an indication of the byte boundaries. When circuitry detects this information, it can align the byte boundaries and thereby provide byte-aligned data to utilization circuitry (e.g., a programmable logic device). In accordance with this invention, circuitry can select different special characters for use in detecting the byte boundaries, where the special characters are different lengths. Circuitry aligns the byte boundaries based on the selected special character when enabled by a control signal. Once aligned, circuitry can provide a signal indicating which special character was used to align the boundaries. Another advantage of the invention is that it eliminates alignment problems associated with system latency. Circuitry automatically locks alignment to a first instance of a detected special character independent of an external control signal.
摘要翻译：提供了用于定位数据流中字节边界的电路。数据流通常具有提供字节边界指示的逗号或头信息。当电路检测到该信息时，它可以对齐字节边界，从而向利用电路（例如，可编程逻辑器件）提供字节对齐的数据。根据本发明，电路可以选择用于检测字节边界的不同特殊字符，其中特殊字符是不同的长度。当控制信号使能时，电路会根据所选择的特殊字符对齐字节边界。一旦对准，电路可以提供一个信号，指示哪个特殊字符用于对齐边界。本发明的另一个优点是它消除了与系统延迟相关联的对准问题。电路自动将校准锁定到独立于外部控制信号的检测到的特殊字符的第一实例。

6. 发明授权

US06842034B1 Selectable dynamic reconfiguration of programmable embedded IP 有权
标题翻译：可编程嵌入式IP的可选择动态重新配置
公开(公告)号：US06842034B1
公开(公告)日：2005-01-11
申请号：US10612253
申请日：2003-07-01
申请人： Vinson Chan , Chong Lee , Rakesh Patel , Ramanand Venkata , Binh Ton
发明人： Vinson Chan , Chong Lee , Rakesh Patel , Ramanand Venkata , Binh Ton
IPC分类号： H03K19/177 , H03K19/00
CPC分类号： H03K19/17752 , H03K19/17732 , H03K19/17736 , H03K19/17744
摘要： Improved communication, and an improved communication interface, between the core PLD fabric of a PLD and embedded IP building blocks resident therein is provided. A circuit according to the invention may include at least two different signal paths between the PLD core fabric and embedded IP building blocks. Either one, or both, of these two paths may be used for configuration and/or implementation of the embedded IP building blocks.
摘要翻译：提供了PLD的核心PLD结构与驻留在其中的嵌入式IP构建块之间的改进的通信和改进的通信接口。根据本发明的电路可以包括PLD核心结构和嵌入式IP构建块之间的至少两个不同的信号路径。这两个路径中的一个或两者可以用于嵌入式IP构建块的配置和/或实现。

7. 发明授权

US09170952B1 Configurable multi-standard device interface 有权
标题翻译：可配置的多标准设备接口
公开(公告)号：US09170952B1
公开(公告)日：2015-10-27
申请号：US13338707
申请日：2011-12-28
申请人： Divya Vijayaraghavan , Vinson Chan , Keith Duwel , Chong H. Lee
发明人： Divya Vijayaraghavan , Vinson Chan , Keith Duwel , Chong H. Lee
IPC分类号： G06F13/00 , G06F12/02 , G06F12/08 , G06F13/12 , G06F13/14 , G06F11/00 , H01L25/00 , H04J3/06
CPC分类号： G06F12/0862 , G06F13/00 , H03K19/17744
摘要： A configurable interface includes a transmitter module and a receiver module, each configured to operate according to at least three different interface standards. The configurable interface further includes an interface module configured to determine a physical medium attachment (PMA) standard of a PMA coupled to the configurable interface and activate at least one component of the configurable interface based on the PMA standard. In an arrangement, the device interface supports a CAUI-4 standard.
摘要翻译：可配置接口包括发射器模块和接收器模块，每个发送器模块和接收器模块被配置为根据至少三个不同的接口标准进行操作。所述可配置接口还包括接口模块，所述接口模块被配置为确定耦合到所述可配置接口的PMA的物理介质连接（PMA）标准，并基于所述PMA标准激活所述可配置接口的至少一个组件。在这种安排中，设备接口支持CAUI-4标准。

8. 发明申请

US20120027026A1 SCALABLE INTERCONNECT MODULES WITH FLEXIBLE CHANNEL BONDING 有权
标题翻译：具有灵活通道连接的可扩展互连模块
公开(公告)号：US20120027026A1
公开(公告)日：2012-02-02
申请号：US12845672
申请日：2010-07-28
申请人： Keith Duwel , Michael Menghui Zheng , Vinson Chan , Kalyan Kankipati
发明人： Keith Duwel , Michael Menghui Zheng , Vinson Chan , Kalyan Kankipati
IPC分类号： H04J3/16
CPC分类号： H04J3/1682 , H04J3/04 , H04J3/0685 , H04L5/22 , H04Q2213/13208 , H04Q2213/13322
摘要： The present application discloses apparatus and methods for increasing channel utilization for a high-speed serial interface of an integrated circuit (IC). A new circuit architecture is disclosed which provides circuitry that may be programmed flexibly to support a multitude of different channel bonding schemes. In accordance with one aspect of the invention, the new architecture decouples the granularity of control-signal channel bonding from the granularity of data-aggregation channel bonding. This advantageously allows optimization of configurations for both types of channel bonding. In another aspect of the invention, the logical boundaries of bonded user channels are decoupled from the physical boundaries of the PCS modules. This decoupling advantageously eliminates a rigid constraint of previous architectures.
摘要翻译：本申请公开了用于增加集成电路（IC）的高速串行接口的信道利用的装置和方法。公开了一种新的电路架构，其提供可以被灵活地编程以支持多种不同的信道绑定方案的电路。根据本发明的一个方面，新架构使控制信号信道绑定的粒度与数据聚合信道绑定的粒度分离。这有利地允许优化用于两种类型的通道结合的配置。在本发明的另一方面，粘合用户信道的逻辑边界与PCS模块的物理边界分离。这种去耦有利地消除了先前架构的刚性约束。

9. 发明授权

US07343569B1 Apparatus and method for reset distribution 有权
标题翻译：复位分配的装置和方法
公开(公告)号：US07343569B1
公开(公告)日：2008-03-11
申请号：US11351425
申请日：2006-02-10
申请人： John Lam , Arch Zaliznyak , Chong Lee , Rakesh Patel , Vinson Chan
发明人： John Lam , Arch Zaliznyak , Chong Lee , Rakesh Patel , Vinson Chan
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F2217/66
摘要： A skew-tolerant, glitch-free reset distribution apparatus and method are provided in an intellectual property (IP) block that supports a multi-channel input/output protocol. During reset mode, synchronizers are used to create more predictable timing, to pipeline the propagation delay, and to tolerate RC-induced skews of up to a clock period in routing a reset signal to all the channels and within the channels in an IP block. Two control signals, which are available from programmable logic resource core circuitry, are used to control the input of the reset signal into the IP block. Because the control signals are designed to be glitch-free, the reset signal is therefore also glitch-free, thus preventing the IP block from inadvertently transitioning into or out of reset mode.
摘要翻译：在支持多通道输入/输出协议的知识产权（IP）块中提供了容错，无毛刺的复位分配装置和方法。在复位模式期间，使用同步器创建更可预测的时序，流水线传播延迟，并允许在将复位信号路由到IP模块中的所有通道和通道内的RC时钟周期的RC引起的偏差。两个控制信号可从可编程逻辑资源核心电路获得，用于控制复位信号输入到IP模块。由于控制信号被设计为无毛刺，因此复位信号也无毛刺，从而防止IP块无意中转换或复位。

10. 发明授权

US09736086B1 Multi-function, multi-protocol FIFO for high-speed communication 有权
公开(公告)号：US09736086B1
公开(公告)日：2017-08-15
申请号：US13098361
申请日：2011-04-29
申请人： Huy Ngo , Keith Duwel , Vinson Chan , Divya Vijayaraghavan , Curt Wortman
发明人： Huy Ngo , Keith Duwel , Vinson Chan , Divya Vijayaraghavan , Curt Wortman
IPC分类号： H04L12/861
CPC分类号： H04L49/90 , H04L47/6245
摘要： Systems and methods are disclosed for buffering data using a multi-function, multi-protocol first-in-first-out (FIFO) circuit. For example, a data buffering apparatus is provided that includes a mode selection input and a FIFO circuit that is operative to buffer a data signal between a FIFO circuit input and a FIFO circuit output, wherein the FIFO circuit is configured in an operating mode responsive to the mode selection signal.

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