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1. 发明授权

US08946025B2 Manufacturing method of thin film and metal line for display using the same, thin film transistor array panel, and method for manufacturing the same 有权
标题翻译：用于使用该显示器的薄膜和金属线的制造方法，薄膜晶体管阵列面板及其制造方法
公开(公告)号：US08946025B2
公开(公告)日：2015-02-03
申请号：US12931516
申请日：2011-02-03
申请人： Byeong-Beom Kim , Je-Hyeong Park , Jae-Hyoung Youn , Jean-Ho Song , Jong-In Kim
发明人： Byeong-Beom Kim , Je-Hyeong Park , Jae-Hyoung Youn , Jean-Ho Song , Jong-In Kim
IPC分类号： H01L21/336 , H01L21/00 , H01L21/84 , H01L29/04 , H01L29/10 , H01L27/14 , H01L31/036 , H01L23/48 , C23C14/14 , C23C14/34 , H01L23/52 , H01L29/786
CPC分类号： H01L27/124 , C23C14/14 , C23C14/34 , H01L23/4827 , H01L23/52 , H01L29/786 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a thin film according to an exemplary embodiment of the present invention includes forming the thin film at a power density in the range of approximately 1.5 to approximately 3 W/cm2 and at a pressure of an inert gas that is in the range of approximately 0.2 to approximately 0.3 Pa. This process results in an amorphous metal thin film barrier layer that prevents undesired diffusion from adjacent layers, even when this barrier layer is thinner than many conventional barrier layers.
摘要翻译：根据本发明的示例性实施方案的薄膜的形成方法包括以大约1.5至大约3W / cm 2的功率密度和处于该范围内的惰性气体的压力形成薄膜大约0.2至大约0.3Pa。这个过程产生一个非晶金属薄膜阻挡层，防止相邻层的不期望的扩散，即使该阻挡层比许多传统的阻挡层薄。

2. 发明申请

US20120064678A1 MANUFACTURING METHOD OF THIN FILM TRANSISTOR ARRAY PANEL 审中-公开
标题翻译：薄膜晶体管阵列的制造方法
公开(公告)号：US20120064678A1
公开(公告)日：2012-03-15
申请号：US13069070
申请日：2011-03-22
申请人： Byeong-Jin LEE , Yu-Gwang Jeong , Dong-Ju Yang , Bong-Kyun Kim , Hong-Sick Park , Byeong-Beom Kim , Sang-Gab Kim , Ji-Young Park , Jean-Ho Song , Ki-Yeup Lee , Shin-Il Choi
发明人： Byeong-Jin LEE , Yu-Gwang Jeong , Dong-Ju Yang , Bong-Kyun Kim , Hong-Sick Park , Byeong-Beom Kim , Sang-Gab Kim , Ji-Young Park , Jean-Ho Song , Ki-Yeup Lee , Shin-Il Choi
IPC分类号： H01L21/336
CPC分类号： H01L27/1288 , H01L27/1214 , H01L29/458 , H01L29/4908 , H01L29/66765 , H01L29/78678
摘要： A method for manufacturing a TFT array panel includes forming a photosensitive film pattern with first and second parts in first and second sections on a metal layer, etching the metal layer of a third section using the film pattern as a mask to form first and second metal patterns, etching the film pattern to remove the first part, etching first and second amorphous silicon layers of the third section using the second part as a mask to form an amorphous silicon pattern and a semiconductor, etching the first and second metal patterns of the first section using the second part as a mask to form a source electrode and a drain electrode including an upper layer and a lower layer, and etching the amorphous silicon pattern of the region corresponding to the first section by using the second part as a mask to form an ohmic contact.
摘要翻译：一种TFT阵列板的制造方法，其特征在于，在金属层的第一和第二部分中形成具有第一和第二部分的感光膜图案，使用所述膜图案作为掩模蚀刻第三部分的金属层，以形成第一和第二金属蚀刻薄膜图案以去除第一部分，使用第二部分作为掩模蚀刻第三部分的第一和第二非晶硅层以形成非晶硅图案和半导体，蚀刻第一部分的第一和第二金属图案使用第二部分作为掩模形成源电极和包括上层和下层的漏极，并且通过使用第二部分作为掩模来蚀刻与第一部分相对应的区域的非晶硅图案以形成欧姆接触。

3. 发明授权

US08058114B2 Method of manufacturing the array substrate capable of decreasing a line resistance 有权
标题翻译：能够降低线电阻的阵列基板的制造方法
公开(公告)号：US08058114B2
公开(公告)日：2011-11-15
申请号：US12797527
申请日：2010-06-09
申请人： Jang-Soo Kim , Hong-Long Ning , Bong-Kyun Kim , Hong-Sick Park , Shi-Yul Kim , Chang-Oh Jeong , Sang-Gab Kim , Jae-Hyoung Youn , Woo-Geun Lee , Yang-Ho Bae , Pil-Sang Yun , Jong-Hyun Choung , Sun-Young Hong , Ki-Won Kim , Byeong-Jin Lee , Young-Wook Lee , Jong-In Kim , Byeong-Beom Kim , Nam-Seok Suh
发明人： Jang-Soo Kim , Hong-Long Ning , Bong-Kyun Kim , Hong-Sick Park , Shi-Yul Kim , Chang-Oh Jeong , Sang-Gab Kim , Jae-Hyoung Youn , Woo-Geun Lee , Yang-Ho Bae , Pil-Sang Yun , Jong-Hyun Choung , Sun-Young Hong , Ki-Won Kim , Byeong-Jin Lee , Young-Wook Lee , Jong-In Kim , Byeong-Beom Kim , Nam-Seok Suh
IPC分类号： H01L21/84 , H01L21/336
CPC分类号： G02F1/13458 , G02F1/136286 , G02F2001/136295 , H01L27/1218 , H01L27/124 , H01L27/1288
摘要： A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed.
摘要翻译：栅极线包括形成在基底基板上的第一籽晶层和形成在第一籽晶层上的第一金属层。在基底基板上形成第一绝缘层。在基底基板上形成第二绝缘层。这里，在与栅极线交叉的方向上通过第二绝缘层形成线沟槽。数据线包括形成在线沟槽下方的第二晶种层和形成在线沟槽中的第二金属层。像素电极形成在基底基板的像素区域中。因此，使用绝缘层形成预定深度的沟槽，并且通过电镀方法形成金属层，从而可以形成具有足够厚度的金属线。

4. 发明申请

US20110186843A1 Manufacturing method of thin film and metal line for display using the same, thin film transistor array panel, and method for manufacturing the same 有权
标题翻译：使用该薄膜和金属线的显示器的制造方法，薄膜晶体管阵列面板及其制造方法
公开(公告)号：US20110186843A1
公开(公告)日：2011-08-04
申请号：US12931516
申请日：2011-02-03
申请人： Byeong-Beom Kim , Je-Hyeong Park , Jae-Hyoung Youn , Jean-Ho Song , Jong-In Kim
发明人： Byeong-Beom Kim , Je-Hyeong Park , Jae-Hyoung Youn , Jean-Ho Song , Jong-In Kim
IPC分类号： H01L29/786 , H01L21/336 , H01L23/52 , C23C14/34 , C23C14/14
CPC分类号： H01L27/124 , C23C14/14 , C23C14/34 , H01L23/4827 , H01L23/52 , H01L29/786 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a thin film according to an exemplary embodiment of the present invention includes forming the thin film at a power density in the range of approximately 1.5 to approximately 3 W/cm2 and at a pressure of an inert gas that is in the range of approximately 0.2 to approximately 0.3 Pa. This process results in an amorphous metal thin film barrier layer that prevents undesired diffusion from adjacent layers, even when this barrier layer is thinner than many conventional barrier layers.
摘要翻译：根据本发明的示例性实施方式的薄膜形成方法包括以大约1.5至大约3W / cm 2的功率密度形成薄膜，并且在惰性气体的压力范围内大约0.2至大约0.3Pa。这个过程产生一个非晶金属薄膜阻挡层，防止相邻层的不期望的扩散，即使该阻挡层比许多传统的阻挡层更薄。

5. 发明申请

US20100261322A1 ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：阵列基板及其制造方法
公开(公告)号：US20100261322A1
公开(公告)日：2010-10-14
申请号：US12797527
申请日：2010-06-09
申请人： Jang-Soo Kim , Hong-Long Ning , Bong-Kyun Kim , Hong-Sick Park , Shi-Yul Kim , Chang-Oh Jeong , Sang-Gab Kim , Jae-Hyoung Youn , Woo-Geun Lee , Yang-Ho Bae , Pil-Sang Yun , Jong-Hyun Choung , Sun-Young Hong , Ki-Won Kim , Byeong-Jin Lee , Young-Wook Lee , Jong-In Kim , Byeong-Beom Kim , Nam-Seok Suh
发明人： Jang-Soo Kim , Hong-Long Ning , Bong-Kyun Kim , Hong-Sick Park , Shi-Yul Kim , Chang-Oh Jeong , Sang-Gab Kim , Jae-Hyoung Youn , Woo-Geun Lee , Yang-Ho Bae , Pil-Sang Yun , Jong-Hyun Choung , Sun-Young Hong , Ki-Won Kim , Byeong-Jin Lee , Young-Wook Lee , Jong-In Kim , Byeong-Beom Kim , Nam-Seok Suh
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： G02F1/13458 , G02F1/136286 , G02F2001/136295 , H01L27/1218 , H01L27/124 , H01L27/1288
摘要： A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed.
摘要翻译：栅极线包括形成在基底基板上的第一籽晶层和形成在第一籽晶层上的第一金属层。在基底基板上形成第一绝缘层。在基底基板上形成第二绝缘层。这里，在与栅极线交叉的方向上通过第二绝缘层形成线沟槽。数据线包括形成在线沟槽下方的第二晶种层和形成在线沟槽中的第二金属层。像素电极形成在基底基板的像素区域中。因此，使用绝缘层形成预定深度的沟槽，并且通过电镀方法形成金属层，从而可以形成具有足够厚度的金属线。

6. 发明申请

US20090212290A1 DISPLAY PANEL AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：显示面板及其制造方法
公开(公告)号：US20090212290A1
公开(公告)日：2009-08-27
申请号：US12354115
申请日：2009-01-15
申请人： Joo-Ae YOUN , Yang-Ho BAE , Chang-Oh JEONG , Chong-Chul CHAI , Pil-Sang YUN , Honglong NING , Byeong-Beom KIM
发明人： Joo-Ae YOUN , Yang-Ho BAE , Chang-Oh JEONG , Chong-Chul CHAI , Pil-Sang YUN , Honglong NING , Byeong-Beom KIM
IPC分类号： H01L27/088 , H01L21/77
CPC分类号： H01L33/0041 , H01L27/124 , H01L29/458
摘要： A display panel includes; a lower gate line, a lower data line disposed substantially perpendicular to the lower gate line, a thin film transistor (“TFT”) connected to the lower gate line and the lower data line, an insulating layer disposed on the lower gate line, the lower data line, and the TFT and having a plurality of trenches exposing the lower gate line and the lower data line, an upper gate line disposed in the trench on the lower gate line, an upper data line disposed in the trench on the lower data line, and a pixel electrode connected to the TFT.
摘要翻译：显示面板包括：下栅极线，基本上垂直于下栅极线设置的下数据线，连接到下栅极线和下数据线的薄膜晶体管（“TFT”），设置在下栅极线上的绝缘层，下数据线和TFT，并且具有暴露下栅极线和下数据线的多个沟槽，设置在下栅极线上的沟槽中的上栅极线，设置在下数据上的沟槽中的上数据线线和与TFT连接的像素电极。

7. 发明申请

US20080213702A1 METHOD FOR PATTERNING CONDUCTIVE POLYMER 审中-公开
标题翻译：用于形成导电聚合物的方法
公开(公告)号：US20080213702A1
公开(公告)日：2008-09-04
申请号：US11932496
申请日：2007-10-31
申请人： Yang-Ho BAE , Chang-Oh JEONG , Byeong-Beom KIM , Jae-Gab LEE , Tae-Wook KWON
发明人： Yang-Ho BAE , Chang-Oh JEONG , Byeong-Beom KIM , Jae-Gab LEE , Tae-Wook KWON
IPC分类号： G03F7/00
CPC分类号： H01L51/0021 , G03F7/0755 , G03F7/165 , H01L51/0023
摘要： A method for patterning a conductive polymer that adheres well to an oxide layer is presented. The method includes forming a self-assembled monolayer on a substrate, patterning the self-assembled monolayer, forming a catalyst layer on the self-assembled monolayer, and forming a conductive polymer layer on the self-assembled monolayer.
摘要翻译：提出了一种用于图案化粘附到氧化物层的导电聚合物的方法。该方法包括在衬底上形成自组装单层，图案化自组装单层，在自组装单层上形成催化剂层，并在自组装单层上形成导电聚合物层。

8. 发明申请

US20080191213A1 THIN FILM TRANSISTOR, THIN FILM TRANSISTOR SUBSTRATE INCLUDING THE SAME AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：薄膜晶体管，包括其的薄膜晶体管基板及其制造方法
公开(公告)号：US20080191213A1
公开(公告)日：2008-08-14
申请号：US11932314
申请日：2007-10-31
申请人： Yang Ho Bae , Chang Oh Jeong , Byeong Beom Kim
发明人： Yang Ho Bae , Chang Oh Jeong , Byeong Beom Kim
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/458 , H01L27/124
摘要： A thin film transistor showing desirable contact characteristics during contact with indium tin oxide (ITO) or indium zinc oxide (IZO), in which a first conductive pattern including a gate electrode and a second conductive pattern including a source electrode and a drain electrode are formed without an etching process, a TFT substrate including the TFTs, and a method of manufacturing the same. The thin film transistor includes a gate electrode formed of a first conductive layer, a gate insulating layer covering the gate electrode, a semiconductor layer forming a channel on the gate insulating layer; an ohmic contact layer formed on the semiconductor layer, and a source electrode and a drain electrode formed of a second conductive layer and of a third conductive layer. The second conductive layer includes an aluminum-nickel alloy and nitrogen and is formed on the semiconductor layer. The third conductive layer includes an aluminum-nickel alloy and is formed on the second conductive layer.
摘要翻译：在与铟锡氧化物（ITO）或铟锌氧化物（IZO）接触期间显示出期望的接触特性的薄膜晶体管，其中形成包括栅电极的第一导电图案和包括源电极和漏电极的第二导电图案没有蚀刻处理，包括TFT的TFT基板及其制造方法。薄膜晶体管包括由第一导电层形成的栅电极，覆盖栅电极的栅极绝缘层，在栅极绝缘层上形成沟道的半导体层; 形成在半导体层上的欧姆接触层，以及由第二导电层和第三导电层形成的源电极和漏电极。第二导电层包括铝 - 镍合金和氮，并形成在半导体层上。第三导电层包括铝镍合金，并形成在第二导电层上。

9. 发明授权

US08304299B2 Thin film transistor substrate and manufacturing method thereof 有权
标题翻译：薄膜晶体管基板及其制造方法
公开(公告)号：US08304299B2
公开(公告)日：2012-11-06
申请号：US12821668
申请日：2010-06-23
申请人： Sung-Ryul Kim , Jean-Ho Song , Jae-Hyoung Youn , O-Sung Seo , Byeong-Beom Kim , Je-Hyeong Park , Jong-In Kim , Jae-Jin Song
发明人： Sung-Ryul Kim , Jean-Ho Song , Jae-Hyoung Youn , O-Sung Seo , Byeong-Beom Kim , Je-Hyeong Park , Jong-In Kim , Jae-Jin Song
IPC分类号： H01L21/00
CPC分类号： H01L29/78603 , H01L27/124 , H01L27/1288 , H01L29/458 , H01L29/66765
摘要： A thin film transistor array panel according to an exemplary embodiment of the present invention comprises a substrate, a gate line formed on the substrate, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, and a data line formed on the semiconductor layer, wherein the data line comprises a lower data layer, an upper data layer, a data oxide layer, and a buffer layer, wherein the upper data layer and the buffer layer comprise a same material.
摘要翻译：根据本发明的示例性实施例的薄膜晶体管阵列面板包括基板，形成在基板上的栅极线，形成在栅极线上的栅极绝缘层，形成在栅极绝缘层上的半导体层，以及数据其中所述数据线包括下数据层，上数据层，数据氧化层和缓冲层，其中所述上数据层和所述缓冲层包括相同的材料。

10. 发明授权

US08273612B2 Display panel and method of manufacturing the same 有权
标题翻译：显示面板及其制造方法
公开(公告)号：US08273612B2
公开(公告)日：2012-09-25
申请号：US12981287
申请日：2010-12-29
申请人： Min-Seok Oh , Yang-Ho Bae , Pil-Sang Yun , Byeong-Beom Kim , Seung-Ha Choi , Sang-Gab Kim , Chang-Ho Jeong , Shin-Il Choi , Hong-Kee Chin , Yu-Gwang Jeong , Dong-Ju Yang
发明人： Min-Seok Oh , Yang-Ho Bae , Pil-Sang Yun , Byeong-Beom Kim , Seung-Ha Choi , Sang-Gab Kim , Chang-Ho Jeong , Shin-Il Choi , Hong-Kee Chin , Yu-Gwang Jeong , Dong-Ju Yang
IPC分类号： H01L21/84
CPC分类号： H01L27/12 , G02F2001/136295 , H01L27/124 , H01L29/458
摘要： In a display panel and a method of manufacturing the display panel, a gate line, a data line, and source and drain electrodes including a same material as the data line are formed on a substrate constituting the display panel, and the data line includes an aluminum based alloy containing sufficient nickel to inhibit corrosion during dry etching. The corrosion resistance of the AlNi-containing alloy helps prevent corrosion of the data line, the source electrode, and the drain electrode during selective dry etching that shapes these lines and electrodes.
摘要翻译：在显示面板和制造显示面板的方法中，在构成显示面板的基板上形成包括与数据线相同材料的栅极线，数据线以及源极和漏极，并且数据线包括铝基合金含有足够的镍以在干蚀刻期间抑制腐蚀。含有AlNi的合金的耐腐蚀性有助于防止在形成这些线和电极的选择性干蚀刻期间数据线，源电极和漏电极的腐蚀。

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