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1. 发明授权

US06884736B2 Method of forming contact plug on silicide structure 有权
标题翻译：在硅化物结构上形成接触塞的方法
公开(公告)号：US06884736B2
公开(公告)日：2005-04-26
申请号：US10265937
申请日：2002-10-07
申请人： Chii-Ming Wu , Mei-Yun Wang , Chih-Wei Chang , Chin-Hwa Hsieh , Shau-Lin Shue , Chu-Yun Fu , Ju-Wang Hsu , Ming-Huan Tsai , Yuan-Hung Chiu
发明人： Chii-Ming Wu , Mei-Yun Wang , Chih-Wei Chang , Chin-Hwa Hsieh , Shau-Lin Shue , Chu-Yun Fu , Ju-Wang Hsu , Ming-Huan Tsai , Yuan-Hung Chiu
IPC分类号： H01L21/311 , H01L21/60 , H01L21/768 , H01L21/302
CPC分类号： H01L21/76829 , H01L21/31105 , H01L21/31116 , H01L21/76802 , H01L21/76832
摘要： A method of manufacturing a semiconductor device is provided. A semiconductor element is formed on a substrate. The semiconductor element has at least one nickel silicide contact region, an etch stop layer formed over said element, and an insulating layer formed over said etch stop layer. A portion of the etch stop layer immediately over a selected contact region is removed using a process that does not substantially react with the contact region, to form a contact opening. The contact opening is then filled with a conductive material to form a contact.
摘要翻译：提供一种制造半导体器件的方法。半导体元件形成在基板上。半导体元件具有至少一个硅化镍接触区，在所述元件上形成的蚀刻停止层，以及形成在所述蚀刻停止层上的绝缘层。使用基本上不与接触区域反应的方法去除在所选择的接触区域上方的蚀刻停止层的一部分，以形成接触开口。然后用导电材料填充接触开口以形成接触。

2. 发明授权

US07256137B2 Method of forming contact plug on silicide structure 有权
标题翻译：在硅化物结构上形成接触塞的方法
公开(公告)号：US07256137B2
公开(公告)日：2007-08-14
申请号：US11052938
申请日：2005-02-07
申请人： Chii-Ming Wu , Chih-Wei Chang , Shau-Lin Shue , Ju-Wang Hsu , Ming-Huan Tsai
发明人： Chii-Ming Wu , Chih-Wei Chang , Shau-Lin Shue , Ju-Wang Hsu , Ming-Huan Tsai
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/76829 , H01L21/31105 , H01L21/31116 , H01L21/76802 , H01L21/76832
摘要： A method of manufacturing a semiconductor device is provided comprising the steps of: (a) forming a semiconductor element on a substrate, the semiconductor element having at least one nickel silicide contact region, a first etch stop layer formed over the element and an insulating layer formed over the first etch stop layer; (b) forming an opening through the insulating layer over the contact region at least to the first etch stop layer; (c) removing a portion of the first etch stop layer contacting a selected contact region using a process that does not substantially oxidize with the contact region, to form a contact opening to the contact region; and (d) filling the contact opening with conductive material to form a contact.
摘要翻译：提供一种制造半导体器件的方法，包括以下步骤：（a）在衬底上形成半导体元件，所述半导体元件具有至少一个硅化镍接触区域，形成在元件上的第一蚀刻停止层和绝缘层形成在第一蚀刻停止层上; （b）至少在所述第一蚀刻停止层上在所述接触区域上形成穿过所述绝缘层的开口; （c）使用不与接触区域基本上氧化的工艺去除与所选择的接触区域接触的第一蚀刻停止层的一部分，以形成到接触区域的接触开口; 和（d）用导电材料填充接触开口以形成接触。

3. 发明申请

US20050158986A1 Method of forming contact plug on silicide structure 有权
标题翻译：在硅化物结构上形成接触塞的方法
公开(公告)号：US20050158986A1
公开(公告)日：2005-07-21
申请号：US11052938
申请日：2005-02-07
申请人： Chii-Ming Wu , Chih-Wei Chang , Shau-Lin Shue , Ju-Wang Hsu , Ming-Huan Tsai
发明人： Chii-Ming Wu , Chih-Wei Chang , Shau-Lin Shue , Ju-Wang Hsu , Ming-Huan Tsai
IPC分类号： H01L21/311 , H01L21/60 , H01L21/768 , H01L21/20 , H01L21/4763
CPC分类号： H01L21/76829 , H01L21/31105 , H01L21/31116 , H01L21/76802 , H01L21/76832
摘要： A method of manufacturing a semiconductor device is provided comprising the steps of: (a) forming a semiconductor element on a substrate, the semiconductor element having at least one nickel silicide contact region, a first etch stop layer formed over the element and an insulating layer formed over the first etch stop layer; (b) forming an opening through the insulating layer over the contact region at least to the first etch stop layer; (c) removing a portion of the first etch stop layer contacting a selected contact region using a process that does not substantially oxidize with the contact region, to form a contact opening to the contact region; and (d) filling the contact opening with conductive material to form a contact.
摘要翻译：提供一种制造半导体器件的方法，包括以下步骤：（a）在衬底上形成半导体元件，所述半导体元件具有至少一个硅化镍接触区域，形成在元件上的第一蚀刻停止层和绝缘层形成在第一蚀刻停止层上; （b）至少在所述第一蚀刻停止层上在所述接触区域上形成穿过所述绝缘层的开口; （c）使用不与接触区域基本上氧化的工艺去除与所选择的接触区域接触的第一蚀刻停止层的一部分，以形成到接触区域的接触开口; 和（d）用导电材料填充接触开口以形成接触。

4. 发明授权

US08569139B2 Method of manufacturing strained source/drain structures 有权
公开(公告)号：US08569139B2
公开(公告)日：2013-10-29
申请号：US12913041
申请日：2010-10-27
申请人： Chun-Feng Nieh , Ming-Huan Tsai , Wei-Han Fan , Yimin Huang , Chun-Fai Cheng , Han-Ting Tsai , Chii-Ming Wu
发明人： Chun-Feng Nieh , Ming-Huan Tsai , Wei-Han Fan , Yimin Huang , Chun-Fai Cheng , Han-Ting Tsai , Chii-Ming Wu
IPC分类号： H01L21/336 , H01L21/461
CPC分类号： H01L21/823814 , H01L21/26586 , H01L21/30604 , H01L21/3065 , H01L21/76224 , H01L21/823807 , H01L21/823878 , H01L29/66492 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of an integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite to the LDD region.

5. 发明授权

US06410424B1 Process flow to optimize profile of ultra small size photo resist free contact 有权
标题翻译：工艺流程优化超小尺寸光刻胶的自由接触
公开(公告)号：US06410424B1
公开(公告)日：2002-06-25
申请号：US09837599
申请日：2001-04-19
申请人： Ming-Huan Tsai , Chung-Long Chang , Chii-Ming Wu , Hun-Jan Tao
发明人： Ming-Huan Tsai , Chung-Long Chang , Chii-Ming Wu , Hun-Jan Tao
IPC分类号： H01L214763
CPC分类号： H01L21/76804 , H01L21/76802 , H01L21/76814 , H01L21/76829 , H01L21/76831 , Y10S438/975
摘要： A new processing sequence is provided for the creation of openings in layers of dielectric. Over a semiconductor surface are successively deposited an etch stop layer, a layer of dielectric and a hard mask layer. An opening is etched in the hard mask layer, the main opening is etched through the layer of dielectric and the etch stop layer. The surface is wet cleaned, after which a thin layer of silicon oxide is CVD deposited over the inside surfaces of the created opening. This thin layer of CVD oxide is subjected to argon sputter, providing of the critical dimensions of the upper region of the opening. Then the process continues with the deposition of the barrier metal, the filling of the opening with a conducting material to create the metal plug and the polishing of the surface of the deposited conducting material.
摘要翻译：提供了一种新的处理顺序，用于在电介质层中产生开口。在半导体表面上依次沉积蚀刻停止层，电介质层和硬掩模层。在硬掩模层中蚀刻开口，通过电介质层和蚀刻停止层蚀刻主开口。表面被湿清洗，之后在所产生的开口的内表面上CVD沉积薄层的氧化硅。对CVD氧化物薄层进行氩溅射，提供开口上部区域的临界尺寸。然后，该过程继续阻挡金属的沉积，用导电材料填充开口以产生金属塞和抛光沉积的导电材料的表面。

6. 发明申请

US20050127459A1 Novel gate structure and method of forming the gate dielectric with mini-spacer 审中-公开
标题翻译：具有微型间隔物形成栅极电介质的新型栅极结构和方法
公开(公告)号：US20050127459A1
公开(公告)日：2005-06-16
申请号：US11048205
申请日：2005-02-01
申请人： Yuan-Hung Chiu , Ming-Huan Tsai , Fang-Cheng Chen , Hun-Jan Tao
发明人： Yuan-Hung Chiu , Ming-Huan Tsai , Fang-Cheng Chen , Hun-Jan Tao
IPC分类号： H01L21/265 , H01L21/8238 , H01L29/78 , H01L29/80
CPC分类号： H01L21/2652 , H01L29/517 , H01L29/518 , H01L29/78
摘要： A field effect transistor gate structure and a method of fabricating the gate structure with a high-k gate dielectric material and high-k spacer are described. A gate pattern or trench is first etched in a dummy organic or inorganic film deposited over a silicon substrate with source/drain regions. A high-k dielectric material liner is then deposited on all exposed surfaces. Excess poly-silicon gate conductor film is then deposited within and over the trench to provide adequate overburden. Poly-silicon is then planarized with chemical mechanical polishing or etch-back methods such that the high-k material film on top of the dummy film surface is removed during this step. In the final step, the dummy film is disposed off, leaving the final transistor gate structure with high-k gate dielectric and high-k spacer surrounding the gate conductor poly-silicon, with the entire gate structure fabricated to form an FET device on a silicon substrate.
摘要翻译：描述了场效应晶体管栅极结构和制造具有高k栅极介电材料和高k隔离物的栅极结构的方法。首先在具有源极/漏极区域的硅衬底上沉积的虚拟有机或无机膜中蚀刻栅极图案或沟槽。然后将高k电介质材料衬垫沉积在所有暴露的表面上。然后将过多的多晶硅栅极导体膜沉积在沟槽内和沟槽上，以提供足够的覆盖层。然后通过化学机械抛光或蚀刻方法对多晶硅进行平面化，使得在该步骤期间去除虚拟膜表面顶部的高k材料膜。在最后的步骤中，将虚设薄膜放开，留下最终的晶体管栅极结构，其中高k栅极电介质和围绕栅极导体多晶硅的高k隔离层，整个栅极结构被制成以形成FET器件硅衬底。

7. 发明授权

US08236659B2 Source and drain feature profile for improving device performance and method of manufacturing same 有权
标题翻译：源极和漏极特征轮廓，用于提高器件性能及其制造方法
公开(公告)号：US08236659B2
公开(公告)日：2012-08-07
申请号：US12816519
申请日：2010-06-16
申请人： Ming-Huan Tsai , Chun-Fai Cheng , Hui Ouyang , Yuan-Hung Chiu , Yen-Ming Chen
发明人： Ming-Huan Tsai , Chun-Fai Cheng , Hui Ouyang , Yuan-Hung Chiu , Yen-Ming Chen
IPC分类号： H01L21/336
CPC分类号： H01L29/66515 , H01L21/265 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.
摘要翻译：公开了一种用于制造集成电路器件的集成电路器件和方法。所公开的方法提供对集成电路器件的表面接近度和尖端深度的改进的控制。在一个实施例中，该方法通过在器件的源极和漏极区域中形成掺杂区域和轻掺杂源极和漏极（LDD）区域来实现改进的控制。掺杂区域注入与LDD区域相反的掺杂剂类型。

8. 发明授权

US06867084B1 Gate structure and method of forming the gate dielectric with mini-spacer 有权
标题翻译：用微型间隔物形成栅极电介质的栅结构和方法
公开(公告)号：US06867084B1
公开(公告)日：2005-03-15
申请号：US10263541
申请日：2002-10-03
申请人： Yuan-Hung Chiu , Ming-Huan Tsai , Fang-Cheng Chen , Hun-Jan Tao
发明人： Yuan-Hung Chiu , Ming-Huan Tsai , Fang-Cheng Chen , Hun-Jan Tao
IPC分类号： H01L21/265 , H01L21/8238 , H01L29/78 , H01L29/80
CPC分类号： H01L21/2652 , H01L29/517 , H01L29/518 , H01L29/78
摘要： A field effect transistor gate structure and a method of fabricating the gate structure with a high-k gate dielectric material and high-k spacer are described. A gate pattern or trench is first etched in a dummy organic or inorganic film deposited over a silicon substrate with source/drain regions. A high-k dielectric material liner is then deposited on all exposed surfaces. Excess poly-silicon gate conductor film is then deposited within and over the trench to provide adequate overburden. Poly-silicon is then planarized with chemical mechanical polishing or etch-back methods such that the high-k material film on top of the dummy film surface is removed during this step. In the final step, the dummy film is disposed off, leaving the final transistor gate structure with high-k gate dielectric and high-k spacer surrounding the gate conductor poly-silicon, with the entire gate structure fabricated to form an FET device on a silicon substrate.
摘要翻译：描述了场效应晶体管栅极结构和制造具有高k栅极介电材料和高k隔离物的栅极结构的方法。首先在具有源极/漏极区域的硅衬底上沉积的虚拟有机或无机膜中蚀刻栅极图案或沟槽。然后将高k电介质材料衬垫沉积在所有暴露的表面上。然后将过多的多晶硅栅极导体膜沉积在沟槽内和沟槽上，以提供足够的覆盖层。然后通过化学机械抛光或蚀刻方法对多晶硅进行平面化，使得在该步骤期间去除虚拟膜表面顶部的高k材料膜。在最后的步骤中，将虚设薄膜放开，留下最终的晶体管栅极结构，其中高k栅极电介质和围绕栅极导体多晶硅的高k隔离层，整个栅极结构被制成以形成FET器件硅衬底。

9. 发明授权

US08614132B2 Integrated circuit device with well controlled surface proximity and method of manufacturing same 有权
标题翻译：具有良好控制的表面接近的集成电路器件及其制造方法
公开(公告)号：US08614132B2
公开(公告)日：2013-12-24
申请号：US13240025
申请日：2011-09-22
申请人： Ming-Huan Tsai , Chun-Fai Cheng , Hui Ouyang , Yuan-Hung Chiu , Yen-Ming Chen
发明人： Ming-Huan Tsai , Chun-Fai Cheng , Hui Ouyang , Yuan-Hung Chiu , Yen-Ming Chen
IPC分类号： H01L21/336
CPC分类号： H01L29/66515 , H01L21/265 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.
摘要翻译：公开了一种用于制造集成电路器件的集成电路器件和方法。所公开的方法提供对集成电路器件的表面接近度和尖端深度的改进的控制。在一个实施例中，该方法通过在器件的源极和漏极区域中形成掺杂区域和轻掺杂源极和漏极（LDD）区域来实现改进的控制。掺杂区域注入与LDD区域相反的掺杂剂类型。

10. 发明申请

US20050092348A1 Method for cleaning an integrated circuit device using an aqueous cleaning composition 审中-公开
标题翻译：使用水性清洁组合物清洁集成电路装置的方法
公开(公告)号：US20050092348A1
公开(公告)日：2005-05-05
申请号：US10701708
申请日：2003-11-05
申请人： Ju-Chien Chiang , Ming-Huan Tsai , Huan-Just Lin , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Ju-Chien Chiang , Ming-Huan Tsai , Huan-Just Lin , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： B08B3/08 , B08B3/12 , C11D3/39 , C11D7/08 , C11D11/00 , H01L21/306 , H01L21/311
CPC分类号： H01L21/02052 , B08B3/08 , B08B3/12 , C11D3/3947 , C11D7/08 , C11D11/0047 , H01L21/31122
摘要： The present invention provides aqueous compositions for cleaning integrated circuit substrates. Specifically, in the cleaning of an integrated circuit substrate, disclosed is a method for removing the by-products of the high-k dielectric dry etch process from the integrated circuit substrate, the method including: contacting the integrated circuit substrate with an aqueous composition including an amount, effective for the purpose of a (a) hydrogen fluoride, followed by (b) a mixture of hydrogen peroxide with a compound selected from the group consisting of ammonium hydroxide, hydrochloric acid and sulfuric acid.
摘要翻译：本发明提供用于清洁集成电路基板的水性组合物。具体地，在集成电路基板的清洗中，公开了从集成电路基板除去高介电常数干蚀刻工艺的副产物的方法，该方法包括：使集成电路基板与水性组合物接触，所述水性组合物包括（a）氟化氢，其次是（b）过氧化氢与选自氢氧化铵，盐酸和硫酸的化合物的混合物的量。

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