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1. 发明授权

US06884736B2 Method of forming contact plug on silicide structure 有权
标题翻译：在硅化物结构上形成接触塞的方法
公开(公告)号：US06884736B2
公开(公告)日：2005-04-26
申请号：US10265937
申请日：2002-10-07
申请人： Chii-Ming Wu , Mei-Yun Wang , Chih-Wei Chang , Chin-Hwa Hsieh , Shau-Lin Shue , Chu-Yun Fu , Ju-Wang Hsu , Ming-Huan Tsai , Yuan-Hung Chiu
发明人： Chii-Ming Wu , Mei-Yun Wang , Chih-Wei Chang , Chin-Hwa Hsieh , Shau-Lin Shue , Chu-Yun Fu , Ju-Wang Hsu , Ming-Huan Tsai , Yuan-Hung Chiu
IPC分类号： H01L21/311 , H01L21/60 , H01L21/768 , H01L21/302
CPC分类号： H01L21/76829 , H01L21/31105 , H01L21/31116 , H01L21/76802 , H01L21/76832
摘要： A method of manufacturing a semiconductor device is provided. A semiconductor element is formed on a substrate. The semiconductor element has at least one nickel silicide contact region, an etch stop layer formed over said element, and an insulating layer formed over said etch stop layer. A portion of the etch stop layer immediately over a selected contact region is removed using a process that does not substantially react with the contact region, to form a contact opening. The contact opening is then filled with a conductive material to form a contact.
摘要翻译：提供一种制造半导体器件的方法。半导体元件形成在基板上。半导体元件具有至少一个硅化镍接触区，在所述元件上形成的蚀刻停止层，以及形成在所述蚀刻停止层上的绝缘层。使用基本上不与接触区域反应的方法去除在所选择的接触区域上方的蚀刻停止层的一部分，以形成接触开口。然后用导电材料填充接触开口以形成接触。

2. 发明授权

US08236659B2 Source and drain feature profile for improving device performance and method of manufacturing same 有权
标题翻译：源极和漏极特征轮廓，用于提高器件性能及其制造方法
公开(公告)号：US08236659B2
公开(公告)日：2012-08-07
申请号：US12816519
申请日：2010-06-16
申请人： Ming-Huan Tsai , Chun-Fai Cheng , Hui Ouyang , Yuan-Hung Chiu , Yen-Ming Chen
发明人： Ming-Huan Tsai , Chun-Fai Cheng , Hui Ouyang , Yuan-Hung Chiu , Yen-Ming Chen
IPC分类号： H01L21/336
CPC分类号： H01L29/66515 , H01L21/265 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.
摘要翻译：公开了一种用于制造集成电路器件的集成电路器件和方法。所公开的方法提供对集成电路器件的表面接近度和尖端深度的改进的控制。在一个实施例中，该方法通过在器件的源极和漏极区域中形成掺杂区域和轻掺杂源极和漏极（LDD）区域来实现改进的控制。掺杂区域注入与LDD区域相反的掺杂剂类型。

3. 发明授权

US06867084B1 Gate structure and method of forming the gate dielectric with mini-spacer 有权
标题翻译：用微型间隔物形成栅极电介质的栅结构和方法
公开(公告)号：US06867084B1
公开(公告)日：2005-03-15
申请号：US10263541
申请日：2002-10-03
申请人： Yuan-Hung Chiu , Ming-Huan Tsai , Fang-Cheng Chen , Hun-Jan Tao
发明人： Yuan-Hung Chiu , Ming-Huan Tsai , Fang-Cheng Chen , Hun-Jan Tao
IPC分类号： H01L21/265 , H01L21/8238 , H01L29/78 , H01L29/80
CPC分类号： H01L21/2652 , H01L29/517 , H01L29/518 , H01L29/78
摘要： A field effect transistor gate structure and a method of fabricating the gate structure with a high-k gate dielectric material and high-k spacer are described. A gate pattern or trench is first etched in a dummy organic or inorganic film deposited over a silicon substrate with source/drain regions. A high-k dielectric material liner is then deposited on all exposed surfaces. Excess poly-silicon gate conductor film is then deposited within and over the trench to provide adequate overburden. Poly-silicon is then planarized with chemical mechanical polishing or etch-back methods such that the high-k material film on top of the dummy film surface is removed during this step. In the final step, the dummy film is disposed off, leaving the final transistor gate structure with high-k gate dielectric and high-k spacer surrounding the gate conductor poly-silicon, with the entire gate structure fabricated to form an FET device on a silicon substrate.
摘要翻译：描述了场效应晶体管栅极结构和制造具有高k栅极介电材料和高k隔离物的栅极结构的方法。首先在具有源极/漏极区域的硅衬底上沉积的虚拟有机或无机膜中蚀刻栅极图案或沟槽。然后将高k电介质材料衬垫沉积在所有暴露的表面上。然后将过多的多晶硅栅极导体膜沉积在沟槽内和沟槽上，以提供足够的覆盖层。然后通过化学机械抛光或蚀刻方法对多晶硅进行平面化，使得在该步骤期间去除虚拟膜表面顶部的高k材料膜。在最后的步骤中，将虚设薄膜放开，留下最终的晶体管栅极结构，其中高k栅极电介质和围绕栅极导体多晶硅的高k隔离层，整个栅极结构被制成以形成FET器件硅衬底。

4. 发明授权

US08614132B2 Integrated circuit device with well controlled surface proximity and method of manufacturing same 有权
标题翻译：具有良好控制的表面接近的集成电路器件及其制造方法
公开(公告)号：US08614132B2
公开(公告)日：2013-12-24
申请号：US13240025
申请日：2011-09-22
申请人： Ming-Huan Tsai , Chun-Fai Cheng , Hui Ouyang , Yuan-Hung Chiu , Yen-Ming Chen
发明人： Ming-Huan Tsai , Chun-Fai Cheng , Hui Ouyang , Yuan-Hung Chiu , Yen-Ming Chen
IPC分类号： H01L21/336
CPC分类号： H01L29/66515 , H01L21/265 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.
摘要翻译：公开了一种用于制造集成电路器件的集成电路器件和方法。所公开的方法提供对集成电路器件的表面接近度和尖端深度的改进的控制。在一个实施例中，该方法通过在器件的源极和漏极区域中形成掺杂区域和轻掺杂源极和漏极（LDD）区域来实现改进的控制。掺杂区域注入与LDD区域相反的掺杂剂类型。

5. 发明申请

US20050092348A1 Method for cleaning an integrated circuit device using an aqueous cleaning composition 审中-公开
标题翻译：使用水性清洁组合物清洁集成电路装置的方法
公开(公告)号：US20050092348A1
公开(公告)日：2005-05-05
申请号：US10701708
申请日：2003-11-05
申请人： Ju-Chien Chiang , Ming-Huan Tsai , Huan-Just Lin , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Ju-Chien Chiang , Ming-Huan Tsai , Huan-Just Lin , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： B08B3/08 , B08B3/12 , C11D3/39 , C11D7/08 , C11D11/00 , H01L21/306 , H01L21/311
CPC分类号： H01L21/02052 , B08B3/08 , B08B3/12 , C11D3/3947 , C11D7/08 , C11D11/0047 , H01L21/31122
摘要： The present invention provides aqueous compositions for cleaning integrated circuit substrates. Specifically, in the cleaning of an integrated circuit substrate, disclosed is a method for removing the by-products of the high-k dielectric dry etch process from the integrated circuit substrate, the method including: contacting the integrated circuit substrate with an aqueous composition including an amount, effective for the purpose of a (a) hydrogen fluoride, followed by (b) a mixture of hydrogen peroxide with a compound selected from the group consisting of ammonium hydroxide, hydrochloric acid and sulfuric acid.
摘要翻译：本发明提供用于清洁集成电路基板的水性组合物。具体地，在集成电路基板的清洗中，公开了从集成电路基板除去高介电常数干蚀刻工艺的副产物的方法，该方法包括：使集成电路基板与水性组合物接触，所述水性组合物包括（a）氟化氢，其次是（b）过氧化氢与选自氢氧化铵，盐酸和硫酸的化合物的混合物的量。

6. 发明申请

US20050081781A1 Fully dry, Si recess free process for removing high k dielectric layer 审中-公开
标题翻译：完全干燥，Si无凹槽工艺，用于去除高k电介质层
公开(公告)号：US20050081781A1
公开(公告)日：2005-04-21
申请号：US10688045
申请日：2003-10-17
申请人： Huan-Just Lin , Ming-Huan Tsai , Li-Te Lin , Yuan-Hung Chiu , Han-Jan Tao
发明人： Huan-Just Lin , Ming-Huan Tsai , Li-Te Lin , Yuan-Hung Chiu , Han-Jan Tao
IPC分类号： C30B23/00 , C30B25/00 , C30B28/12 , C30B28/14 , H01L21/28 , H01L21/311 , H01L21/316 , H01L29/49 , H01L29/51
CPC分类号： H01L29/517 , H01L21/28079 , H01L21/28088 , H01L21/28194 , H01L21/31122 , H01L21/31645 , H01L29/495 , H01L29/4966 , H01L29/513
摘要： A fully dry etch method is described for removing a high k dielectric layer from a substrate without damaging the substrate and has a high selectivity with respect to a gate layer. The etch is comprised of BCl3, a fluorocarbon, and an inert gas. A low RF bias power is preferred. The method can also be used to remove an interfacial layer between the substrate and the high k dielectric layer. A HfO2 etch rate of 55 Angstroms per minute is achieved without causing a recess in a silicon substrate and with an etch selectivity to polysilicon of greater than 10:1. Better STI oxide divot control is also provided by this method. The etch through the high k dielectric layer may be performed in the same etch chamber as the etch process to form a gate electrode.
摘要翻译：描述了用于从衬底去除高k电介质层而不损坏衬底并且相对于栅极层具有高选择性的全干蚀刻方法。蚀刻由BCl 3 3，碳氟化合物和惰性气体组成。低RF偏置功率是优选的。该方法也可以用于去除衬底和高k电介质层之间的界面层。实现了每分钟55埃的HfO 2/2蚀刻速率，而不会在硅衬底中产生凹陷，并且对多晶硅的蚀刻选择性大于10:1。该方法也提供更好的STI氧化物控制。通过高k介电层的蚀刻可以在与蚀刻工艺相同的蚀刻室中进行以形成栅电极。

7. 发明申请

US20050127459A1 Novel gate structure and method of forming the gate dielectric with mini-spacer 审中-公开
标题翻译：具有微型间隔物形成栅极电介质的新型栅极结构和方法
公开(公告)号：US20050127459A1
公开(公告)日：2005-06-16
申请号：US11048205
申请日：2005-02-01
申请人： Yuan-Hung Chiu , Ming-Huan Tsai , Fang-Cheng Chen , Hun-Jan Tao
发明人： Yuan-Hung Chiu , Ming-Huan Tsai , Fang-Cheng Chen , Hun-Jan Tao
IPC分类号： H01L21/265 , H01L21/8238 , H01L29/78 , H01L29/80
CPC分类号： H01L21/2652 , H01L29/517 , H01L29/518 , H01L29/78
摘要： A field effect transistor gate structure and a method of fabricating the gate structure with a high-k gate dielectric material and high-k spacer are described. A gate pattern or trench is first etched in a dummy organic or inorganic film deposited over a silicon substrate with source/drain regions. A high-k dielectric material liner is then deposited on all exposed surfaces. Excess poly-silicon gate conductor film is then deposited within and over the trench to provide adequate overburden. Poly-silicon is then planarized with chemical mechanical polishing or etch-back methods such that the high-k material film on top of the dummy film surface is removed during this step. In the final step, the dummy film is disposed off, leaving the final transistor gate structure with high-k gate dielectric and high-k spacer surrounding the gate conductor poly-silicon, with the entire gate structure fabricated to form an FET device on a silicon substrate.
摘要翻译：描述了场效应晶体管栅极结构和制造具有高k栅极介电材料和高k隔离物的栅极结构的方法。首先在具有源极/漏极区域的硅衬底上沉积的虚拟有机或无机膜中蚀刻栅极图案或沟槽。然后将高k电介质材料衬垫沉积在所有暴露的表面上。然后将过多的多晶硅栅极导体膜沉积在沟槽内和沟槽上，以提供足够的覆盖层。然后通过化学机械抛光或蚀刻方法对多晶硅进行平面化，使得在该步骤期间去除虚拟膜表面顶部的高k材料膜。在最后的步骤中，将虚设薄膜放开，留下最终的晶体管栅极结构，其中高k栅极电介质和围绕栅极导体多晶硅的高k隔离层，整个栅极结构被制成以形成FET器件硅衬底。

8. 发明申请

US20110312145A1 SOURCE AND DRAIN FEATURE PROFILE FOR IMPROVING DEVICE PERFORMANCE AND METHOD OF MANUFACTURING SAME 有权
标题翻译：用于改进装置性能的源和排出特征轮廓及其制造方法
公开(公告)号：US20110312145A1
公开(公告)日：2011-12-22
申请号：US12816519
申请日：2010-06-16
申请人： Ming-Huan Tsai , Chun-Fai Cheng , Hui Ouyang , Yuan-Hung Chiu , Yen-Ming Chen
发明人： Ming-Huan Tsai , Chun-Fai Cheng , Hui Ouyang , Yuan-Hung Chiu , Yen-Ming Chen
IPC分类号： H01L21/336
CPC分类号： H01L29/66515 , H01L21/265 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.
摘要翻译：公开了一种用于制造集成电路器件的集成电路器件和方法。所公开的方法提供对集成电路器件的表面接近度和尖端深度的改进的控制。在一个实施例中，该方法通过在器件的源极和漏极区域中形成掺杂区域和轻掺杂源极和漏极（LDD）区域来实现改进的控制。掺杂区域注入与LDD区域相反的掺杂剂类型。

9. 发明授权

US07078351B2 Photoresist intensive patterning and processing 失效
标题翻译：光刻胶强化图案和加工
公开(公告)号：US07078351B2
公开(公告)日：2006-07-18
申请号：US10361875
申请日：2003-02-10
申请人： Yuan-Hung Chiu , Ming-Huan Tsai , Hun-Jan Tao , Jeng-Horng Chen
发明人： Yuan-Hung Chiu , Ming-Huan Tsai , Hun-Jan Tao , Jeng-Horng Chen
IPC分类号： H01L21/302
CPC分类号： H01L21/0276 , H01L21/0332 , H01L21/30604 , H01L21/3081 , H01L21/31116 , H01L21/31144 , H01L21/3144 , H01L21/3145 , H01L21/76802
摘要： A layer of Anti Reflective Coating (ARC) is first deposited over the surface of a silicon based or oxide based semiconductor surface, a dual hardmask is deposited over the surface of the layer of ARC. A layer of soft mask material is next coated over the surface of the dual hardmask layer, the layer of soft mask material is exposed, creating a soft mask material mask. The upper layer of the dual hardmask layer is next patterned in accordance with the soft mask material mask, the soft mask material mask is removed from the surface. The lower layer of the hardmask layer is then patterned after which the layer of ARC is patterned, both layers are patterned in accordance with the patterned upper layer of the dual hardmask layer. The substrate is now patterned in accordance with the patterned upper and lower layer of the dual hardmask layer and the patterned layer of ARC. The patterned upper and lower layers of the hardmask layer and the patterned layer of ARC are removed from the surface of the silicon based or oxide based semiconductor surface.
摘要翻译：首先将抗反射涂层（ARC）沉积在硅基或氧化物基半导体表面的表面上，双重硬掩模沉积在ARC层的表面上。然后将一层软掩模材料涂覆在双重硬掩模层的表面上，该软掩模材料层被暴露，形成柔软的掩模材料掩模。根据软掩模材料掩模，双硬掩模层的上层接下来图案化，从表面去除软掩模材料掩模。然后对硬掩模层的下层进行图案化，之后对ARC层进行构图，根据双重硬掩模层的图案化上层对两层进行图案化。衬底现在根据双重硬掩模层的图案化的上下层和ARC的图案化层进行图案化。从硅基或氧化物基半导体表面的表面去除硬掩模层的图案化的上层和下层以及ARC的图案化层。

10. 发明授权

US06407002B1 Partial resist free approach in contact etch to improve W-filling 有权
标题翻译：接触蚀刻中的部分抗光蚀刻方法，以改善W填充
公开(公告)号：US06407002B1
公开(公告)日：2002-06-18
申请号：US09636583
申请日：2000-08-10
申请人： Li-Te Lin , Yuan-Hung Chiu , Ming-Huan Tsai , Hun-Jan Tao
发明人： Li-Te Lin , Yuan-Hung Chiu , Ming-Huan Tsai , Hun-Jan Tao
IPC分类号： H01L21302
CPC分类号： H01L21/31144 , H01L21/31138 , H01L21/76804 , H01L21/76829 , H01L21/76877
摘要： A method is provided for improving the tungsten, W-filling of hole openings in semiconductor substrates. This is accomplished by forming an opening—which can be used either as a contact or via hole—with a faceted entrance along with tapered side-walls. This combination of faceted entrance and tapered side-walls improves substantially the tungsten W-filling of contact/via holes in substrates without the formation of key-holes, thereby resulting in metal plugs of high electrical integrity and high reliability.
摘要翻译：提供了一种提高半导体衬底中的开孔的钨，W填充的方法。这可以通过形成开口来实现，该开口可以作为接触或通孔使用，与开口的入口以及锥形侧壁一起使用。面形入口和锥形侧壁的这种组合基本上改善了衬底中的接触/通孔的钨W填充，而没有形成键孔，从而导致高电气完整性和高可靠性的金属插头。

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