专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06426470B1 Formation of multisegmented plated through holes 有权
标题翻译：多段电镀通孔的形成
公开(公告)号：US06426470B1
公开(公告)日：2002-07-30
申请号：US09764464
申请日：2001-01-17
申请人： Donald S. Farquhar , Robert M. Japp , John M. Lauffer , Konstantinos I. Papathomas
发明人： Donald S. Farquhar , Robert M. Japp , John M. Lauffer , Konstantinos I. Papathomas
IPC分类号： H05K111
CPC分类号： H05K3/429 , H05K2201/0187 , H05K2201/096 , H05K2201/09645 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165 , Y10T428/24917
摘要： A method and structure relating to multisegmented plated through holes. A substrate includes a dielectric layer sandwiched between a first laminate layer and a second laminate layer. A through hole is formed through the substrate. The through hole passes through nonplatable dielectric material within the dielectric layer. As a result, subsequent seeding and electroplating of the through hole results in a conductive metal plating forming at a wall of the through hole on a segment of the first laminate layer and on a segment of the second laminate layer, but not on the nonplatable dielectric material of the dielectric layer. Thus, the conductive metal plating is not continuous from the first laminate layer to the second laminate layer.
摘要翻译：涉及多段电镀通孔的方法和结构。基板包括夹在第一层叠层和第二层叠层之间的电介质层。穿过基板形成通孔。通孔穿过介电层内的不可电介质材料。结果，随后的通孔的接种和电镀导致在第一层压层的段上的通孔的壁上和第二层压层的段上形成导电金属电镀，而不在不可电绝缘的电介质电介质层的材料。因此，导电金属电镀从第一层叠层到第二层叠层不是连续的。

2. 发明授权

US06996903B2 Formation of multisegmented plated through holes 失效
公开(公告)号：US06996903B2
公开(公告)日：2006-02-14
申请号：US10641182
申请日：2003-08-14
申请人： Donald S. Farquhar , Robert M. Japp , John M. Lauffer , Konstantinos I. Papathomas
发明人： Donald S. Farquhar , Robert M. Japp , John M. Lauffer , Konstantinos I. Papathomas
IPC分类号： H01K3/10
CPC分类号： H05K3/429 , H05K2201/0187 , H05K2201/096 , H05K2201/09645 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165 , Y10T428/24917
摘要： A method and structure relating to multisegmented plated through holes. A substrate includes a dielectric layer sandwiched between a first laminate layer and a second laminate layer. A through hole is formed through the substrate. The through hole passes through nonplatable dielectric material within the dielectric layer. As a result, subsequent seeding and electroplating of the through hole results in a conductive metal plating forming at a wall of the through hole on a segment of the first laminate layer and on a segment of the second laminate layer, but not on the nonplatable dielectric material of the dielectric layer. Thus, the conductive metal plating is not continuous from the first laminate layer to the second laminate layer.

3. 发明授权

US06700078B2 Formation of multisegmented plated through holes 失效
标题翻译：多段电镀通孔的形成
公开(公告)号：US06700078B2
公开(公告)日：2004-03-02
申请号：US10176254
申请日：2002-06-19
申请人： Donald S. Farquhar , Robert M. Japp , John M. Lauffer , Konstantinos I. Papathomas
发明人： Donald S. Farquhar , Robert M. Japp , John M. Lauffer , Konstantinos I. Papathomas
IPC分类号： H05K116
CPC分类号： H05K3/429 , H05K2201/0187 , H05K2201/096 , H05K2201/09645 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165 , Y10T428/24917
摘要： A method and structure relating to multisegmented plated through holes. A substrate includes a dielectric layer sandwiched between a first laminate layer and a second laminate layer. A through hole is formed through the substrate. The through hole passes through nonplatable dielectric material within the dielectric layer. As a result, subsequent seeding and electroplating of the through hole results in a conductive metal plating forming at a wall of the through hole on a segment of the first laminate layer and on a segment of the second laminate layer, but not on the nonplatable dielectric material of the dielectric layer. Thus, the conductive metal plating is not continuous from the first laminate layer to the second laminate layer.
摘要翻译：涉及多段电镀通孔的方法和结构。基板包括夹在第一层叠层和第二层叠层之间的电介质层。穿过基板形成通孔。通孔穿过介电层内的不可电介质材料。结果，随后的通孔的接种和电镀导致在第一层压层的段上的通孔的壁上和第二层压层的段上形成导电金属电镀，而不在不可电绝缘的电介质电介质层的材料。因此，导电金属电镀从第一层叠层到第二层叠层不是连续的。

4. 发明授权

US06343001B1 Multilayer capacitance structure and circuit board containing the same 失效
标题翻译：包含多层电容结构和电路板
公开(公告)号：US06343001B1
公开(公告)日：2002-01-29
申请号：US09655381
申请日：2000-09-05
申请人： Robert M. Japp , John M. Lauffer , Konstantinos I. Papathomas
发明人： Robert M. Japp , John M. Lauffer , Konstantinos I. Papathomas
IPC分类号： H01G4228
CPC分类号： H05K1/162 , H05K3/429 , H05K3/4611 , H05K3/4641 , H05K2201/0209 , H05K2201/0355 , H05K2201/09309 , H05K2203/0759
摘要： A method of forming a capacitive core structure and of forming a circuitized printed wiring board from the core structure and the resulting structures are provided. The capacitive core structure is formed by providing a central conducting plane of a sheet of conductive material and forming at least one clearance hole in the central conducting plane. First and second external conducting planes are laminated to opposite sides of the ground plane with a film of dielectric material between each of the first and second external planes and the central conducting plane. At least one clearance hole is formed in each of the first and second external planes. A circuitized wiring board structure can be formed by laminating a capacitive core structure between two circuitized structures. The invention also relates to the structures formed by these methods.
摘要翻译：提供了一种从芯结构形成电容性芯结构和形成电路化印刷线路板的方法及其结构。通过提供导电材料片的中心导电平面并在中心导电平面中形成至少一个间隙孔来形成电容芯结构。第一和第二外部导电平面在第一和第二外部平面之间的介电材料膜和中心导电平面之间层压到接地平面的相对侧。在第一和第二外部平面的每一个中形成至少一个间隙孔。可以通过在两个电路化结构之间层叠电容性芯结构来形成电路化布线板结构。本发明还涉及通过这些方法形成的结构。

5. 发明授权

US06496356B2 Multilayer capacitance structure and circuit board containing the same and method of forming the same 有权
标题翻译：多层电容结构和电路板含有相同的方法和其形成方法
公开(公告)号：US06496356B2
公开(公告)日：2002-12-17
申请号：US10026873
申请日：2001-12-21
申请人： Robert M. Japp , John M. Lauffer , Konstantinos I. Papathomas
发明人： Robert M. Japp , John M. Lauffer , Konstantinos I. Papathomas
IPC分类号： H01G4228
CPC分类号： H05K1/162 , H05K3/429 , H05K3/4611 , H05K3/4641 , H05K2201/0209 , H05K2201/0355 , H05K2201/09309 , H05K2203/0759
摘要： A method of forming a capacitive core structure and of forming a circuitized printed wiring board from the core structure and the resulting structures are provided. The capacitive core structure is formed by providing a central conducting plane of a sheet of conductive material and forming at least one clearance hole in the central conducting plane. First and second external conducting planes are laminated to opposite sides of the ground plane with a film of dielectric material between each of the first and second external planes and the central conducting plane. At least one clearance hole is formed in each of the first and second external planes. A circuitized wiring board structure can be formed by laminating a capacitive core structure between two circuitized structures. The invention also relates to the structures formed by these methods.
摘要翻译：提供了一种从芯结构形成电容性芯结构和形成电路化印刷线路板的方法及其结构。通过提供导电材料片的中心导电平面并在中心导电平面中形成至少一个间隙孔来形成电容芯结构。第一和第二外部导电平面在第一和第二外部平面之间的介电材料膜和中心导电平面之间层压到接地平面的相对侧。在第一和第二外部平面的每一个中形成至少一个间隙孔。可以通过在两个电路化结构之间层叠电容性芯结构来形成电路化布线板结构。本发明还涉及通过这些方法形成的结构。

6. 发明授权

US06459047B1 Laminate circuit structure and method of fabricating 失效
标题翻译：层压电路结构及其制造方法
公开(公告)号：US06459047B1
公开(公告)日：2002-10-01
申请号：US09947130
申请日：2001-09-05
申请人： Robert M. Japp , Voya R. Markovich , Konstantinos I. Papathomas
发明人： Robert M. Japp , Voya R. Markovich , Konstantinos I. Papathomas
IPC分类号： H05K109
CPC分类号： H05K3/382 , H05K1/056 , H05K3/383 , H05K3/384 , H05K3/388 , H05K3/389 , H05K3/445 , H05K2201/0209 , H05K2201/0355 , H05K2203/0307 , Y10S428/901 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165
摘要： A substrate and a method of making the substrate is provided. The substrate includes a layer of metal with at least one through hole therein, the layer of metal having an adhesion promoting layer thereon. A layer of a partially cured low-loss polymer or polymer precursor is positioned on the adhesion promoting layer and a plurality of conductive circuit lines are positioned on a portion of the partially cured dielectric layer. The substrate can be used as a building block in the fabrication of a multilayered printed circuit board.
摘要翻译：提供了基板和制造基板的方法。衬底包括金属层，其中具有至少一个通孔，金属层在其上具有粘附促进层。部分固化的低损失聚合物或聚合物前体层位于粘附促进层上，并且多个导电电路线位于部分固化的介电层的一部分上。衬底可以用作制造多层印刷电路板的构件。

7. 发明授权

US06734259B1 Resin composition with a polymerizing agent and method of manufacturing prepreg and other laminate structures therefrom 有权
标题翻译：具有聚合剂的树脂组合物及其制备预浸料及其它层合结构的方法
公开(公告)号：US06734259B1
公开(公告)日：2004-05-11
申请号：US10281038
申请日：2002-10-24
申请人： Robert M. Japp , Konstantinos I. Papathomas , Cory J. Ruud
发明人： Robert M. Japp , Konstantinos I. Papathomas , Cory J. Ruud
IPC分类号： C08F28308
CPC分类号： C08G65/485 , C08F283/08 , C08L71/126 , C08L2666/20
摘要： A prepreg resin comprising: (a) 98 to 40% by weight based on the total weight of components (a) and (b), of a curable polyphenylene ether resin; (b) 2 to 60% by weight based on the total weight of components (a) and (b), of at least one cyanurate selected from the group consisting of triallyl isocyanurate and triallyl cyanurate; (c) a polymerization initiator comprised of a peroxide functionalized polymer, said peroxide functionalized polymer being fragmented by heat to a plurality of free radical moieties, such as t-butoxide moieties, and a relatively inert moiety having a molecular weight greater than about 1,000. The invention also encompasses a cured resin either as a coating on a substrate, without fiberglass cloth embedded, or a cured prepreg with fiberglass cloth embedded and a method of forming the same.
摘要翻译：一种预浸料树脂，其包含：（a）基于组分（a）和（b）的总重量的98-40重量％的可固化聚苯醚树脂;（b）基于总重量的2-60重量％的组分（a）和（b））中的至少一种选自三烯丙基异氰脲酸酯和氰尿酸三烯丙酯的氰脲酸酯;（c）由过氧化物官能化聚合物组成的聚合引发剂，所述过氧化物官能化聚合物被加热分解成多个自由基部分，例如叔丁醇部分，以及分子量大于约1,000的相对惰性的部分。本发明还包括固化树脂，作为基材上的涂层，无玻璃纤维布嵌入或固化嵌入玻璃纤维布的预浸料及其形成方法。

8. 发明授权

US06820332B2 Laminate circuit structure and method of fabricating 失效
标题翻译：层压电路结构及其制造方法
公开(公告)号：US06820332B2
公开(公告)日：2004-11-23
申请号：US10196993
申请日：2002-07-16
申请人： Robert M. Japp , Voya R. Markovich , Konstantinos I. Papathomas
发明人： Robert M. Japp , Voya R. Markovich , Konstantinos I. Papathomas
IPC分类号： H01K310
CPC分类号： H05K3/382 , H05K1/056 , H05K3/383 , H05K3/384 , H05K3/388 , H05K3/389 , H05K3/445 , H05K2201/0209 , H05K2201/0355 , H05K2203/0307 , Y10S428/901 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165
摘要： A substrate and a method of making the substrate is provided. The substrate includes a layer of metal with at least one through hole therein, the layer of metal having an adhesion promoting layer thereon. A layer of a partially cured low-loss polymer or polymer precursor is positioned on the adhesion promoting layer and a plurality of conductive circuit lines are positioned on a portion of the partially cured dielectric layer. The substrate can be used as a building block in the fabrication of a multilayered printed circuit board.
摘要翻译：提供了基板和制造基板的方法。衬底包括金属层，其中具有至少一个通孔，金属层在其上具有粘附促进层。部分固化的低损失聚合物或聚合物前体层位于粘附促进层上，并且多个导电电路线位于部分固化的介电层的一部分上。衬底可以用作制造多层印刷电路板的构件。

9. 发明授权

US06399896B1 Circuit package having low modulus, conformal mounting pads 失效
标题翻译：具有低模数，适形安装垫的电路封装
公开(公告)号：US06399896B1
公开(公告)日：2002-06-04
申请号：US09525379
申请日：2000-03-15
申请人： Frank J. Downes, Jr. , Donald S. Farquhar , Robert M. Japp , William J. Rudik
发明人： Frank J. Downes, Jr. , Donald S. Farquhar , Robert M. Japp , William J. Rudik
IPC分类号： H05K116
CPC分类号： H05K3/326 , H05K1/0271 , H05K1/111 , H05K1/114 , H05K2201/0133 , H05K2201/0187 , H05K2201/10734 , H05K2203/0307
摘要： Reliability of circuit packaging while accommodating larger chips and increased temperature excursions is achieved by use of compliant pads only at the locations of connections between packaging levels, preferably between a laminated chip carrier and a printed circuit board. The invention allows the coefficient of thermal expansion of the chip carrier to be economically well-matched to the CTE of the chip and accommodation of significant differences in CTEs of package materials to be accommodated at a single packaging level. The compliant pads are preferably of low aspect ratio which are not significantly deflected by accelerations and can be formed on a surface or recessed into it. Connections can be made through surface connections and/or plated through holes. Connection enhancements such as solder wettable surfaces or dendritic textures are provided in a conductive metal or alloy layer over a compliant rubber or elastomer layer which may be conductive or non-conductive.
摘要翻译：通过仅在封装层之间的连接位置（优选在层压芯片载体和印刷电路板之间）使用柔性焊盘来实现电路封装的可靠性，同时容纳更大的芯片和增加的温度漂移。本发明允许芯片载体的热膨胀系数与芯片的CTE经济地良好匹配，并且可以容纳在单个封装层面上容纳的封装材料的CTE的显着差异。柔性衬垫优选地具有低纵横比，其不被加速度显着偏转，并且可以形成在表面上或凹入其中。可以通过表面连接和/或电镀通孔进行连接。在导电金属或合金层中的柔性橡胶或弹性体层上提供诸如焊料可润湿表面或树枝状织构的连接增强，其可以是导电的或不导电的。

10. 发明授权

US06373717B1 Electronic package with high density interconnect layer 有权
公开(公告)号：US06373717B1
公开(公告)日：2002-04-16
申请号：US09540172
申请日：2000-03-31
申请人： Francis J. Downes, Jr. , Donald S. Farquhar , Elizabeth Foster , Robert M. Japp , Gerald W. Jones , John S. Kresge , Robert D. Sebesta , David B. Stone , James R. Wilcox
发明人： Francis J. Downes, Jr. , Donald S. Farquhar , Elizabeth Foster , Robert M. Japp , Gerald W. Jones , John S. Kresge , Robert D. Sebesta , David B. Stone , James R. Wilcox
IPC分类号： H05K118
CPC分类号： H05K3/4641 , H01L21/4853 , H01L23/3735 , H01L23/49822 , H01L2224/16225 , H01L2924/00014 , H01L2924/01004 , H01L2924/01019 , H01L2924/01046 , H01L2924/01068 , H01L2924/01078 , H01L2924/01322 , H01L2924/12044 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025 , H05K1/114 , H05K3/429 , H05K3/4602 , H05K3/4608 , H05K3/4623 , H05K3/4626 , H05K3/4632 , H05K3/4688 , H05K2201/0141 , H05K2201/0191 , H05K2201/068 , H05K2201/09509 , H05K2201/09536 , H05K2201/09554 , H05K2201/0959 , H05K2201/096 , H05K2201/10378 , Y10T29/49155 , Y10T29/49165 , H01L2224/0401
摘要： An electronic package, and method of making the electronic package, is provided. The package includes a semiconductor chip and an multi-layered interconnect structure having a high density interconnect layer such as an allylated surface layer. The semiconductor chip includes a plurality of contact members on one of its surfaces that are connected to the multi-layered interconnect structure by a plurality of solder connections. The multi-layered interconnect structure is adapted for electrically interconnecting the semiconductor chip to a circuitized substrate (eg., circuit board) with another plurality of solder connections and includes a thermally conductive layer being comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between said first plurality of electrically conductive members and the semiconductor chip. The electronic package further includes a dielectric material having an effective modulus to assure sufficient compliancy of the multi-layered interconnect structure during operation. The allylated surface layer has the property of being able to withstand thermal stresses that arise during thermal cycling operation of the electronic package.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式