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1. 发明授权

US07930689B2 Method and system for accessing indirect memories 有权
标题翻译：访问间接存储器的方法和系统
公开(公告)号：US07930689B2
公开(公告)日：2011-04-19
申请号：US11186271
申请日：2005-07-21
申请人： Gilbert Cabillic , Jean-Philippe Lesot , Gerard Chauvel
发明人： Gilbert Cabillic , Jean-Philippe Lesot , Gerard Chauvel
IPC分类号： G06F9/44 , G06F12/06 , G06F9/26
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： Systems, methods, and storage media for accessing indirect memory in Java applications are provided. In some embodiments, a storage medium is provided that comprises Java application software that performs one or more operations on an indirect memory of a device. The software comprises instructions that create an instance of a Java class representing the indirect memory, and instructions that access a memory element of the indirect memory using an element unique identifier (“euid”) of the memory element. Other embodiments provide a method for accessing memory elements of a device that comprises creating an instance of a Java class representing the memory elements, and accessing a memory element of the memory elements using an element unique identifier (“euid”) of the memory element, wherein the memory elements are not mapped into the data memory space of the processor.
摘要翻译：提供了用于在Java应用程序中访问间接内存的系统，方法和存储介质。在一些实施例中，提供存储介质，其包括在设备的间接存储器上执行一个或多个操作的Java应用软件。软件包括创建表示间接存储器的Java类的实例的指令以及使用存储器元件的元素唯一标识符（“euid”）访问间接存储器的存储器元件的指令。其他实施例提供了一种用于访问设备的存储器元件的方法，包括创建表示存储器元件的Java类的实例，以及使用存储元件的元素唯一标识符（“euid”）访问存储器元件的存储器元件，其中所述存储器元件未映射到所述处理器的数据存储器空间。

2. 发明授权

US07533250B2 Automatic operand load, modify and store 有权
标题翻译：自动操作数加载，修改和存储
公开(公告)号：US07533250B2
公开(公告)日：2009-05-12
申请号：US11188311
申请日：2005-07-25
申请人： Gerard Chauvel , Jean-Philippe Lesot , Gilbert Cabillic
发明人： Gerard Chauvel , Jean-Philippe Lesot , Gilbert Cabillic
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： A processor comprising a decode logic coupled to a first storage unit and comprising a data structure. The processor also comprises a second storage unit coupled to the decode logic. The decode logic obtains a single instruction from the first storage unit and, if indicated by a first bit in the data structure, processes a group of instructions in lieu of the single instruction, where the single instruction requires an operand. If indicated by a second bit in the data structure, the decode logic obtains the operand from the first storage unit, modifies the operand, and stores the operand to the second storage unit for use by the group of instructions.
摘要翻译：一种处理器，包括耦合到第一存储单元并包括数据结构的解码逻辑。处理器还包括耦合到解码逻辑的第二存储单元。解码逻辑从第一存储单元获得单个指令，并且如果由数据结构中的第一位指示，则处理一组指令来代替单个指令，其中单个指令需要操作数。如果由数据结构中的第二位指示，则解码逻辑从第一存储单元获得操作数，修改操作数，并将操作数存储到第二存储单元以供指令组使用。

3. 发明申请

US20060026412A1 Removing local RAM size limitations when executing software code 有权
标题翻译：执行软件代码时，删除本地RAM大小限制
公开(公告)号：US20060026412A1
公开(公告)日：2006-02-02
申请号：US11186036
申请日：2005-07-21
申请人： Gilbert Cabillic , Gerard Chauvel , Jean-Philippe Lesot
发明人： Gilbert Cabillic , Gerard Chauvel , Jean-Philippe Lesot
IPC分类号： G06F9/44
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： An electronic device that comprises a processor including an individual instruction and a first group of instructions. The device further comprises a memory externally coupled to the processor, as well as a second group of instructions. When executed, the first group of instructions causes the processor to execute the second group of instructions in lieu of the individual instruction.
摘要翻译：一种电子设备，包括包括单独指令和第一组指令的处理器。该设备还包括外部耦合到处理器的存储器以及第二组指令。当执行时，第一组指令使得处理器执行第二组指令来代替单独的指令。

4. 发明申请

US20060026398A1 Unpack instruction 审中-公开
标题翻译：解开包装说明
公开(公告)号：US20060026398A1
公开(公告)日：2006-02-02
申请号：US11116918
申请日：2005-04-28
申请人： Gilbert Cabillic , Jean-Philippe Lesot , Gerard Chauvel , Dominique D'Inverno , Jaques Mequin
发明人： Gilbert Cabillic , Jean-Philippe Lesot , Gerard Chauvel , Dominique D'Inverno , Jaques Mequin
IPC分类号： G06F9/00
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012 , Y02D10/13
摘要： A processor executes an instruction that causes a source data field from a programmable position within a first source register to be copied to a destination register. The instruction is particularly useful for generating media-based bitstreams (e.g., audio, video). In some embodiments, a system (e.g., a communication device such as cellular telephone) includes a processor capable of executing the instruction as described above.
摘要翻译：处理器执行使来自第一源寄存器中的可编程位置的源数据字段被复制到目的地寄存器的指令。该指令对于生成基于媒体的比特流（例如，音频，视频）特别有用。在一些实施例中，系统（例如，诸如蜂窝电话的通信设备）包括能够执行如上所述的指令的处理器。

5. 发明申请

US20060026391A1 Automatic operand load and store 有权
标题翻译：自动操作数加载和存储
公开(公告)号：US20060026391A1
公开(公告)日：2006-02-02
申请号：US11188827
申请日：2005-07-25
申请人： Gerard Chauvel , Jean-Philippe Lesot , Gilbert Cabillic
发明人： Gerard Chauvel , Jean-Philippe Lesot , Gilbert Cabillic
IPC分类号： G06F9/30
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： A processor that comprises decode logic coupled to a first storage unit and comprising a data structure. The processor also comprises a second storage unit coupled to the decode logic. The decode logic obtains a single instruction from the first storage unit and, if indicated by a first bit in the data structure, processes a group of instructions in lieu of the single instruction, the single instruction requiring an operand. If indicated by a second bit in the data structure, the decode logic obtains the operand from the first storage unit and stores the operand to the second storage unit for use by the group of instructions.
摘要翻译：一种处理器，包括耦合到第一存储单元并包括数据结构的解码逻辑。处理器还包括耦合到解码逻辑的第二存储单元。解码逻辑从第一存储单元获得单个指令，并且如果由数据结构中的第一位指示，则代替单个指令处理一组指令，需要操作数的单个指令。如果由数据结构中的第二位指示，则解码逻辑从第一存储单元获得操作数，并将操作数存储到第二存储单元以供指令组使用。

6. 发明申请

US20060026370A1 Method and system for accessing indirect memories 有权
标题翻译：访问间接存储器的方法和系统
公开(公告)号：US20060026370A1
公开(公告)日：2006-02-02
申请号：US11186271
申请日：2005-07-21
申请人： Gilbert Cabillic , Jean-Philippe Lesot , Gerard Chauvel
发明人： Gilbert Cabillic , Jean-Philippe Lesot , Gerard Chauvel
IPC分类号： G06F12/00
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： Systems, methods, and storage media for accessing indirect memory in Java applications are provided. In some embodiments, a storage medium is provided that comprises Java application software that performs one or more operations on an indirect memory of a device. The software comprises instructions that create an instance of a Java class representing the indirect memory, and instructions that access a memory element of the indirect memory using an element unique identifier (“euid”) of the memory element. Other embodiments provide a method for accessing memory elements of a device that comprises creating an instance of a Java class representing the memory elements, and accessing a memory element of the memory elements using an element unique identifier (“euid”) of the memory element, wherein the memory elements are not mapped into the data memory space of the processor.
摘要翻译：提供了用于在Java应用程序中访问间接内存的系统，方法和存储介质。在一些实施例中，提供存储介质，其包括在设备的间接存储器上执行一个或多个操作的Java应用软件。软件包括创建表示间接存储器的Java类的实例的指令以及使用存储器元件的元素唯一标识符（“euid”）访问间接存储器的存储器元件的指令。其他实施例提供了一种用于访问设备的存储器元件的方法，包括创建表示存储器元件的Java类的实例，以及使用存储元件的元素唯一标识符（“euid”）访问存储器元件的存储器元件，其中所述存储器元件未映射到所述处理器的数据存储器空间。

7. 发明授权

US08190861B2 Micro-sequence based security model 有权
标题翻译：基于微序列的安全模型
公开(公告)号：US08190861B2
公开(公告)日：2012-05-29
申请号：US11677367
申请日：2007-02-21
申请人： Gerard Chauvel , Gilbert Cabillic , Jean-Philippe Lesot , Dominique D'Inverno , Eric Badi , Serge Lasserre
发明人： Gerard Chauvel , Gilbert Cabillic , Jean-Philippe Lesot , Dominique D'Inverno , Eric Badi , Serge Lasserre
IPC分类号： G06F9/00
CPC分类号： G06F9/4812
摘要： A method and system for implementing a micro-sequence based security model in a processor. More particularly, micro-sequences and JSM hardware resources are employed to construct a security model invisible to applications, and when memory constraints are in place, extend a complex security model in JSM code by implementing a micro-sequence security trigger. The method includes micro-sequence based security policy that determines whether an instruction accesses a privileged resource associated with a processor and when not already in privilege mode and not executing a micro-sequence, the micro-sequence based security policy is applied to the instruction to control access to the privileged resource according to the security policy.
摘要翻译：一种用于在处理器中实现基于微序列的安全模型的方法和系统。更具体地，使用微序列和JSM硬件资源来构建对应用不可见的安全模型，并且当存储器约束到位时，通过实现微序列安全触发来扩展JSM代码中的复杂安全模型。该方法包括基于微序列的安全策略，其确定指令是否访问与处理器相关联的特权资源，以及当尚未处于特权模式且不执行微序列时，将基于微序列的安全策略应用于根据安全策略控制对特权资源的访问。

8. 发明授权

US07757223B2 Method and system to construct a data-flow analyzer for a bytecode verifier 有权
标题翻译：构建字节码验证器的数据流分析器的方法和系统
公开(公告)号：US07757223B2
公开(公告)日：2010-07-13
申请号：US11188502
申请日：2005-07-25
申请人： Gilbert Cabillic , Jean-Philippe Lesot , Mikael Peltier , Gerard Chauvel
发明人： Gilbert Cabillic , Jean-Philippe Lesot , Mikael Peltier , Gerard Chauvel
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： The problems noted above are solved in large part by a method and system to construct a data-flow analyzer for a bytecode verifier using existing hardware resources and software. Specifically, micro-sequences and JSM hardware resources may be employed fetch a first instruction, apply the first instruction to a decode logic of a processor, trigger execution of a first series of instructions by the decode logic that pops a first value off of a data structure, such as a stack or local variable map, the first value indicative of a parameter type pushed on the stack or local variable map by a previously decoded instruction; and verify that the first value is a parameter type expected by the first instruction.
摘要翻译：上述问题在很大程度上是由现有硬件资源和软件构成用于字节码验证器的数据流分析器的方法和系统。具体来说，可以采用微序列和JSM硬件资源来取得第一指令，将第一指令应用于处理器的解码逻辑，由解码逻辑触发第一系列指令的执行，该解码逻辑从数据中弹出第一值结构，例如堆栈或局部变量映射，指示通过先前解码的指令来推送在堆栈上的参数类型的第一值或局部变量映射; 并验证第一个值是第一个指令预期的参数类型。

9. 发明授权

US07624382B2 Method and system of control flow graph construction 有权
标题翻译：控制流程图构建方法与系统
公开(公告)号：US07624382B2
公开(公告)日：2009-11-24
申请号：US11189367
申请日：2005-07-26
申请人： Gerard Chauvel , Jean-Philippe Lesot , Gilbert Cabillic , Mikael Peltier
发明人： Gerard Chauvel , Jean-Philippe Lesot , Gilbert Cabillic , Mikael Peltier
IPC分类号： G06F9/44
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： A method and system to build a control flow graph by execution of micro-sequences using hardware. Some illustrative embodiments are a processor comprising fetch logic that retrieves an instruction from a memory, the instruction being part of a program, and decode logic coupled to the fetch logic which decodes the instruction, wherein the instruction decoded by the decode logic triggers execution of a micro-sequence to enter the instruction in a control flow graph.
摘要翻译：一种通过使用硬件执行微序列构建控制流程图的方法和系统。一些说明性实施例是包括从存储器检索指令的获取逻辑的处理器，作为程序的一部分的指令以及耦合到解码指令的取指逻辑的解码逻辑，其中由解码逻辑解码的指令触发执行微序列在控制流程图中输入指令。

10. 发明授权

US07493476B2 Method and system for obtaining an immediate operand of a bytecode for use by a micro-sequence 有权
标题翻译：用于获得由微序列使用的字节码的立即操作数的方法和系统
公开(公告)号：US07493476B2
公开(公告)日：2009-02-17
申请号：US11188827
申请日：2005-07-25
申请人： Gerard Chauvel , Jean-Philippe Lesot , Gilbert Cabillic
发明人： Gerard Chauvel , Jean-Philippe Lesot , Gilbert Cabillic
IPC分类号： G06F9/22
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： A processor is provided that includes decode logic coupled to an instruction cache and a micro-sequence vector table including entries for each bytecode in an instruction set of the processor. The processor also includes a register coupled to the decode logic, wherein the register is dedicated for storage of an immediate operand of a bytecode. The decode logic is configured to obtain a single bytecode from the instruction cache, wherein the single bytecode requires an immediate operand stored in the instruction cache, use the single bytecode to locate an entry corresponding to the bytecode in the micro-sequence vector table, and, when indicated by information in the entry, obtain the immediate operand from the instruction cache and store the immediate operand in the register for use by a micro-sequence that is executed in lieu of the single bytecode.
摘要翻译：提供了处理器，其包括耦合到指令高速缓存的解码逻辑和包括处理器的指令集中的每个字节码的条目的微序列向量表。处理器还包括耦合到解码逻辑的寄存器，其中寄存器专用于存储字节码的立即操作数。解码逻辑被配置为从指令高速缓存获得单个字节码，其中单个字节码需要存储在指令高速缓存中的立即操作数，使用单个字节码来定位与微序列向量表中的字节码相对应的条目，以及当由条目中的信息指示时，从指令高速缓存中获取立即操作数，并将该立即操作数存储在寄存器中以供代替单字节代码执行的微序列使用。

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