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1. 发明授权

US07930689B2 Method and system for accessing indirect memories 有权
标题翻译：访问间接存储器的方法和系统
公开(公告)号：US07930689B2
公开(公告)日：2011-04-19
申请号：US11186271
申请日：2005-07-21
申请人： Gilbert Cabillic , Jean-Philippe Lesot , Gerard Chauvel
发明人： Gilbert Cabillic , Jean-Philippe Lesot , Gerard Chauvel
IPC分类号： G06F9/44 , G06F12/06 , G06F9/26
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： Systems, methods, and storage media for accessing indirect memory in Java applications are provided. In some embodiments, a storage medium is provided that comprises Java application software that performs one or more operations on an indirect memory of a device. The software comprises instructions that create an instance of a Java class representing the indirect memory, and instructions that access a memory element of the indirect memory using an element unique identifier (“euid”) of the memory element. Other embodiments provide a method for accessing memory elements of a device that comprises creating an instance of a Java class representing the memory elements, and accessing a memory element of the memory elements using an element unique identifier (“euid”) of the memory element, wherein the memory elements are not mapped into the data memory space of the processor.
摘要翻译：提供了用于在Java应用程序中访问间接内存的系统，方法和存储介质。在一些实施例中，提供存储介质，其包括在设备的间接存储器上执行一个或多个操作的Java应用软件。软件包括创建表示间接存储器的Java类的实例的指令以及使用存储器元件的元素唯一标识符（“euid”）访问间接存储器的存储器元件的指令。其他实施例提供了一种用于访问设备的存储器元件的方法，包括创建表示存储器元件的Java类的实例，以及使用存储元件的元素唯一标识符（“euid”）访问存储器元件的存储器元件，其中所述存储器元件未映射到所述处理器的数据存储器空间。

2. 发明授权

US07533250B2 Automatic operand load, modify and store 有权
标题翻译：自动操作数加载，修改和存储
公开(公告)号：US07533250B2
公开(公告)日：2009-05-12
申请号：US11188311
申请日：2005-07-25
申请人： Gerard Chauvel , Jean-Philippe Lesot , Gilbert Cabillic
发明人： Gerard Chauvel , Jean-Philippe Lesot , Gilbert Cabillic
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： A processor comprising a decode logic coupled to a first storage unit and comprising a data structure. The processor also comprises a second storage unit coupled to the decode logic. The decode logic obtains a single instruction from the first storage unit and, if indicated by a first bit in the data structure, processes a group of instructions in lieu of the single instruction, where the single instruction requires an operand. If indicated by a second bit in the data structure, the decode logic obtains the operand from the first storage unit, modifies the operand, and stores the operand to the second storage unit for use by the group of instructions.
摘要翻译：一种处理器，包括耦合到第一存储单元并包括数据结构的解码逻辑。处理器还包括耦合到解码逻辑的第二存储单元。解码逻辑从第一存储单元获得单个指令，并且如果由数据结构中的第一位指示，则处理一组指令来代替单个指令，其中单个指令需要操作数。如果由数据结构中的第二位指示，则解码逻辑从第一存储单元获得操作数，修改操作数，并将操作数存储到第二存储单元以供指令组使用。

3. 发明申请

US20060026412A1 Removing local RAM size limitations when executing software code 有权
标题翻译：执行软件代码时，删除本地RAM大小限制
公开(公告)号：US20060026412A1
公开(公告)日：2006-02-02
申请号：US11186036
申请日：2005-07-21
申请人： Gilbert Cabillic , Gerard Chauvel , Jean-Philippe Lesot
发明人： Gilbert Cabillic , Gerard Chauvel , Jean-Philippe Lesot
IPC分类号： G06F9/44
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： An electronic device that comprises a processor including an individual instruction and a first group of instructions. The device further comprises a memory externally coupled to the processor, as well as a second group of instructions. When executed, the first group of instructions causes the processor to execute the second group of instructions in lieu of the individual instruction.
摘要翻译：一种电子设备，包括包括单独指令和第一组指令的处理器。该设备还包括外部耦合到处理器的存储器以及第二组指令。当执行时，第一组指令使得处理器执行第二组指令来代替单独的指令。

4. 发明申请

US20060026398A1 Unpack instruction 审中-公开
标题翻译：解开包装说明
公开(公告)号：US20060026398A1
公开(公告)日：2006-02-02
申请号：US11116918
申请日：2005-04-28
申请人： Gilbert Cabillic , Jean-Philippe Lesot , Gerard Chauvel , Dominique D'Inverno , Jaques Mequin
发明人： Gilbert Cabillic , Jean-Philippe Lesot , Gerard Chauvel , Dominique D'Inverno , Jaques Mequin
IPC分类号： G06F9/00
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012 , Y02D10/13
摘要： A processor executes an instruction that causes a source data field from a programmable position within a first source register to be copied to a destination register. The instruction is particularly useful for generating media-based bitstreams (e.g., audio, video). In some embodiments, a system (e.g., a communication device such as cellular telephone) includes a processor capable of executing the instruction as described above.
摘要翻译：处理器执行使来自第一源寄存器中的可编程位置的源数据字段被复制到目的地寄存器的指令。该指令对于生成基于媒体的比特流（例如，音频，视频）特别有用。在一些实施例中，系统（例如，诸如蜂窝电话的通信设备）包括能够执行如上所述的指令的处理器。

5. 发明申请

US20060026391A1 Automatic operand load and store 有权
标题翻译：自动操作数加载和存储
公开(公告)号：US20060026391A1
公开(公告)日：2006-02-02
申请号：US11188827
申请日：2005-07-25
申请人： Gerard Chauvel , Jean-Philippe Lesot , Gilbert Cabillic
发明人： Gerard Chauvel , Jean-Philippe Lesot , Gilbert Cabillic
IPC分类号： G06F9/30
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： A processor that comprises decode logic coupled to a first storage unit and comprising a data structure. The processor also comprises a second storage unit coupled to the decode logic. The decode logic obtains a single instruction from the first storage unit and, if indicated by a first bit in the data structure, processes a group of instructions in lieu of the single instruction, the single instruction requiring an operand. If indicated by a second bit in the data structure, the decode logic obtains the operand from the first storage unit and stores the operand to the second storage unit for use by the group of instructions.
摘要翻译：一种处理器，包括耦合到第一存储单元并包括数据结构的解码逻辑。处理器还包括耦合到解码逻辑的第二存储单元。解码逻辑从第一存储单元获得单个指令，并且如果由数据结构中的第一位指示，则代替单个指令处理一组指令，需要操作数的单个指令。如果由数据结构中的第二位指示，则解码逻辑从第一存储单元获得操作数，并将操作数存储到第二存储单元以供指令组使用。

6. 发明申请

US20060026370A1 Method and system for accessing indirect memories 有权
标题翻译：访问间接存储器的方法和系统
公开(公告)号：US20060026370A1
公开(公告)日：2006-02-02
申请号：US11186271
申请日：2005-07-21
申请人： Gilbert Cabillic , Jean-Philippe Lesot , Gerard Chauvel
发明人： Gilbert Cabillic , Jean-Philippe Lesot , Gerard Chauvel
IPC分类号： G06F12/00
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： Systems, methods, and storage media for accessing indirect memory in Java applications are provided. In some embodiments, a storage medium is provided that comprises Java application software that performs one or more operations on an indirect memory of a device. The software comprises instructions that create an instance of a Java class representing the indirect memory, and instructions that access a memory element of the indirect memory using an element unique identifier (“euid”) of the memory element. Other embodiments provide a method for accessing memory elements of a device that comprises creating an instance of a Java class representing the memory elements, and accessing a memory element of the memory elements using an element unique identifier (“euid”) of the memory element, wherein the memory elements are not mapped into the data memory space of the processor.
摘要翻译：提供了用于在Java应用程序中访问间接内存的系统，方法和存储介质。在一些实施例中，提供存储介质，其包括在设备的间接存储器上执行一个或多个操作的Java应用软件。软件包括创建表示间接存储器的Java类的实例的指令以及使用存储器元件的元素唯一标识符（“euid”）访问间接存储器的存储器元件的指令。其他实施例提供了一种用于访问设备的存储器元件的方法，包括创建表示存储器元件的Java类的实例，以及使用存储元件的元素唯一标识符（“euid”）访问存储器元件的存储器元件，其中所述存储器元件未映射到所述处理器的数据存储器空间。

7. 发明授权

US08516502B2 Performing java interrupt with two program counters 有权
标题翻译：用两个程序计数器执行java中断
公开(公告)号：US08516502B2
公开(公告)日：2013-08-20
申请号：US11741237
申请日：2007-04-27
申请人： Gerard Chauvel , Gilbert Cabillic , Jean-Philippe Lesot
发明人： Gerard Chauvel , Gilbert Cabillic , Jean-Philippe Lesot
IPC分类号： G06F3/00 , G06F9/44 , G06F9/46 , G06F13/00 , G06F9/455 , G06F9/45
CPC分类号： G06F9/4812
摘要： A method and system for performing a Java interrupt. At least some of the illustrative embodiments are methods comprising executing a thread having a context on a stack based on a first program counter, detecting an interrupt while executing the thread (wherein execution of the thread is temporarily suspended), and executing a method portion to handle the interrupt (wherein the method portion is executed on the stack based on the first program counter, and wherein the context during execution of the method portion is the same as during execution of the thread).
摘要翻译：一种用于执行Java中断的方法和系统。至少一些说明性实施例是包括基于第一程序计数器执行在堆栈上具有上下文的线程的方法，在执行线程的同时检测中断（其中线程的执行被暂停），并且执行方法部分处理中断（其中基于第一程序计数器在堆栈上执行方法部分，并且其中方法部分的执行期间的上下文与执行线程期间相同）。

8. 发明授权

US08046748B2 Method and system to emulate an M-bit instruction set 有权
标题翻译：一种用于模拟M位指令集的方法和系统
公开(公告)号：US08046748B2
公开(公告)日：2011-10-25
申请号：US11188310
申请日：2005-07-25
申请人： Gilbert Cabillic , Jean-Philippe Lesot , Gerard Chauvel
发明人： Gilbert Cabillic , Jean-Philippe Lesot , Gerard Chauvel
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： A method and system to emulate an M-bit instruction set. At least some of the illustrative embodiments are a method comprising fetching at least a portion of an instruction (the instruction from a first instruction set that is not directly executable by a processor), indexing into a table to an index location (the index location based on the at least a portion of the instruction), executing a first series of instructions directly executable by the processor (the first series of instructions pointed to by the table at the index location), and thereby emulating execution of the instruction from the first instruction set.
摘要翻译：一种模拟M位指令集的方法和系统。说明性实施例中的至少一些是一种方法，包括获取指令的至少一部分（来自第一指令集的不是由处理器直接执行的指令），索引到索引位置（基于索引位置）在指令的至少一部分上），执行由处理器直接执行的第一系列指令（由索引位置处的表指向的第一系列指令），从而模拟来自第一指令的指令的执行组。

9. 发明授权

US07565385B2 Embedded garbage collection 有权
标题翻译：嵌入式垃圾收集
公开(公告)号：US07565385B2
公开(公告)日：2009-07-21
申请号：US10831387
申请日：2004-04-22
申请人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Jean-Paul Routeau , Salam Majoul , Frédéric Parain
发明人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Jean-Paul Routeau , Salam Majoul , Frédéric Parain
IPC分类号： G06F17/00
CPC分类号： G06F12/0269 , Y02D10/13 , Y10S707/99957
摘要： An electronic system comprises a processor, memory coupled to the processor, and an application programming interface that causes an embedded garbage collection object to be active. The memory stores one or more objects that selectively have references from root objects. The embedded garbage collection object preferably uses control data to cause objects to be removed from said memory, the removed objects comprise those objects that were created while an embedded garbage collection object was active and that do not have references from root objects.
摘要翻译：电子系统包括处理器，耦合到处理器的存储器以及使嵌入式垃圾回收对象活动的应用编程接口。存储器存储一个或多个选择性地具有来自根对象的引用的对象。嵌入式垃圾回收对象优选地使用控制数据来使对象从所述存储器中移除，所移除的对象包括当嵌入式垃圾回收对象是活动的并且没有来自根对象的引用时创建的对象。

10. 发明授权

US07434021B2 Memory allocation in a multi-processor system 有权
标题翻译：多处理器系统中的内存分配
公开(公告)号：US07434021B2
公开(公告)日：2008-10-07
申请号：US10831388
申请日：2004-04-22
申请人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Jean-Paul Routeau , Salam Majoul , Frédéric Parain
发明人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Jean-Paul Routeau , Salam Majoul , Frédéric Parain
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F9/5016 , Y02D10/22
摘要： A process and associated system comprise pre-allocating a portion of memory in a first processor based upon a control input and determining in a second processor if the portion of the pre-allocated memory can satisfy a memory allocation request. Further, if a portion of pre-allocated memory can satisfy a memory allocation request, the technique includes assigning the pre-allocated portion of memory to the allocation request. However, if a portion of pre-allocated memory cannot satisfy a memory allocation request, the technique includes allocating a portion of memory in the first processor to the allocation request.
摘要翻译：过程和相关系统包括基于控制输入在第一处理器中预分配存储器的一部分，并且在第二处理器中确定预分配存储器的部分是否可以满足存储器分配请求。此外，如果预先分配的存储器的一部分可以满足存储器分配请求，则该技术包括将存储器的预分配部分分配给分配请求。然而，如果预分配存储器的一部分不能满足存储器分配请求，则该技术包括将第一处理器中的存储器的一部分分配给分配请求。

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