专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090072858A1 HETEROGENEOUS CONFIGURABLE INTEGRATED CIRCUIT 有权
标题翻译：异构可配置集成电路
公开(公告)号：US20090072858A1
公开(公告)日：2009-03-19
申请号：US11855666
申请日：2007-09-14
申请人： Godfrey P. D'Souza , Douglas Laird , Malcolm J. Wing , Colin N. Murphy , Dana L. How , Robert Yu , Jay B. Patel , Ivo Dobbelaere , Jason Golbus , Suresh Subramaniam , Mukunda Krishnappa , Pohrong R. Chu , Dave Trossen , Kevin James
发明人： Godfrey P. D'Souza , Douglas Laird , Malcolm J. Wing , Colin N. Murphy , Dana L. How , Robert Yu , Jay B. Patel , Ivo Dobbelaere , Jason Golbus , Suresh Subramaniam , Mukunda Krishnappa , Pohrong R. Chu , Dave Trossen , Kevin James
IPC分类号： H03K19/173
CPC分类号： H03K19/177
摘要： A system including a plurality of programmable logic blocks, a plurality of special-purpose blocks, and a configurable high-speed mesh interconnect fabric operatively connecting the plurality of programmable logic blocks and the plurality of special-purpose blocks, where the configurable high-speed mesh interconnect fabric is configured to implement a plurality of interconnect pipeline buses spanning across the system.
摘要翻译：一种包括多个可编程逻辑块，多个特殊用途块和可操作地连接多个可编程逻辑块和多个专用块的可配置高速网状互连结构的系统，其中可配置的高速网状互连结构被配置为实现横跨系统的多个互连管线总线。

2. 发明授权

US07557605B2 Heterogeneous configurable integrated circuit 有权
标题翻译：异构可配置集成电路
公开(公告)号：US07557605B2
公开(公告)日：2009-07-07
申请号：US11855666
申请日：2007-09-14
申请人： Godfrey P. D'Souza , Douglas Laird , Malcolm J. Wing , Colin N. Murphy , Dana L. How , Robert Yu , Jay B. Patel , Ivo Dobbelaere , Jason Golbus , Suresh Subramaniam , Mukunda Krishnappa , Pohrong R. Chu , Dave Trossen , Kevin James
发明人： Godfrey P. D'Souza , Douglas Laird , Malcolm J. Wing , Colin N. Murphy , Dana L. How , Robert Yu , Jay B. Patel , Ivo Dobbelaere , Jason Golbus , Suresh Subramaniam , Mukunda Krishnappa , Pohrong R. Chu , Dave Trossen , Kevin James
IPC分类号： H03K19/173
CPC分类号： H03K19/177
摘要： A system including a plurality of programmable logic blocks, a plurality of special-purpose blocks, and a configurable high-speed mesh interconnect fabric operatively connecting the plurality of programmable logic blocks and the plurality of special-purpose blocks, where the configurable high-speed mesh interconnect fabric is configured to implement a plurality of interconnect pipeline buses spanning across the system.
摘要翻译：一种包括多个可编程逻辑块，多个特殊用途块和可操作地连接多个可编程逻辑块和多个专用块的可配置高速网状互连结构的系统，其中可配置的高速网状互连结构被配置为实现横跨系统的多个互连管线总线。

3. 发明申请

US20090077308A1 RECONFIGURABLE CONTENT-ADDRESSABLE MEMORY 有权
标题翻译：可重新配置的内容可寻址存储器
公开(公告)号：US20090077308A1
公开(公告)日：2009-03-19
申请号：US11855721
申请日：2007-09-14
申请人： Robert Yu , Dave Trossen , Jack Liu , Mukunda Krishnappa , Kevin James
发明人： Robert Yu , Dave Trossen , Jack Liu , Mukunda Krishnappa , Kevin James
IPC分类号： G06F12/00
CPC分类号： G11C15/00
摘要： A system for determining memory addresses including a first content-addressable memory (CAM) configured to generate a first matchvector based on a first key; a first inverse-mask-reverse (IMR) module operatively connected to the first CAM, where the first IMR module is configured to generate a first auxiliary matchvector based on the first matchvector; and a first priority encoder (PE) operatively connected to the first IMR module, where the first PE is configured to output a first encoded memory address based on the first auxiliary matchvector, where the first CAM, the first IMR module, and the first PE are associated with a first reconfigurable content-addressable memory (RCAM).
摘要翻译：一种用于确定存储器地址的系统，包括被配置为基于第一密钥生成第一匹配向量的第一可内容寻址存储器（CAM）可操作地连接到第一CAM的第一逆掩模反向（IMR）模块，其中第一IMR模块被配置为基于第一匹配向量生成第一辅助匹配向量; 以及可操作地连接到第一IMR模块的第一优先级编码器（PE），其中第一PE被配置为基于第一辅助匹配向量来输出第一编码存储器地址，其中第一CAM，第一IMR模块和第一PE 与第一可重新配置的内容可寻址存储器（RCAM）相关联。

4. 发明授权

US07889530B2 Reconfigurable content-addressable memory 有权
标题翻译：可重配置的内容可寻址内存
公开(公告)号：US07889530B2
公开(公告)日：2011-02-15
申请号：US11855721
申请日：2007-09-14
申请人： Robert Yu , Dave Trossen , Jack Liu , Mukunda Krishnappa , Kevin James
发明人： Robert Yu , Dave Trossen , Jack Liu , Mukunda Krishnappa , Kevin James
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： A system for determining memory addresses including a first content-addressable memory (CAM) configured to generate a first matchvector based on a first key; a first inverse-mask-reverse (IMR) module operatively connected to the first CAM, where the first IMR module is configured to generate a first auxiliary matchvector based on the first matchvector; and a first priority encoder (PE) operatively connected to the first IMR module, where the first PE is configured to output a first encoded memory address based on the first auxiliary matchvector, where the first CAM, the first IMR module, and the first PE are associated with a first reconfigurable content-addressable memory (RCAM).
摘要翻译：一种用于确定存储器地址的系统，包括被配置为基于第一密钥生成第一匹配向量的第一可内容寻址存储器（CAM）可操作地连接到第一CAM的第一逆掩模反向（IMR）模块，其中第一IMR模块被配置为基于第一匹配向量生成第一辅助匹配向量; 以及可操作地连接到第一IMR模块的第一优先级编码器（PE），其中第一PE被配置为基于第一辅助匹配向量来输出第一编码存储器地址，其中第一CAM，第一IMR模块和第一PE 与第一可重新配置的内容可寻址存储器（RCAM）相关联。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式