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1. 发明申请

US20090072858A1 HETEROGENEOUS CONFIGURABLE INTEGRATED CIRCUIT 有权
标题翻译：异构可配置集成电路
公开(公告)号：US20090072858A1
公开(公告)日：2009-03-19
申请号：US11855666
申请日：2007-09-14
申请人： Godfrey P. D'Souza , Douglas Laird , Malcolm J. Wing , Colin N. Murphy , Dana L. How , Robert Yu , Jay B. Patel , Ivo Dobbelaere , Jason Golbus , Suresh Subramaniam , Mukunda Krishnappa , Pohrong R. Chu , Dave Trossen , Kevin James
发明人： Godfrey P. D'Souza , Douglas Laird , Malcolm J. Wing , Colin N. Murphy , Dana L. How , Robert Yu , Jay B. Patel , Ivo Dobbelaere , Jason Golbus , Suresh Subramaniam , Mukunda Krishnappa , Pohrong R. Chu , Dave Trossen , Kevin James
IPC分类号： H03K19/173
CPC分类号： H03K19/177
摘要： A system including a plurality of programmable logic blocks, a plurality of special-purpose blocks, and a configurable high-speed mesh interconnect fabric operatively connecting the plurality of programmable logic blocks and the plurality of special-purpose blocks, where the configurable high-speed mesh interconnect fabric is configured to implement a plurality of interconnect pipeline buses spanning across the system.
摘要翻译：一种包括多个可编程逻辑块，多个特殊用途块和可操作地连接多个可编程逻辑块和多个专用块的可配置高速网状互连结构的系统，其中可配置的高速网状互连结构被配置为实现横跨系统的多个互连管线总线。

2. 发明授权

US07557605B2 Heterogeneous configurable integrated circuit 有权
标题翻译：异构可配置集成电路
公开(公告)号：US07557605B2
公开(公告)日：2009-07-07
申请号：US11855666
申请日：2007-09-14
申请人： Godfrey P. D'Souza , Douglas Laird , Malcolm J. Wing , Colin N. Murphy , Dana L. How , Robert Yu , Jay B. Patel , Ivo Dobbelaere , Jason Golbus , Suresh Subramaniam , Mukunda Krishnappa , Pohrong R. Chu , Dave Trossen , Kevin James
发明人： Godfrey P. D'Souza , Douglas Laird , Malcolm J. Wing , Colin N. Murphy , Dana L. How , Robert Yu , Jay B. Patel , Ivo Dobbelaere , Jason Golbus , Suresh Subramaniam , Mukunda Krishnappa , Pohrong R. Chu , Dave Trossen , Kevin James
IPC分类号： H03K19/173
CPC分类号： H03K19/177
摘要： A system including a plurality of programmable logic blocks, a plurality of special-purpose blocks, and a configurable high-speed mesh interconnect fabric operatively connecting the plurality of programmable logic blocks and the plurality of special-purpose blocks, where the configurable high-speed mesh interconnect fabric is configured to implement a plurality of interconnect pipeline buses spanning across the system.
摘要翻译：一种包括多个可编程逻辑块，多个特殊用途块和可操作地连接多个可编程逻辑块和多个专用块的可配置高速网状互连结构的系统，其中可配置的高速网状互连结构被配置为实现横跨系统的多个互连管线总线。

3. 发明授权

US07902862B2 High-bandwidth interconnect network for an integrated circuit 有权
标题翻译：用于集成电路的高带宽互连网络
公开(公告)号：US07902862B2
公开(公告)日：2011-03-08
申请号：US11901182
申请日：2007-09-14
申请人： Dana How , Godfrey P. D'Souza , Malcolm J. Wing , Colin N. Murphy , Arun Jangity
发明人： Dana How , Godfrey P. D'Souza , Malcolm J. Wing , Colin N. Murphy , Arun Jangity
IPC分类号： H03K19/173
CPC分类号： G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits.
摘要翻译：总线结构在逻辑电路和集成电路的专用电路之间提供流水线传输数据，总线结构包括流水线导体网络，并且连接器选择性地将流水线导体连接在专用电路，其它流水线连接器和逻辑电路。

4. 发明申请

US20100306429A1 System and Method of Signal Processing Engines With Programmable Logic Fabric 有权
标题翻译：信号处理引擎与可编程逻辑结构的系统与方法
公开(公告)号：US20100306429A1
公开(公告)日：2010-12-02
申请号：US12855466
申请日：2010-08-12
申请人： Dana How , Godfrey P. D'Souza , Malcolm J. Wing , Colin N. Murphy , Arun Jangity
发明人： Dana How , Godfrey P. D'Souza , Malcolm J. Wing , Colin N. Murphy , Arun Jangity
IPC分类号： G06F13/40 , G06F13/42
CPC分类号： G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits.
摘要翻译：总线结构在逻辑电路和集成电路的专用电路之间提供流水线传输数据，总线结构包括流水线导体网络，并且连接器选择性地将流水线导体连接在专用电路，其它流水线连接器和逻辑电路。

5. 发明申请

US20090073967A1 High-bandwidth interconnect network for an integrated circuit 有权
标题翻译：用于集成电路的高带宽互连网络
公开(公告)号：US20090073967A1
公开(公告)日：2009-03-19
申请号：US11901182
申请日：2007-09-14
申请人： Dana How , Godfrey P. D'Souza , Malcolm J. Wing , Colin N. Murphy , Arun Jangity
发明人： Dana How , Godfrey P. D'Souza , Malcolm J. Wing , Colin N. Murphy , Arun Jangity
IPC分类号： H04L12/50
CPC分类号： G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits.
摘要翻译：总线结构在逻辑电路和集成电路的专用电路之间提供流水线传输数据，总线结构包括流水线导体网络，并且连接器选择性地将流水线导体连接在专用电路，其它流水线连接器和逻辑电路。

6. 发明授权

US07944236B2 High-bandwidth interconnect network for an integrated circuit 有权
公开(公告)号：US07944236B2
公开(公告)日：2011-05-17
申请号：US12855466
申请日：2010-08-12
申请人： Dana How , Godfrey P. D'Souza , Malcolm J. Wing , Colin N. Murphy , Arun Jangity
发明人： Dana How , Godfrey P. D'Souza , Malcolm J. Wing , Colin N. Murphy , Arun Jangity
IPC分类号： H03K19/173
CPC分类号： G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits.

7. 发明授权

US08405418B1 High-bandwidth interconnect network for an integrated circuit 有权
公开(公告)号：US08405418B1
公开(公告)日：2013-03-26
申请号：US13107899
申请日：2011-05-14
申请人： Dana How , Godfrey P. D'Souza , Malcolm J. Wing , Colin N. Murphy , Arun Jangity
发明人： Dana How , Godfrey P. D'Souza , Malcolm J. Wing , Colin N. Murphy , Arun Jangity
IPC分类号： H03K19/173
CPC分类号： G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits.

8. 发明授权

US06011908A Gated store buffer for an advanced microprocessor 失效
标题翻译：高级微处理器的门控存储缓冲区
公开(公告)号：US06011908A
公开(公告)日：2000-01-04
申请号：US772686
申请日：1996-12-23
申请人： Malcolm J. Wing , Godfrey P. D'Souza
发明人： Malcolm J. Wing , Godfrey P. D'Souza
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F9/455 , G06F11/00
CPC分类号： G06F9/3808 , G06F9/3834 , G06F9/3861
摘要： A gated store buffer including circuitry for temporarily holding apart from other memory stores all memory stores sequentially generated during a translation interval by a host processor translating a sequence of target instructions into host instructions, circuitry for transferring memory stores sequentially generated during a translation interval to memory if the translation executes without generating an exception, circuitry for indicating which memory stores to identical memory addresses are most recent in response to a memory access at the memory address, and circuitry for eliminating memory stores sequentially generated during a translation interval if the translation executes without generating an exception.
摘要翻译：门控存储缓冲器，包括用于临时保持与其他存储器分开的电路，用于存储在翻译间隔期间由主处理器顺序产生的所有存储器存储器，所述存储器存储器将目标指令序列转换为主机指令，用于传送在翻译间隔期间顺序生成的存储器存储器的存如果转换执行而不产生异常，则用于指示哪个存储器存储到相同的存储器地址的电路响应于存储器地址处的存储器访问是最新的，以及用于消除在转换间隔期间顺序生成的存储器存储器的电路，如果转换执行而没有产生异常。

9. 发明授权

US5180937A Delay compensator and monitor circuit having timing generator and sequencer 失效
标题翻译：具有定时发生器和定序器的延时补偿器和监视电路
公开(公告)号：US5180937A
公开(公告)日：1993-01-19
申请号：US843700
申请日：1992-02-28
申请人： Douglas Laird , Godfrey P. D'Souza
发明人： Douglas Laird , Godfrey P. D'Souza
IPC分类号： H03K5/00 , H03K5/13
CPC分类号： H03K5/133 , H03K2005/00097 , H03K2005/00123 , H03K2005/0013 , H03K2005/00143
摘要： A delay compensator circuit is disclosed to compensate for variations in temperature, supply voltage and process. A monitor circuit is further disclosed that allows the monitoring of the delay of a delay element. The delay compensator circuit and monitor circuit lend themselves easily to the ASIC design methodology since they use conventional ASIC building blocks; namely gates, memory elements and delay elements. The delay compensator and monitor use a time base to track variations in circuit parameters by monitoring the delay through a delay element (delay line or sub-circuit). Compensation may be achieved by switching delays in or out of the circuit to be compensated based on variations of temperature, voltage, and process as measured using the time base. The delay compensator permits the designer to control the output hold time independently of the output delay time. The delay compensator enables a latching device to hold the output signal for the required duration after a reference.
摘要翻译：公开了一种延迟补偿电路来补偿温度，电源电压和工艺的变化。还公开了一种监视电路，其允许监视延迟元件的延迟。延迟补偿电路和监控电路很容易适用于ASIC设计方法，因为它们使用传统的ASIC构建块; 即门，存储元件和延迟元件。延迟补偿器和监视器通过监视通过延迟元件（延迟线或子电路）的延迟来使用时基来跟踪电路参数的变化。可以通过基于使用时基测量的温度，电压和过程的变化来切换要补偿的电路中的延迟来实现补偿。延迟补偿器允许设计者独立于输出延迟时间来控制输出保持时间。延迟补偿器使得锁存装置能够在参考之后保持所需持续时间的输出信号。

10. 发明申请

US20100011233A1 ADAPTIVE POWER CONTROL 有权
标题翻译：自适应功率控制
公开(公告)号：US20100011233A1
公开(公告)日：2010-01-14
申请号：US12502685
申请日：2009-07-14
申请人： Sameer Halepete , H. Peter Anvin , Zongjian Chen , Godfrey P. D'Souza , Marc Fleischmann , Keith Klayman , Thomas Lawrence , Andrew Read
发明人： Sameer Halepete , H. Peter Anvin , Zongjian Chen , Godfrey P. D'Souza , Marc Fleischmann , Keith Klayman , Thomas Lawrence , Andrew Read
IPC分类号： G06F1/26 , G06F1/00
CPC分类号： G06F1/3203 , G06F1/08 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A method for controlling the power used by a computer including the steps of measuring the operating characteristics of a central processor of the computer, determining when the operating characteristics of the central processor are significantly different than required by the operations being conducted, and changing the operating characteristics of the central processor to a level commensurate with the operations being conducted.
摘要翻译：一种用于控制计算机使用的功率的方法，包括以下步骤：测量计算机的中央处理器的操作特性，确定中央处理器的操作特性何时与正在进行的操作所要求的显着不同，以及改变操作中央处理器的特性与正在进行的操作相当。

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