专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090072858A1 HETEROGENEOUS CONFIGURABLE INTEGRATED CIRCUIT 有权
标题翻译：异构可配置集成电路
公开(公告)号：US20090072858A1
公开(公告)日：2009-03-19
申请号：US11855666
申请日：2007-09-14
申请人： Godfrey P. D'Souza , Douglas Laird , Malcolm J. Wing , Colin N. Murphy , Dana L. How , Robert Yu , Jay B. Patel , Ivo Dobbelaere , Jason Golbus , Suresh Subramaniam , Mukunda Krishnappa , Pohrong R. Chu , Dave Trossen , Kevin James
发明人： Godfrey P. D'Souza , Douglas Laird , Malcolm J. Wing , Colin N. Murphy , Dana L. How , Robert Yu , Jay B. Patel , Ivo Dobbelaere , Jason Golbus , Suresh Subramaniam , Mukunda Krishnappa , Pohrong R. Chu , Dave Trossen , Kevin James
IPC分类号： H03K19/173
CPC分类号： H03K19/177
摘要： A system including a plurality of programmable logic blocks, a plurality of special-purpose blocks, and a configurable high-speed mesh interconnect fabric operatively connecting the plurality of programmable logic blocks and the plurality of special-purpose blocks, where the configurable high-speed mesh interconnect fabric is configured to implement a plurality of interconnect pipeline buses spanning across the system.
摘要翻译：一种包括多个可编程逻辑块，多个特殊用途块和可操作地连接多个可编程逻辑块和多个专用块的可配置高速网状互连结构的系统，其中可配置的高速网状互连结构被配置为实现横跨系统的多个互连管线总线。

2. 发明授权

US07557605B2 Heterogeneous configurable integrated circuit 有权
标题翻译：异构可配置集成电路
公开(公告)号：US07557605B2
公开(公告)日：2009-07-07
申请号：US11855666
申请日：2007-09-14
申请人： Godfrey P. D'Souza , Douglas Laird , Malcolm J. Wing , Colin N. Murphy , Dana L. How , Robert Yu , Jay B. Patel , Ivo Dobbelaere , Jason Golbus , Suresh Subramaniam , Mukunda Krishnappa , Pohrong R. Chu , Dave Trossen , Kevin James
发明人： Godfrey P. D'Souza , Douglas Laird , Malcolm J. Wing , Colin N. Murphy , Dana L. How , Robert Yu , Jay B. Patel , Ivo Dobbelaere , Jason Golbus , Suresh Subramaniam , Mukunda Krishnappa , Pohrong R. Chu , Dave Trossen , Kevin James
IPC分类号： H03K19/173
CPC分类号： H03K19/177
摘要： A system including a plurality of programmable logic blocks, a plurality of special-purpose blocks, and a configurable high-speed mesh interconnect fabric operatively connecting the plurality of programmable logic blocks and the plurality of special-purpose blocks, where the configurable high-speed mesh interconnect fabric is configured to implement a plurality of interconnect pipeline buses spanning across the system.
摘要翻译：一种包括多个可编程逻辑块，多个特殊用途块和可操作地连接多个可编程逻辑块和多个专用块的可配置高速网状互连结构的系统，其中可配置的高速网状互连结构被配置为实现横跨系统的多个互连管线总线。

3. 发明授权

US5180937A Delay compensator and monitor circuit having timing generator and sequencer 失效
标题翻译：具有定时发生器和定序器的延时补偿器和监视电路
公开(公告)号：US5180937A
公开(公告)日：1993-01-19
申请号：US843700
申请日：1992-02-28
申请人： Douglas Laird , Godfrey P. D'Souza
发明人： Douglas Laird , Godfrey P. D'Souza
IPC分类号： H03K5/00 , H03K5/13
CPC分类号： H03K5/133 , H03K2005/00097 , H03K2005/00123 , H03K2005/0013 , H03K2005/00143
摘要： A delay compensator circuit is disclosed to compensate for variations in temperature, supply voltage and process. A monitor circuit is further disclosed that allows the monitoring of the delay of a delay element. The delay compensator circuit and monitor circuit lend themselves easily to the ASIC design methodology since they use conventional ASIC building blocks; namely gates, memory elements and delay elements. The delay compensator and monitor use a time base to track variations in circuit parameters by monitoring the delay through a delay element (delay line or sub-circuit). Compensation may be achieved by switching delays in or out of the circuit to be compensated based on variations of temperature, voltage, and process as measured using the time base. The delay compensator permits the designer to control the output hold time independently of the output delay time. The delay compensator enables a latching device to hold the output signal for the required duration after a reference.
摘要翻译：公开了一种延迟补偿电路来补偿温度，电源电压和工艺的变化。还公开了一种监视电路，其允许监视延迟元件的延迟。延迟补偿电路和监控电路很容易适用于ASIC设计方法，因为它们使用传统的ASIC构建块; 即门，存储元件和延迟元件。延迟补偿器和监视器通过监视通过延迟元件（延迟线或子电路）的延迟来使用时基来跟踪电路参数的变化。可以通过基于使用时基测量的温度，电压和过程的变化来切换要补偿的电路中的延迟来实现补偿。延迟补偿器允许设计者独立于输出延迟时间来控制输出保持时间。延迟补偿器使得锁存装置能够在参考之后保持所需持续时间的输出信号。

4. 发明授权

US5058110A Protocol processor 失效
标题翻译：协议处理器
公开(公告)号：US5058110A
公开(公告)日：1991-10-15
申请号：US346648
申请日：1989-05-03
申请人： Robert Beach , Mark Bryers , Casey Cox , Richard Fall , Norman Finn , Douglas Laird
发明人： Robert Beach , Mark Bryers , Casey Cox , Richard Fall , Norman Finn , Douglas Laird
IPC分类号： G06F13/12 , H04L12/44 , H04L12/56
CPC分类号： H04L49/351 , G06F13/128 , H04L2012/445 , H04L49/3027
摘要： A computer network method and apparatus. The present invention comprises a computer network having one or more hubs, each hub comprising one or more connection means for connection of computing devices to the network. Each connection means comprising a first interface means for coupling with a computing device, a second interface means for coupling with the network and a protocol processing means. The protocol processing means receives message packets and, depending on the message type, processing the message as either a network control message or a data transfer message. The present invention provides for "flow through" of data in the case of data transfer messages. The present invention further provides for calculation of checksum bytes as a data packet is received by the protocol processing means.
摘要翻译：计算机网络方法和装置。本发明包括具有一个或多个集线器的计算机网络，每个集线器包括用于将计算设备连接到网络的一个或多个连接装置。每个连接装置包括用于与计算设备耦合的第一接口装置，用于与网络耦合的第二接口装置和协议处理装置。协议处理装置接收消息分组，并且根据消息类型将消息处理为网络控制消息或数据传送消息。本发明提供了在数据传输消息的情况下“数据流”。本发明还提供了由协议处理装置接收到的数据分组的校验和字节的计算。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式