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    • 2. 发明授权
    • Shift register unit and gate drive device for liquid crystal display
    • 移位寄存器单元和液晶显示器的栅极驱动装置
    • US08199870B2
    • 2012-06-12
    • US12875556
    • 2010-09-03
    • Guangliang ShangSeung Woo Han
    • Guangliang ShangSeung Woo Han
    • G11C19/00
    • G11C19/184G11C19/28
    • An embodiment of the present invention discloses a shift register unit and a gate drive device for a liquid crystal display. The shift register unit, on the basis of a structure of 12 transistors and 1 capacitor in the prior art, enables both the drain of the seventh thin film transistor and the gate and the drain of the ninth thin film transistor being connected to the second clock signal input terminal, such that a leakage current would not be generated among the seventh thin film transistor, the eighth thin film transistor, the ninth thin film transistor and the tenth thin film transistor when a high level signal is outputted from the shift register unit, thus power consumption of the shift register unit may be reduced.
    • 本发明的实施例公开了一种用于液晶显示器的移位寄存器单元和栅极驱动装置。 基于现有技术中的12个晶体管和1个电容器的结构,移位寄存器单元能够使第七薄膜晶体管的漏极和栅极与第九薄膜晶体管的漏极连接到第二时钟 信号输入端子,使得当从移位寄存器单元输出高电平信号时,在第七薄膜晶体管,第八薄膜晶体管,第九薄膜晶体管和第十薄膜晶体管中不会产生漏电流, 因此可以减少移位寄存器单元的功耗。
    • 4. 发明授权
    • Array substrate and shift register
    • 阵列基板和移位寄存器
    • US08508458B2
    • 2013-08-13
    • US12976060
    • 2010-12-22
    • Seung Woo HanGuangliang Shang
    • Seung Woo HanGuangliang Shang
    • G09G3/36
    • G09G3/3677G09G3/3659G09G2310/0205G11C19/184G11C19/28
    • An array substrate and a shift register directly fabricated thereon are provided. The shift register comprises a plurality of shift register units each connected to respective one of gate lines of the array substrate. The plurality of shift register units are divided into three groups. As to any two adjacent shift register units of each group, a signal output terminal of the following shift register unit is connected to a reset signal input terminal of the preceding shift register unit, and a signal output terminal of the preceding shift register unit is connected to a start voltage timing signal input terminal of the following shift register unit. Each group of shift register units are controlled by two clock signals, and the two clock signals alternately control two adjacent shift register units of each group. Both the first shift register unit and the third shift register unit are connected to a first start voltage timing signal input terminal, and the second shift register unit is connected to a second start voltage timing signal input terminal.
    • 提供了直接制造在其上的阵列基板和移位寄存器。 移位寄存器包括多个移位寄存器单元,每个移位寄存器单元各自连接到阵列基板的相应一个栅极线。 多个移位寄存器单元被分成三组。 对于每个组的任何两个相邻移位寄存器单元,下一个移位寄存器单元的信号输出端连接到前一移位寄存器单元的复位信号输入端,并且前一移位寄存器单元的信号输出端连接 到下一个移位寄存器单元的启动电压定时信号输入端。 每组移位寄存器单元由两个时钟信号控制,两个时钟信号交替地控制每个组的两个相邻的移位寄存器单元。 第一移位寄存器单元和第三移位寄存器单元都连接到第一开始电压定时信号输入端,并且第二移位寄存器单元连接到第二启动电压定时信号输入端。
    • 5. 发明授权
    • Shift register unit, gate driving device for display and liquid crystal display
    • 移位寄存器单元,用于显示和液晶显示的门驱动装置
    • US09224498B2
    • 2015-12-29
    • US13106947
    • 2011-05-13
    • Guangliang ShangSeung Woo Han
    • Guangliang ShangSeung Woo Han
    • G09G3/36G11C19/28
    • G11C19/28G09G3/3677G09G2310/0286
    • A shift register unit includes an input module for inputting a second clock signal or a third clock signal, and for inputting a frame starting signal, a first clock signal, a low voltage signal, a reset signal as well as a first signal and a second signal transmitted from a next neighboring shift register unit; a processing module for generating a gate driving signal and allowing a level of at least one of first junctions formed by at least two TFTs to be maintained at low level in a frame interval during which the second clock signal or the third clock signal inputted from the input module is maintained at low level; and an output module for transmitting the gate driving signal generated by the processing module.
    • 移位寄存器单元包括用于输入第二时钟信号或第三时钟信号的输入模块,以及用于输入帧起始信号,第一时钟信号,低电压信号,复位信号以及第一信号的第二信号 信号从下一个相邻移位寄存器单元发送; 处理模块,用于产生栅极驱动信号,并且允许由至少两个TFT形成的至少一个第一结的电平在帧间隔中保持在低电平,在该间隔期间,从第二时钟信号或第三时钟信号输入的第二时钟信号 输入模块维持在低电平; 以及用于发送由处理模块生成的门驱动信号的输出模块。