专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09634679B1 Digital down converter with equalization 有权
公开(公告)号：US09634679B1
公开(公告)日：2017-04-25
申请号：US15242467
申请日：2016-08-19
申请人： Guzik Technical Enterprises
发明人： Anatoli B. Stein , Semen P. Volfbeyn , Alexander Taratorin , Igor Tarnikov , Valeriy Serebryanskiy
IPC分类号： H03M1/12 , H03M1/06 , H03M1/00
CPC分类号： H03M1/0626 , H03M1/00 , H03M1/0695 , H03M1/12 , H03M1/1215 , H03M1/1245 , H04B1/0021
摘要： A digital down converter with equalization includes a composite ADC that performs demodulation of a received analog signal, converting the signal into in phase baseband signal and quadrature baseband signal. Equalization is performed to correct for misalignment of the frequency responses of the sub-ADCs in the composite ADC. In a form, ADC output signals are applied to a mixer array to frequency down-shift the digital form of the input signal, followed by digital filtering to effect convolutions of portions of the digital form of the input signal with a set of convolution coefficients determined so that the net processing is mathematically equivalent to down conversion with equalization. In another form, the ADC output signals are directly applied to a digital filter to effect both frequency down-shifting and convolutions, with filter coefficients determined so that the net processing is mathematically equivalent to down conversion with equalization.

2. 发明授权

US08879675B1 Synchronization system for a wireless receiver 有权
标题翻译：无线接收机的同步系统
公开(公告)号：US08879675B1
公开(公告)日：2014-11-04
申请号：US14283590
申请日：2014-05-21
申请人： Guzik Technical Enterprises
发明人： Anatoli B. Stein , Semen P. Velfbeyn
IPC分类号： H04L27/06 , H04L7/04 , H04L7/00
CPC分类号： H04L7/042 , H04L7/0004 , H04L27/0014 , H04L2027/0016 , H04L2027/0036 , H04L2027/0067 , H04L2027/0095
摘要： A synchronization system for initial setup of phases of local oscillators in a wireless receiver of a communication system characterized by transmission of data packets having a predetermined preamble consisting of M identical sections of L symbols followed by a single section of the same kind, multiplied by −1, and wherein the wireless receiver is operative to perform decimation in an RF demodulator. The synchronization system includes a twofold correlator, an accumulator, a multiplier, a threshold comparator, a carrier phase former and a clock phase former, and operates at a decimated symbols frequency, and performs not only preamble detection, but also symbols clock phase detection together with carrier phase detection, while enabling the theoretically possible noise immunity.
摘要翻译：一种用于在通信系统的无线接收机中初始建立本地振荡器的相位的同步系统，其特征在于传输具有由相同类型的单个部分的M个相同部分的M个相同部分组成的预定前导码的数据分组， 1，并且其中无线接收器可操作以在RF解调器中执行抽取。同步系统包括双重相关器，累加器，乘法器，阈值比较器，载波相位变换器和时钟相位变换器，并且以抽取符号频率工作，不仅执行前导码检测，而且还一起执行符号时钟相位检测具有载波相位检测，同时实现理论上可能的抗噪声能力。

3. 发明授权

US08542142B2 Interleaved analog to digital converter with reduced number of multipliers for digital equalization 有权
标题翻译：具有数字均衡的乘法器数量减少的交错模数转换器
公开(公告)号：US08542142B2
公开(公告)日：2013-09-24
申请号：US13772925
申请日：2013-02-21
申请人： Guzik Technical Enterprises
发明人： Anatoli B. Stein , Semen P. Volfbeyn , Valeriy Serebryanskiy
IPC分类号： H03M1/12
CPC分类号： H03M1/121 , H03M1/0626 , H03M1/1215
摘要： A digital equalizer with a reduced number of multipliers for correction of the frequency responses of an interleaved ADC is disclosed. An exemplary interleaved analog to digital converter with digital equalization includes a composite ADC including M time interleaved sub-ADC, a demultiplexer, samples repositioning unit, a first PreFIRs transformer, a second PreFIRs transformer, K double buffer FIR filters, a PostFIRs transformer, a samples sequence restoration unit, and a multiplexer, coupled in series and providing an equalized, frequency response-corrected output.
摘要翻译：公开了一种数字均衡器，其具有用于校正交错ADC的频率响应的乘法器数目减少。具有数字均衡的示例性交错模数转换器包括复合ADC，包括M个时间交错子ADC，解复用器，样本重定位单元，第一PreFIR变压器，第二PreFIR变压器，K双缓冲FIR滤波器，PostFIR变压器，采样序列恢复单元和多路复用器，串联耦合并提供均衡的频率响应校正输出。

4. 发明申请

US20130214958A1 INTERLEAVED ANALOG TO DIGITAL CONVERTER WITH REDUCED NUMBER OF MULTIPLIERS FOR DIGITAL EQUALIZATION 有权
标题翻译：用于数字均衡的数字转换器的数字转换器的简化模拟
公开(公告)号：US20130214958A1
公开(公告)日：2013-08-22
申请号：US13772925
申请日：2013-02-21
申请人： Guzik Technical Enterprises
发明人： Anatoli B. Stein , Semen P. Volfbeyn , Valeriy Serebryanskiy
IPC分类号： H03M1/12
CPC分类号： H03M1/121 , H03M1/0626 , H03M1/1215
摘要： A digital equalizer with a reduced number of multipliers for correction of the frequency responses of an interleaved ADC is disclosed. An exemplary interleaved analog to digital converter with digital equalization includes a composite ADC including M time interleaved sub-ADC, a demultiplexer, samples repositioning unit, a first PreFIRs transformer, a second PreFIRs transformer, K double buffer FIR filters, a PostFIRs transformer, a samples sequence restoration unit, and a multiplexer, coupled in series and providing an equalized, frequency response-corrected output.
摘要翻译：公开了一种数字均衡器，其具有用于校正交错ADC的频率响应的乘法器数目减少。具有数字均衡的示例性交错模数转换器包括复合ADC，包括M个时间交错子ADC，解复用器，样本重定位单元，第一PreFIR变压器，第二PreFIR变压器，K双缓冲FIR滤波器，PostFIR变压器，采样序列恢复单元和多路复用器，串联耦合并提供均衡的频率响应校正输出。

5. 发明申请

US20130169463A1 INTERLEAVED ANALOG TO DIGITAL CONVERTER WITH DIGITAL EQUALIZATION 有权
标题翻译：具有数字均衡功能的数字转换器的模拟
公开(公告)号：US20130169463A1
公开(公告)日：2013-07-04
申请号：US13730071
申请日：2012-12-28
申请人： Guzik Technical Enterprises
发明人： Anatoli B. Stein , Semen P. Volfbeyn
IPC分类号： H03M1/12
CPC分类号： H03M1/12 , H03M1/1038 , H03M1/1215
摘要： An interleaved analog to digital converter with digital equalization includes a conversion-measurement-equalization unit and residual distortions reduction unit, and is operative in a calibration mode and converter mode. The conversion-measurement-equalization unit includes a composite ADC containing N sub-ADCs, equalizer, responses measurement unit and a coefficients calculator. The residual distortions reduction unit uses received measured frequency responses and equalizer coefficients, both from the conversion-measurement-equalization unit, as a base to calculate corrected frequency responses that are applied to the coefficients calculator for generation of equalizer coefficients for application to the equalizer. A residual distortions calculator of the residual distortions reduction unit, is responsive to measured frequency responses from the composite ADC and a current set of equalizer coefficients applied to the equalizer, to calculate residual frequency distortions that should have been expected to appear in the output signal of the ADC system if the current equalizer coefficients remain applied to the equalizer.
摘要翻译：具有数字均衡的交错模数转换器包括转换测量均衡单元和残余失真减少单元，并且在校准模式和转换器模式下操作。转换测量均衡单元包括包含N个子ADC，均衡器，响应测量单元和系数计算器的复合ADC。剩余失真减小单元使用来自转换测量均衡单元的接收的测量频率响应和均衡器系数作为基础，以计算应用于系数计算器的校正频率响应，以产生用于均衡器的均衡器系数。剩余失真减小单元的残余失真计算器响应于来自复合ADC的测量的频率响应和施加到均衡器的当前均衡器系数集合，以计算应该预期出现在输出信号中的残余频率失真 ADC系统，如果电流均衡器系数保持施加到均衡器。

6. 发明授权

US08477445B2 Write clock synchronization appartus for magnetic recording disk drives with patterned media 有权
标题翻译：为带有图案介质的磁记录磁盘驱动器写入时钟同步程序
公开(公告)号：US08477445B2
公开(公告)日：2013-07-02
申请号：US13706311
申请日：2012-12-05
申请人： Guzik Technical Enterprises
发明人： Anatoli B. Stein , Semen P. Volfbeyn
IPC分类号： G11B5/09
CPC分类号： G11B20/10222 , G11B5/012 , G11B5/59616 , G11B5/746 , G11B20/1024 , G11B20/10435 , G11B2220/252
摘要： A write clock generator for use in writing data to a rotating patterned magnetic media disk is disclosed. The generator includes a magnetic read head for generating a succession of servo signals representative of succession of servo magnetization patterns detected from a corresponding succession of arcuate sectors along a circular data track on the disk. A preamble processor generates a corresponding succession of sector pair signals representative of the lengths of adjacent sectors along the data track on a rolling pair-wise basis. A next sector length predictor processor determines for a succession of pairs of sectors, a length ratio of the lengths of the sectors in the respective pairs of sectors. A clock generator generates a periodic clock for each sector of the succession of sectors, wherein the clock rate associated with a current sector has an associated phase deviation relative to a clock rate associated with a previous sector, which is proportional to the length ratio for the current sector and the previous sector.
摘要翻译：公开了一种用于将数据写入旋转图案化磁介质盘的写时钟发生器。该发生器包括一个磁读头，用于产生一系列伺服信号，该伺服信号代表沿着圆盘上的圆形数据轨道从相应的一系列弧形扇区中检测出的伺服磁化模式的连续。前导处理器在滚动成对的基础上产生表示沿着数据轨道的相邻扇区的长度的相应连续的扇区对信号。下一扇区长度预测器处理器确定一连串的扇区对，各扇区对中的扇区的长度的长度比。时钟发生器为该连续扇区的每个扇区生成周期性时钟，其中与当前扇区相关联的时钟速率相对于与先前扇区相关联的时钟速率具有相关联的相位偏移，其与当前行业和上一个行业。

7. 发明授权

US10749541B1 Time interleaved analog to digital converter with digital equalization and a reduced number of multipliers 有权
公开(公告)号：US10749541B1
公开(公告)日：2020-08-18
申请号：US16736352
申请日：2020-01-07
申请人： Guzik Technical Enterprises
发明人： Anatoli B. Stein , Semen P. Volfbeyn , Valeriy Serebryanskiy
IPC分类号： H03M1/12 , H03M1/06
摘要： A digital equalizer with reduced number of multipliers for correction of the frequency responses of an interleaved analog-to-digital-converter (ADC) is disclosed. An exemplary interleaved analog to digital converter with digital equalization includes at least one composite ADC including M time-interleaved sub-ADCs, and an equalization configuration deploying a Pre-FIR transformers unit, a FIRs assembly unit, and a Post-FIR transformers unit. The FIRs assembly unit includes a finite impulse response (FIR) filter network which is operative pursuant to a Fast Filtering Algorithm as an alternative to a conventional finite impulse response network, enabling a reduction of the number of multipliers compared to conventional FIR filter-based equalization networks for ADCs.

8. 发明授权

US10534018B1 Time base correction method for high accuracy sampling scope-based measurements 有权
公开(公告)号：US10534018B1
公开(公告)日：2020-01-14
申请号：US16249234
申请日：2019-01-16
申请人： Guzik Technical Enterprises
发明人： Anatoli B. Stein , Alexander Taratorin , Valeriy Serebryanskiy
IPC分类号： G01D18/00 , G01D21/00 , G01P21/00 , G01R35/00 , G01R13/02 , H04B10/079
摘要： A method and apparatus for resolving time base-generated errors from sampling scope-based measurements. Mutually synchronized repetitive waveform-to-be-analyzed signals (WAS) and repetitive sinusoidal reference signals (RS) are respectively applied to a first channel and a second channel of a sampling scope. A time base generator applies a sampling signal to the first and second channels. An average sine wave period Tav for k samples of RS is determined, followed by determination of phase error φk for each of the k samples, corresponding to phase differences between an ideal sine wave signal and the applied reference sinusoidal signal. Time base error values dk for k samples are calculated from dk=φk*Tav/2π. Error values dk correct time base errors in the sampling signal, and the WAS is re-sampled at sampling times adjusted by dk.

9. 发明授权

US09506951B2 Method and apparatus for data acquisition with waveform trigger 有权
标题翻译：用波形触发进行数据采集的方法和装置
公开(公告)号：US09506951B2
公开(公告)日：2016-11-29
申请号：US14992373
申请日：2016-01-11
申请人： Guzik Technical Enterprises
发明人： Alexander Taratorin , Anatoli B. Stein , Lauri Viitas , Igor Tarnikov
IPC分类号： G01R13/00 , G01R13/02
CPC分类号： G01R13/0254 , G01R13/029
摘要： Digital signal acquisition system is triggered when an input waveform matches a known reference waveform. This is achieved by calculating a stream of error metric values defined as a sum of absolute values of differences between incoming and reference samples. An error metric is calculated using only byte operations, which is advantageous for hardware implementation. A waveform trigger is determined by a sample index corresponding to a minimum value of the error metric and corresponds to a best match between input and reference waveforms. A waveform trigger is used for synchronous averaging and estimating time domain noise voltage. A reference waveform updates in poor SNR conditions to provide robust estimates of time domain noise by reducing reference waveform jitter.
摘要翻译：当输入波形匹配已知的参考波形时，触发数字信号采集系统。这是通过计算定义为输入和参考样本之间的差异的绝对值之和的误差度量值流来实现的。仅使用字节操作来计算错误度量，这有利于硬件实现。波形触发由与误差度量的最小值相对应的采样索引确定，并且对应于输入和参考波形之间的最佳匹配。波形触发用于同步平均和估计时域噪声电压。参考波形在较差的SNR条件下更新，以通过减少参考波形抖动来提供时域噪声的鲁棒估计。

10. 发明授权

US09450598B2 Two-stage digital down-conversion of RF pulses 有权
标题翻译： RF脉冲的两级数字下变频
公开(公告)号：US09450598B2
公开(公告)日：2016-09-20
申请号：US14992364
申请日：2016-01-11
申请人： Guzik Technical Enterprises
发明人： Alexander Taratorin , Anatoli B. Stein , Lauri Viitas , Igor Tarnikov
IPC分类号： H04B1/26 , H03M1/12 , G01S7/35 , H04B1/00
CPC分类号： G01S7/352 , G01S7/021 , G01S2007/358 , H04B1/0039
摘要： A two-stage digital down-conversion device for optimal detection of varying RF pulses incorporates a front end analog to digital converter (ADC), which samples an input RF signal and performs a first stage digital down conversion in wide bandwidth by means of two digital local oscillator multipliers, low pass filters and decimators. A stream of first stage quadrature I and Q samples is analyzed by a first stage I/Q processor. The I/Q processor generates an RF pulse trigger based on a first-stage envelope signal, center frequency and frequency span data which are used for a second stage narrow band digital down-conversion. The second stage digital down-conversion is based on mixing the first stage I and Q data samples with a second stage local oscillator, further low pass filtering and decimation using a second bandwidth. A stream of second stage I/Q quadrature samples has an optimal signal to noise ratio and allows accurate estimation of RF pulse parameters (magnitude, phase and frequency) by means of a second I/Q signal processor and/or by storing second I/Q data for subsequent processing and analysis.
摘要翻译：用于最佳检测变化的RF脉冲的两级数字下变频装置包含前端模/数转换器（ADC），其对输入RF信号进行采样，并通过两个数字转换器（ADC）在宽带宽中执行第一级数字下变频本地振荡器乘法器，低通滤波器和抽取器。通过第一级I / Q处理器分析第一级正交I和Q采样流。 I / Q处理器基于用于第二级窄带数字下变频的第一级包络信号，中心频率和频率跨度数据产生RF脉冲触发。第二级数字下变频基于将第一级I和Q数据样本与第二级本地振荡器混合，使用第二带宽进一步进行低通滤波和抽取。第二级I / Q正交采样流具有最佳的信噪比，并且允许借助于第二I / Q信号处理器和/或通过存储第二I / Q信号来精确地估计RF脉冲参数（幅度，相位和频率） Q数据进行后续处理和分析。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式