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1. 发明授权

US08633762B2 Integrated circuit chip and transmitting /receiving system including the same 有权
标题翻译：集成电路芯片和发送/接收系统包括相同的
公开(公告)号：US08633762B2
公开(公告)日：2014-01-21
申请号：US13333692
申请日：2011-12-21
申请人： Yong-Ju Kim , Dae-Han Kwon , Hae-Rang Choi , Jae-Min Jang
发明人： Yong-Ju Kim , Dae-Han Kwon , Hae-Rang Choi , Jae-Min Jang
IPC分类号： H01L25/00
CPC分类号： G06F13/4077
摘要： A system for transmitting data includes a plurality of data lines configured to transmit the data and a transmitting chip configured to output the data to the data lines and perform a crosstalk prevention operation in response to a data pattern of the data to be transmitted through the data lines and array information of the data lines to prevent crosstalk from occurring in the data lines.
摘要翻译：用于发送数据的系统包括被配置为发送数据的多条数据线和被配置为将数据输出到数据线的发送芯片，并且响应于要通过数据发送的数据的数据模式执行串扰防止操作数据线的线和阵列信息，以防止在数据线中发生串扰。

2. 发明授权

US08339159B2 Input buffer circuit of semiconductor apparatus 有权
标题翻译：半导体装置的输入缓冲电路
公开(公告)号：US08339159B2
公开(公告)日：2012-12-25
申请号：US12540496
申请日：2009-08-13
申请人： Ji-Wang Lee , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
发明人： Ji-Wang Lee , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
IPC分类号： H03K5/153
CPC分类号： H03K5/153
摘要： The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal.
摘要翻译：半导体装置的输入缓冲电路包括第一缓冲单元，其由第一电压端子和第二电压端子之间的电压电平差激活，并且通过比较第一电压电平和第二电压电平的电压电平来生成第一比较信号和第二比较信号参考电压和输入信号; 控制单元，其通过比较所述参考电压和所述第二比较信号的电压电平来控制在所述第二电压端子和接地端子之间流动的电流量; 以及第二缓冲单元，其通过比较输入信号和第一比较信号的电压电平来产生输出信号。

3. 发明授权

US08026701B2 Voltage regulator for a synchronous clock system to reduce clock tree jitter 失效
标题翻译：用于同步时钟系统的电压调节器，以减少时钟树抖动
公开(公告)号：US08026701B2
公开(公告)日：2011-09-27
申请号：US12265908
申请日：2008-11-06
申请人： Hyung-Soo Kim , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Hyung-Soo Kim , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： G05F1/652
CPC分类号： G11C5/147
摘要： A voltage regulator with an adaptive bandwidth, including a first buffer chain, a voltage generating unit, a trimming capacitor unit, a second buffer chain, and a control unit. The first buffer chain delays a clock signal using an external voltage as a supply voltage. The voltage generating unit generates a regulated voltage on the basis a reference voltage. The trimming capacitor unit controls a load capacitance of the voltage generating unit. The second buffer chain delays the clock signal using the regulated voltage as a supply voltage. The control unit adjusts the load capacitance by detecting a delay difference of clocks output from the first and second buffer chains.
摘要翻译：具有自适应带宽的电压调节器，包括第一缓冲链，电压产生单元，微调电容器单元，第二缓冲链和控制单元。第一个缓冲链使用外部电压作为电源电压来延迟时钟信号。电压产生单元基于参考电压产生调节电压。微调电容器单元控制电压产生单元的负载电容。第二缓冲链使用调节电压作为电源电压来延迟时钟信号。控制单元通过检测从第一和第二缓冲器链输出的时钟的延迟差来调节负载电容。

4. 发明授权

US07884659B2 Phase mixer and delay locked loop including the same 有权
标题翻译：相位混合器和延迟锁定环包括相同
公开(公告)号：US07884659B2
公开(公告)日：2011-02-08
申请号：US12347298
申请日：2008-12-31
申请人： Jae-Min Jang , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Chang-Kun Park
发明人： Jae-Min Jang , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Chang-Kun Park
IPC分类号： H03K11/16
CPC分类号： H03L7/0814 , H03K5/13 , H03K2005/00052 , H03K2005/00065 , H03L7/0818
摘要： A phase mixer includes a phase mixing unit configured to mix a phase of a first input signal and a phase of a second input signal in response to a phase control signal and output a phase mixed signal whose phase is varied by one or more units of a unit phase value, and a phase value adjusting unit configured to control an operation of the phrase mixing unit so that the unit phase value is adjusted in response to a code signal coding at least one of a process, voltage, or temperature (PVT) variation.
摘要翻译：相位混合器包括：相位混合单元，被配置为响应于相位控制信号混合第一输入信号的相位和第二输入信号的相位，并输出相位混合信号，该相位混合信号的相位由一个或多个单位单位相位值，以及相位值调整单元，被配置为控制短语混合单元的操作，使得响应于代码信号来编码单位相位值，编码信号编码处理，电压或温度（PVT）变化中的至少一个。

5. 发明授权

US07868667B2 Output driving device 失效
标题翻译：输出驱动装置
公开(公告)号：US07868667B2
公开(公告)日：2011-01-11
申请号：US12411893
申请日：2009-03-26
申请人： Chang-Kun Park , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang
发明人： Chang-Kun Park , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang
IPC分类号： H03K3/00
CPC分类号： H03K19/0027 , H03K19/00323 , H03K2005/00123 , H03K2217/0018
摘要： An output driving device capable of improving a slew rate is provided. The output driving device includes a push-pull type driving unit configured with a pull-up PMOS transistor and a pull-down NMOS transistor, wherein body biases of the pull-up PMOS transistor and the pull-down NMOS transistor are controlled for control of a slew rate of an output signal of the driving unit.
摘要翻译：提供了能够提高转换速度的输出驱动装置。输出驱动装置包括配置有上拉PMOS晶体管和下拉式NMOS晶体管的推挽型驱动单元，其中上拉PMOS晶体管和下拉式NMOS晶体管的体偏置被控制以控制驱动单元的输出信号的转换速率。

6. 发明授权

US07847592B2 Buffer circuit of semiconductor memory apparatus 失效
标题翻译：半导体存储装置的缓冲电路
公开(公告)号：US07847592B2
公开(公告)日：2010-12-07
申请号：US12494757
申请日：2009-06-30
申请人： Ji-Wang Lee , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
发明人： Ji-Wang Lee , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
IPC分类号： H03K19/0175 , H03K19/0185
CPC分类号： H03K19/018521
摘要： A buffer circuit of a semiconductor memory apparatus includes a buffering section configured to increase or decrease a voltage level of an output node by comparing a voltage level of an input signal with a voltage level of a reference voltage. A voltage compensation section applies a voltage to the output node in proportion to a variation of the reference voltage when the level of the reference voltage is lower than a target level.
摘要翻译：半导体存储装置的缓冲电路包括：缓冲部，被配置为通过将输入信号的电压电平与参考电压的电压电平进行比较来增大或减小输出节点的电压电平。当参考电压的电平低于目标电平时，电压补偿部分与输出节点成比例地与参考电压的变化成比例。

7. 发明授权

US07826306B2 Semiconductor memory apparatus 有权
标题翻译：半导体存储装置
公开(公告)号：US07826306B2
公开(公告)日：2010-11-02
申请号：US12332298
申请日：2008-12-10
申请人： Ji-Wang Lee , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
发明人： Ji-Wang Lee , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
IPC分类号： G11C8/00
CPC分类号： G11C7/1078 , G11C5/063 , G11C7/02 , G11C7/1084 , G11C7/1093 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028
摘要： A semiconductor memory apparatus includes a clock generator configured to generate an internal clock signal, an asynchronous data input buffer configured to buffer a data input signal through a data pad to output a buffered data signal, and a synchronous data input buffer configured to buffer the buffered data signal synchronously with the internal clock signal, wherein a length of a line, through which the internal clock signal is transmitted to the synchronous data input buffer, is configured to be substantially the same with a length of a line, through which the buffered data is transmitted to the synchronous data input buffer.
摘要翻译：一种半导体存储装置，包括被配置为产生内部时钟信号的时钟发生器，配置成通过数据焊盘缓冲数据输入信号以输出缓冲数据信号的异步数据输入缓冲器，以及被配置为缓冲缓冲的数据输入缓冲器数据信号与内部时钟信号同步，其中通过其将内部时钟信号发送到同步数据输入缓冲器的线路的长度被配置为与线路的长度基本相同，通过该线路的长度，缓冲的数据被发送到同步数据输入缓冲器。

8. 发明授权

US07786783B2 Duty cycle correction circuit with reduced current consumption 失效
标题翻译：占空比校正电路，降低电流消耗
公开(公告)号：US07786783B2
公开(公告)日：2010-08-31
申请号：US12333193
申请日：2008-12-11
申请人： Hee-Woong Song , Yong-Ju Kim , Sung-Woo Han , Jae-Min Jang , Hyung-Soo Kim , Ji-Wang Lee , Chang-Kun Park , Ic-Su Oh , Hae-Rang Choi , Tae-Jin Hwang
发明人： Hee-Woong Song , Yong-Ju Kim , Sung-Woo Han , Jae-Min Jang , Hyung-Soo Kim , Ji-Wang Lee , Chang-Kun Park , Ic-Su Oh , Hae-Rang Choi , Tae-Jin Hwang
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A duty cycle correction circuit includes a signal generating unit including a first signal generating unit coupled to a power supply voltage terminal and configured to output a complementary output signal of an output signal in response to a clock signal, and a second signal generating unit coupled to the power supply voltage terminal and configured to output the output signal in response to a complementary clock signal of the clock signal; a variable resistor unit coupled between the first and second signal generating units configured to vary an amount of current flowing into the signal generating unit according to a duty correction control signal, the duty correction control signal having a voltage level determined based on a voltage level of the output signal; and a current source coupled between the variable resistor unit and a ground voltage terminal configured to supply current to the signal generating unit.
摘要翻译：一种占空比校正电路包括：信号产生单元，包括耦合到电源电压端并被配置为响应于时钟信号输出输出信号的互补输出信号的第一信号产生单元，以及耦合到所述电源电压端子被配置为响应于所述时钟信号的互补时钟信号而输出所述输出信号; 耦合在第一和第二信号发生单元之间的可变电阻器单元，被配置为根据占空比校正控制信号改变流入信号生成单元的电流量，该占空比校正控制信号具有基于电压电平输出信号; 以及耦合在可变电阻器单元和被配置为向信号产生单元提供电流的接地电压端子之间的电流源。

9. 发明授权

US08610475B2 Integrated circuit 有权
标题翻译：集成电路
公开(公告)号：US08610475B2
公开(公告)日：2013-12-17
申请号：US12981764
申请日：2010-12-30
申请人： Yong-Ju Kim , Seong-Jun Lee , Hae-Rang Choi , Jae-Min Jang
发明人： Yong-Ju Kim , Seong-Jun Lee , Hae-Rang Choi , Jae-Min Jang
IPC分类号： H03L7/06
CPC分类号： H03L7/0816
摘要： An integrated circuit includes a delay locked loop configured to delay a reference clock signal by a delay time for delay locking and generate a delay locked clock signal, a clock transmission circuit configured to transmit the delay locked clock signal in response to a clock transmission signal, a duty correction circuit configured to perform duty correction operation on an output clock signal of the clock transmission circuit, and a clock transmission signal generation circuit configured to generate the clock transmission signal in response to a command and burst length information.
摘要翻译：一种集成电路包括：延迟锁定环路，被配置为延迟参考时钟信号延迟锁定的延迟时间，并产生延迟锁定时钟信号;时钟传输电路，被配置为响应于时钟传输信号传输延迟锁定时钟信号; 配置为对时钟发送电路的输出时钟信号进行占空比校正操作的占空比校正电路，以及响应于命令和突发长度信息而生成时钟发送信号的时钟发送信号生成电路。

10. 发明授权

US08319535B2 Delay locked loop 有权
标题翻译：延迟锁定环路
公开(公告)号：US08319535B2
公开(公告)日：2012-11-27
申请号：US13111568
申请日：2011-05-19
申请人： Jae-Min Jang , Yong-Ju Kim , Hae-Rang Choi
发明人： Jae-Min Jang , Yong-Ju Kim , Hae-Rang Choi
IPC分类号： H03L7/06
CPC分类号： H03L7/087 , G11C7/222 , H03L7/0814 , H03L7/0816
摘要： A DLL circuit includes a common delay line configured to generate a delay locked clock by selectively delaying a source clock by one or more unit delays in response to a first delay control code or a second delay control code, a clock cycle detector configured to compare a phase of the source clock with a phase of the delay locked clock in a cycle detection mode and generate the first delay control code corresponding to a delay amount of a cycle of the source clock based on a result of comparing the phases of the source and delay locked clocks, a feedback delay configured to delay the delay locked clock and output a feedback clock, and a delay amount controller configured to compare the phase of the source clock with a phase of the feedback clock in a delay locking mode and change the second delay control code based on a result of comparing the source and feedback clocks.
摘要翻译： DLL电路包括公共延迟线，其配置为通过响应于第一延迟控制代码或第二延迟控制代码选择性地将源时钟延迟一个或多个单位延迟来产生延迟锁定时钟，时钟周期检测器被配置为源时钟的相位以延迟锁定时钟的相位处于周期检测模式，并且基于比较源极和延迟的相位的结果生成与源时钟的周期的延迟量相对应的第一延迟控制代码锁定时钟，被配置为延迟延迟锁定时钟并输出反馈时钟的反馈延迟，以及延迟量控制器，被配置为将延迟锁定模式中的源时钟的相位与反馈时钟的相位进行比较，并且改变第二延迟基于比较源和反馈时钟的结果的控制代码。

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