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1. 发明授权

US4490688A Digital and analog phase detector for a frequency synthesizer 失效
标题翻译：用于频率合成器的数字和模拟相位检测器
公开(公告)号：US4490688A
公开(公告)日：1984-12-25
申请号：US251570
申请日：1981-04-06
申请人： Jaime A. Borras , Jose I. Suarez , Alan M. Victor
发明人： Jaime A. Borras , Jose I. Suarez , Alan M. Victor
IPC分类号： H03C3/09 , H03C3/22 , H03D13/00 , H03J5/02 , H03K23/66 , H03L7/08 , H03L7/193 , H03L7/199 , H04B1/40 , H03L7/12
CPC分类号： H03K21/38 , H03C3/0933 , H03C3/0941 , H03C3/0958 , H03C3/0966 , H03C3/227 , H03D13/005 , H03J5/0281 , H03K23/667 , H03L7/0802 , H03L7/193 , H03L7/199 , H04B1/405
摘要： A sample and hold phase detector for a phase locked loop includes a digital detector for detecting the frequency and phase difference between the reference signal and the voltage controlled oscillator (VCO) signal. In a first mode of operation, the digital detector generates a first signal relating the difference in frequency and in a second mode of operation generates a second signal relating the difference in phase. A capacitor stores the first or second signal depending on the operational mode of the digital detector. The capacitor is selectively discharged in response to a discharge signal produced by the digital detector when either the VCO frequency is higher than the reference frequency or following each detection of a phase difference. A first amplifier is used to bypass a portion of the loop filter to effect rapid changes in VCO frequency in the first mode while a second amplifier couples the control voltage to the VCO via the loop filter to maintain proper VCO frequency in the second mode.
摘要翻译：用于锁相环的采样和保持相位检测器包括用于检测参考信号和压控振荡器（VCO）信号之间的频率和相位差的数字检测器。在第一操作模式中，数字检测器产生与频率差有关的第一信号，而在第二操作模式中产生与相位差有关的第二信号。电容器根据数字检测器的工作模式存储第一或第二信号。当VCO频率高于参考频率或每次检测相位差之后，电容器响应于由数字检测器产生的放电信号而被选择性地放电。第一放大器用于绕过环路滤波器的一部分以在第一模式中实现VCO频率的快速变化，而第二放大器经由环路滤波器将控制电压耦合到VCO以在第二模式中维持适当的VCO频率。

2. 发明授权

US4484153A Voltage converter for a frequency synthesizer 失效
标题翻译：用于频率合成器的电压转换器
公开(公告)号：US4484153A
公开(公告)日：1984-11-20
申请号：US251559
申请日：1981-04-06
申请人： Jaime A. Borras , Ruben J. Gonzalez , Daniel M. Smith , Jose I. Suarez , Alan M. Victor , Alfred B. Wieczorek
发明人： Jaime A. Borras , Ruben J. Gonzalez , Daniel M. Smith , Jose I. Suarez , Alan M. Victor , Alfred B. Wieczorek
IPC分类号： H03C3/09 , H03C3/22 , H03D13/00 , H03J5/02 , H03K23/66 , H03L7/08 , H03L7/193 , H03L7/199 , H04B1/40 , H03L7/18
CPC分类号： H03K21/38 , H03C3/0933 , H03C3/0941 , H03C3/0958 , H03C3/0966 , H03C3/227 , H03D13/005 , H03J5/0281 , H03K23/667 , H03L7/0802 , H03L7/193 , H03L7/199 , H04B1/405
摘要： In a frequency synthesizer phase locked loop including a reference oscillator, a variable reference divider (.div.M), a sample and hold phase detector, a loop filter, a voltage controlled oscillator and a variable divider (.div.N), a voltage converter for controlling the voltage of a control input to the voltage controlled oscillator is disclosed. In the preferred embodiment, the voltage converter has its input connected to the output of a first reference divider in the variable reference divider (.div.M) and its output connected to a control input (varactor diode) of the voltage controlled oscillator. The voltage converter clamps the divider reference signal from the first reference divider and provides a negative voltage level output to bias the varactor diode of the voltage controlled oscillator. Thus, the tuning range of the frequency synthesizer is increased.
摘要翻译：在包括参考振荡器，可变参考分频器（DIVIDED M），采样和保持相位检测器，环路滤波器，压控振荡器和可变分频器（DIVIDED N）的频率合成器锁相环中，用于控制公开了对压控振荡器的控制输入的电压。在优选实施例中，电压转换器的输入连接到可变参考分压器（DIVIDED M）中的第一参考分压器的输出，其输出连接到压控振荡器的控制输入（变容二极管）。电压转换器钳位来自第一参考分压器的分频器参考信号，并提供负电压电平输出以偏压压控振荡器的变容二极管。因此，频率合成器的调谐范围增加。

3. 发明授权

US4631496A Battery saving system for a frequency synthesizer 失效
标题翻译：频率合成器节电系统
公开(公告)号：US4631496A
公开(公告)日：1986-12-23
申请号：US808905
申请日：1985-12-13
申请人： Jaime A. Borras , Jose I. Suarez
发明人： Jaime A. Borras , Jose I. Suarez
IPC分类号： H03C3/09 , H03C3/22 , H03D13/00 , H03J5/02 , H03K23/66 , H03L7/08 , H03L7/193 , H03L7/199 , H04B1/40 , H03L7/18
CPC分类号： H03C3/0966 , H03C3/0933 , H03C3/0941 , H03C3/0958 , H03C3/227 , H03D13/005 , H03J5/0281 , H03K23/66 , H03K23/667 , H03L7/0802 , H03L7/193 , H03L7/199 , H04B1/405
摘要： A frequency synthesized transceiver capable of tuning to a plurality of communication channels is disclosed. The transceiver includes a receiver and a transmitter section which are coupled to the synthesizer which generates the appropriate injection signals to achieve tuning. A battery saving circuit generates a battery saving signal having a predetermined duty cycle and period and is responsive to the phase detector in the synthesizer to disrupt power to the synthesizer while maintaining precise tuning. The battery saver circuit is also responsive to the transceiver. In a normal receive operation, a battery saving circuit synchronizes its battery saving signal with the hold condition of the phase detector to disrupt power to selected modules in the synthesizer without altering the injection frequency of the receiver. In a standby mode, power is disrupted to all modules in the receiver, the selected modules in the phase locked loop and the voltage controlled oscillator. During a transmit mode all battery saving is terminated.
摘要翻译：公开了能够调谐到多个通信信道的频率合成收发器。收发器包括接收器和发射器部分，其耦合到合成器，其产生适当的注入信号以实现调谐。电池节省电路产生具有预定占空比和周期的电池节省信号，并且响应于合成器中的相位检测器来中断合成器的电源，同时保持精确的调谐。电池保护电路也对收发器做出响应。在正常接收操作中，电池节省电路使其电池节省信号与相位检测器的保持状态同步，以将合成器中的选定模块的功率中断，而不改变接收机的注入频率。在待机模式下，接收机中的所有模块，锁相环中的选定模块和压控振荡器的电源中断。在发送模式期间，所有电池节电终止。

4. 发明授权

US06661927B1 System and method for efficiently encoding an image by prioritizing groups of spatially correlated coefficients based on an activity measure 有权
标题翻译：基于活动度量，通过对空间相关系数组进行优先排序来有效地编码图像的系统和方法
公开(公告)号：US06661927B1
公开(公告)日：2003-12-09
申请号：US09628106
申请日：2000-07-27
申请人： Jose I. Suarez , Yolanda Prieto , Yolanda M. Pirez
发明人： Jose I. Suarez , Yolanda Prieto , Yolanda M. Pirez
IPC分类号： G06K936
CPC分类号： H04N19/40 , H04N19/129 , H04N19/132 , H04N19/14 , H04N19/162 , H04N19/63
摘要： An encoder (300) selects (702, 1302, 1304, 1306, 1308) one or more subsets of spatially or temporally correlated transformed data coefficients, on the basis of the significance of each subset in representing the data. The encoder (300) and a complementary decoder (400) may be applied to wavelet transform encoded images (500). The encoder (300) may be implemented on a wireless to Internet gateway server (108), in order to reduce byte size of encoded images (500) sent through a wireless network (112), and reduce the amount of processing that must be performed by a wireless device (118) to decode an image or other data. The decoder (400) and/or encoder (300) may be implemented on the wireless device (118).
摘要翻译：编码器（300）基于每个子集在表示数据中的重要性来选择（702,1302,1304,1306,1308）一个或多个空间或时间相关的变换数据系数子集。编码器（300）和互补解码器（400）可以应用于小波变换编码图像（500）。编码器（300）可以在无线到因特网网关服务器（108）上实现，以便减少通过无线网络（112）发送的编码图像（500）的字节大小，并且减少必须执行的处理量通过无线设备（118）来解码图像或其他数据。解码器（400）和/或编码器（300）可以在无线设备（118）上实现。

5. 发明授权

US06278753B1 Method and apparatus of creating and implementing wavelet filters in a digital system 有权
标题翻译：在数字系统中创建和实现小波滤波器的方法和装置
公开(公告)号：US06278753B1
公开(公告)日：2001-08-21
申请号：US09304313
申请日：1999-05-03
申请人： Jose I. Suarez , Yolanda Prieto , Yolanda M. Pirez
发明人： Jose I. Suarez , Yolanda Prieto , Yolanda M. Pirez
IPC分类号： H04B110
CPC分类号： G06F17/148
摘要： A method for generating a wavelet filter provides improved selectivity with minimal computational intensity in digital data systems (300,400). The process begins by generating an initial wavelet formed of low pass and high pass analysis filter bank (302). The next steps include obtaining an upper triangular matrix which, when multiplied by the initial wavelet, produces a product retaining the symmetry and enhancing the number of zero moment(s) of the initial wavelet (304); and obtaining a lower triangular matrix which, when multiplied by the initial wavelet, produces a product retaining the symmetry and the zero moment of the initial wavelet (306). By multiplying the upper and lower triangular matrices with the initial wavelet, an updated wavelet filter with improved selectivity is produced (308, 318).
摘要翻译：一种生成小波滤波器的方法在数字数据系统中提供了最小的计算强度的选择性（300,400）。该过程开始于产生由低通和高通分析滤波器组（302）形成的初始小波。接下来的步骤包括获得上三角矩阵，当与初始小波相乘时，产生保持对称性并增强初始小波（304）的零时刻数的乘积的上三角矩阵; 并且获得下三角矩阵，当与初始小波相乘时，产生保持初始小波的对称性和零时刻的乘积（306）。通过将上和下三角矩阵与初始小波相乘，产生具有改进选择性的更新小波滤波器（308,318）。

6. 发明授权

US5092783A RF interconnect 失效
标题翻译：射频互连
公开(公告)号：US5092783A
公开(公告)日：1992-03-03
申请号：US700829
申请日：1991-05-16
申请人： Jose I. Suarez , William J. Martin , James V. Lauder , Harold M. Cook
发明人： Jose I. Suarez , William J. Martin , James V. Lauder , Harold M. Cook
IPC分类号： H01R4/48
CPC分类号： H01R4/48 , H01R12/52 , H01R12/57
摘要： An RF contact (2) provides multiple RF paths (51-53) with minimal RF path lengths between a first (8) and second (36) interconnecting surfaces. A stationary member (6) is soldered on the first surface (8). A main spring member (22) is resiliently (26) connected to the stationary member (6) on a springing end (27) to provide contact travel (38) which ensures wiping action with the second surface (36). A secondary spring member (28) having at least two wiping portions (42 and 46) is resiliently (29) connected to the displacement member on its other end (38) to engage the stationary member (6) and the main spring member (22) along the at least two wiping portions (42 and 46) when the main spring member (22) is resiliently biased against the secondary spring member (28) and the stationary member (6).
摘要翻译： RF接触器（2）在第一（8）和第二（36）互连表面之间提供具有最小RF路径长度的多个RF路径（51-53）。固定构件（6）焊接在第一表面（8）上。主弹簧构件（22）在弹簧端（27）上弹性地（26）连接到固定构件（6），以提供接触行进（38），其确保与第二表面（36）的擦拭作用。具有至少两个擦拭部分（42和46）的第二弹簧构件（28）弹性地连接到位于其另一端（38）上的位移构件（29）上，以与静止构件（6）和主弹簧构件）当主弹簧构件（22）弹性偏压抵靠第二弹簧构件（28）和固定构件（6）时沿着至少两个擦拭部分（42和46）。

7. 发明授权

US5081427A Fast lock time phase locked loop 失效
标题翻译：快速锁定锁相环
公开(公告)号：US5081427A
公开(公告)日：1992-01-14
申请号：US619648
申请日：1990-11-29
申请人： Jose I. Suarez
发明人： Jose I. Suarez
IPC分类号： H03L7/081 , H03L7/089
CPC分类号： H03L7/0893 , H03L7/081
摘要： A fast locking phase locked loop includes a first integrator that provides a signal representing a function of the mathematical or ideal integral of the phase difference between an input signal and a feedback signal. A voltage controlled oscillator is coupled to the first integrator and provides a signal to a phase shifter that provides the phase shifted signal that represents a function of the phase of the signal from the VCO, and a function of the integral of the phase difference between the integrated signals.
摘要翻译：快速锁定锁相环包括第一积分器，其提供表示输入信号和反馈信号之间的相位差的数学或理想积分的函数的信号。压控振荡器耦合到第一积分器，并向提供相位移信号的移相器提供信号，该相移信号表示来自VCO的信号的相位的函数，以及相位差的函数综合信号。

8. 发明授权

US06757326B1 Method and apparatus for implementing wavelet filters in a digital system 失效
公开(公告)号：US06757326B1
公开(公告)日：2004-06-29
申请号：US09221434
申请日：1998-12-28
申请人： Yolanda Prieto , Jose I. Suarez , Yolanda M. Pirez
发明人： Yolanda Prieto , Jose I. Suarez , Yolanda M. Pirez
IPC分类号： H03H730
CPC分类号： H03H17/0266 , G06F17/148 , H03H2222/06
摘要： A digital data system (100) provides 1-D, 2-D and 3-D capability and multi-band channel capability. Improved filter banks are created by generating a filter bank having an analysis portion and synthesis portion and obtaining wavelet coefficients (302) for each portion. The wavelet coefficients are expressed in a format capable of canonical signed digit (CSD) representation, such as integers (302). The canonical signed digit (CSD) representation is controlled by a value, N, selected to control resolution of the CSD coding. Optimized CSD-coded wavelet coefficients are used as filters for data signals (318).

9. 发明授权

US4737969A Spectrally efficient digital modulation method and apparatus 失效
标题翻译：高效的数字调制方法和装置
公开(公告)号：US4737969A
公开(公告)日：1988-04-12
申请号：US7847
申请日：1987-01-28
申请人： Francis R. Steel , Clifford D. Leitch , Jose I. Suarez
发明人： Francis R. Steel , Clifford D. Leitch , Jose I. Suarez
IPC分类号： H04L23/02 , H04L25/03 , H04L27/20 , H04L27/34 , H04L27/36 , H04L27/38
CPC分类号： H04L27/3494 , H04L23/02 , H04L25/03859 , H04L27/363 , H04L27/3854
摘要： A method and apparatus are provided for generating a uniquely shaped prototype digital pulse which is transmitted with minimal frequency spectrum consumption and yet a relatively high bit rate. Such uniquely shaped digital pulse is stored in a memory included in a transmitter until transmission is desired, at which time a positive of the pulse is transmitted to correspond to a first logic level or the negative of the pulse is transmitted to correspond to a second logic level.
摘要翻译：提供了一种方法和装置，用于产生唯一成形的原型数字脉冲，其以最小频谱消耗并且具有相对较高的比特率被传输。这种唯一形状的数字脉冲被存储在包括在发射机中的存储器中，直到需要传输，此时发送脉冲的正值以对应于第一逻辑电平，或者发送脉冲的负值以对应于第二逻辑水平。

10. 发明授权

US4494090A Frequency modulation system for a frequency synthesizer 失效
标题翻译：频率合成器的频率调制系统
公开(公告)号：US4494090A
公开(公告)日：1985-01-15
申请号：US614692
申请日：1984-05-25
申请人： Marc H. Popek , Jose I. Suarez
发明人： Marc H. Popek , Jose I. Suarez
IPC分类号： H03C3/09 , H03C3/22 , H03D13/00 , H03J5/02 , H03K23/66 , H03L7/08 , H03L7/193 , H03L7/199 , H04B1/40 , H03C3/08
CPC分类号： H03C3/0966 , H03C3/0933 , H03C3/0941 , H03C3/0958 , H03C3/227 , H03D13/005 , H03J5/0281 , H03K23/66 , H03K23/667 , H03L7/0802 , H03L7/193 , H03L7/199 , H04B1/405
摘要： A voltage controlled oscillator includes a main varactor diode coupled to a frequency resonating circuit to produce an output frequency in response to a control voltage. A secondary varactor diode of an appreciably lower voltage to frequency sensitivity ratio is coupled to the main varactor diode. A modulation input circuit is coupled to the secondary varactor diode to enable modulation of the resonating output frequency. A linearizing circuit is coupled to the secondary varactor diode and tracks the main varactor diode capacitance to continuously adjust the bias voltage of the secondary varactor diode to provide constant carrier modulation deviation.
摘要翻译：压控振荡器包括耦合到频率谐振电路的主变容二极管，以响应于控制电压产生输出频率。具有相当低的电压与频率灵敏度比的次级变容二极管耦合到主变容二极管。调制输入电路耦合到次级变容二极管以使得能够调制谐振输出频率。线性化电路耦合到二次变容二极管，并跟踪主变容二极管电容，以连续调节二次变容二极管的偏置电压，以提供恒定的载波调制偏差。

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