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1. 发明授权

US08595449B2 Memory scheduler for managing maintenance operations in a resistive memory in response to a trigger condition 有权
标题翻译：用于响应于触发条件来管理电阻性存储器中的维护操作的存储器调度器
公开(公告)号：US08595449B2
公开(公告)日：2013-11-26
申请号：US12202581
申请日：2008-09-02
申请人： Michael Kund , Thomas Happ , GillYong Lee , Heinz Hoenigschmid , Rolf Weis , Christoph Ludwig
发明人： Michael Kund , Thomas Happ , GillYong Lee , Heinz Hoenigschmid , Rolf Weis , Christoph Ludwig
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G11C13/00 , G11C11/00 , G11C11/34 , G11C16/06 , G11C16/04 , G11C7/04
CPC分类号： G11C7/04 , G11C13/0002 , G11C13/0033 , G11C16/3431
摘要： An integrated circuit includes: a resistive memory having an array of resistive memory cells; a memory controller that controls operation of the resistive memory in accordance with external commands from an external device; and a memory scheduler coupled to the resistive memory and to the memory controller. The memory scheduler schedules internal maintenance operations within the resistive memory in response to trigger conditions indicated by at least one sensor signal or external command. The operation of the memory scheduler and performance of the internal maintenance operations are transparent to the external device and, optionally, transparent to the memory controller.
摘要翻译：集成电路包括：具有电阻存储器单元阵列的电阻性存储器; 存储器控制器，其根据来自外部设备的外部命令来控制所述电阻性存储器的操作; 以及耦合到电阻存储器和存储器控制器的存储器调度器。存储器调度器响应于由至少一个传感器信号或外部命令指示的触发条件来调度电阻性存储器内的内部维护操作。内存调度器的操作和内部维护操作的性能对于外部设备是透明的，并且可选地对存储器控制器是透明的。

2. 发明申请

US20100058018A1 Memory Scheduler for Managing Internal Memory Operations 有权
标题翻译：用于管理内部存储器操作的内存调度器
公开(公告)号：US20100058018A1
公开(公告)日：2010-03-04
申请号：US12202581
申请日：2008-09-02
申请人： Michael Kund , Thomas Happ , GillYong Lee , Heinz Hoenigschmid , Rolf Weis , Christoph Ludwig
发明人： Michael Kund , Thomas Happ , GillYong Lee , Heinz Hoenigschmid , Rolf Weis , Christoph Ludwig
IPC分类号： G06F12/00
CPC分类号： G11C7/04 , G11C13/0002 , G11C13/0033 , G11C16/3431
摘要： An integrated circuit includes: a resistive memory having an array of resistive memory cells; a memory controller that controls operation of the resistive memory in accordance with external commands from an external device; and a memory scheduler coupled to the resistive memory and to the memory controller. The memory scheduler schedules internal maintenance operations within the resistive memory in response to trigger conditions indicated by at least one sensor signal or external command. The operation of the memory scheduler and performance of the internal maintenance operations are transparent to the external device and, optionally, transparent to the memory controller.
摘要翻译：集成电路包括：具有电阻存储器单元阵列的电阻性存储器; 存储器控制器，其根据来自外部设备的外部命令来控制所述电阻性存储器的操作; 以及耦合到电阻存储器和存储器控制器的存储器调度器。存储器调度器响应于由至少一个传感器信号或外部命令指示的触发条件来调度电阻性存储器内的内部维护操作。存储器调度器的操作和内部维护操作的性能对于外部设备是透明的，并且可选地对存储器控制器是透明的。

3. 发明授权

US07829879B2 Integrated circuit including U-shaped access device 有权
标题翻译：集成电路包括U型接入装置
公开(公告)号：US07829879B2
公开(公告)日：2010-11-09
申请号：US12033519
申请日：2008-02-19
申请人： Rolf Weis , Thomas Happ
发明人： Rolf Weis , Thomas Happ
IPC分类号： H01L29/02
CPC分类号： H01L27/2409 , H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148
摘要： An integrated circuit includes a first contact, a second contact, and a U-shaped access device coupled to the first contact and the second contact. The integrated circuit includes self-aligned dielectric material isolating the first contact from the second contact.
摘要翻译：集成电路包括耦合到第一触点和第二触点的第一触点，第二触点和U形存取装置。集成电路包括将第一接触与第二接触隔离的自对准电介质材料。

4. 发明申请

US20090206315A1 INTEGRATED CIRCUIT INCLUDING U-SHAPED ACCESS DEVICE 有权
标题翻译：集成电路，包括U形形式的访问设备
公开(公告)号：US20090206315A1
公开(公告)日：2009-08-20
申请号：US12033519
申请日：2008-02-19
申请人： Rolf Weis , Thomas Happ
发明人： Rolf Weis , Thomas Happ
IPC分类号： H01L45/00
CPC分类号： H01L27/2409 , H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148
摘要： An integrated circuit includes a first contact, a second contact, and a U-shaped access device coupled to the first contact and the second contact. The integrated circuit includes self-aligned dielectric material isolating the first contact from the second contact.
摘要翻译：集成电路包括耦合到第一触点和第二触点的第一触点，第二触点和U形存取装置。集成电路包括将第一接触与第二接触隔离的自对准电介质材料。

5. 发明申请

US20090206316A1 INTEGRATED CIRCUIT INCLUDING U-SHAPED ACCESS DEVICE 有权
标题翻译：集成电路，包括U形形式的访问设备
公开(公告)号：US20090206316A1
公开(公告)日：2009-08-20
申请号：US12033533
申请日：2008-02-19
申请人： Rolf Weis , Thomas Happ
发明人： Rolf Weis , Thomas Happ
IPC分类号： H01L45/00
CPC分类号： H01L27/24
摘要： An integrated circuit includes a U-shaped access device and a first line coupled to a first side of the access device. The integrated circuit includes a contact coupled to a second side of the access device and self-aligned dielectric material isolating the first line from the contact.
摘要翻译：集成电路包括U形接入设备和耦合到接入设备的第一侧的第一线路。集成电路包括耦合到存取装置的第二侧的触点和将第一线与触点隔离的自对准电介质材料。

6. 发明授权

US07994536B2 Integrated circuit including U-shaped access device 有权
标题翻译：集成电路包括U型接入装置
公开(公告)号：US07994536B2
公开(公告)日：2011-08-09
申请号：US12033533
申请日：2008-02-19
申请人： Rolf Weis , Thomas Happ
发明人： Rolf Weis , Thomas Happ
IPC分类号： H01L29/00 , H01L21/00 , G11C19/00
CPC分类号： H01L27/24
摘要： An integrated circuit includes a U-shaped access device and a first line coupled to a first side of the access device. The integrated circuit includes a contact coupled to a second side of the access device and self-aligned dielectric material isolating the first line from the contact.
摘要翻译：集成电路包括U形接入设备和耦合到接入设备的第一侧的第一线路。集成电路包括耦合到存取装置的第二侧的触点和将第一线与触点隔离的自对准电介质材料。

7. 发明授权

US09035690B2 Circuit arrangement with a first semiconductor device and with a plurality of second semiconductor devices 有权
标题翻译：具有第一半导体器件和多个第二半导体器件的电路布置
公开(公告)号：US09035690B2
公开(公告)日：2015-05-19
申请号：US13599946
申请日：2012-08-30
申请人： Rolf Weis
发明人： Rolf Weis
IPC分类号： H03K17/567 , H03K17/10 , H03K17/687
CPC分类号： H03K5/08 , H03K17/102 , H03K17/567 , H03K17/687 , H03K2017/6875
摘要： A circuit arrangement includes a first semiconductor device having a load path and a number of second semiconductor devices. Each second semiconductor device has a control terminal and a load path between a first load terminal and a second load terminal. The second semiconductor devices have their load paths connected in series and connected in series with the load path of the first semiconductor device. Each of the second semiconductor devices has a load terminal of one of the first semiconductor device and of one of the second semiconductor devices associated thereto and a voltage limiting element coupled between the control terminal of one of the second semiconductor devices and the load terminal associated with that one of the second semiconductor devices.
摘要翻译：电路装置包括具有负载路径和多个第二半导体器件的第一半导体器件。每个第二半导体器件具有在第一负载端子和第二负载端子之间的控制端子和负载路径。第二半导体器件的负载路径串联连接并与第一半导体器件的负载路径串联连接。每个第二半导体器件具有第一半导体器件中的一个和与其相关联的第二半导体器件中的一个的负载端子，以及耦合在第二半导体器件中的一个的控制端子与与之相关联的负载端子之间的电压限制元件那个第二个半导体器件之一。

8. 发明授权

US08971080B2 Circuit arrangement with a rectifier circuit 有权
标题翻译：电路布置与整流电路
公开(公告)号：US08971080B2
公开(公告)日：2015-03-03
申请号：US13546510
申请日：2012-07-11
申请人： Rolf Weis , Gerald Deboy
发明人： Rolf Weis , Gerald Deboy
IPC分类号： H02M7/217
CPC分类号： H02M3/33592 , H02M3/1588 , H02M7/217 , Y02B70/1466 , Y02B70/1475
摘要： A circuit arrangement includes a rectifier circuit having a first and a second load terminal, a first semiconductor device having a load path and a control terminal and a plurality of n, with n>1, second semiconductor devices, each having a load path between a first load terminal and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. The series circuit with the first semiconductor device and the second semiconductor devices are connected between the load terminals of the rectifier circuit. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices. One of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device.
摘要翻译：一种电路装置包括具有第一和第二负载端子的整流电路，具有负载路径的第一半导体器件和具有n≥1的多个n，第二半导体器件具有负载路径第一负载端子和第二负载端子和控制端子。第二半导体器件的负载路径串联连接并与第一半导体器件的负载路径串联连接。具有第一半导体器件和第二半导体器件的串联电路连接在整流器电路的负载端子之间。每个第二半导体器件的控制端子连接到其它第二半导体器件之一的负载端子。第二半导体器件中的一个具有连接到第一半导体器件的负载端子之一的控制端子。

9. 发明申请

US20140016386A1 Circuit Arrangement with a Rectifier Circuit 有权
标题翻译：整流电路的电路布置
公开(公告)号：US20140016386A1
公开(公告)日：2014-01-16
申请号：US13546510
申请日：2012-07-11
申请人： Rolf Weis , Gerald Deboy
发明人： Rolf Weis , Gerald Deboy
IPC分类号： H02M7/00 , H02M7/217 , H02M7/06
CPC分类号： H02M3/33592 , H02M3/1588 , H02M7/217 , Y02B70/1466 , Y02B70/1475
摘要： A circuit arrangement includes a rectifier circuit having a first and a second load terminal, a first semiconductor device having a load path and a control terminal and a plurality of n, with n>1, second semiconductor devices, each having a load path between a first load terminal and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. The series circuit with the first semiconductor device and the second semiconductor devices are connected between the load terminals of the rectifier circuit. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices. One of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device.
摘要翻译：一种电路装置包括具有第一和第二负载端子的整流电路，具有负载路径的第一半导体器件和具有n≥1的多个n，第二半导体器件具有负载路径第一负载端子和第二负载端子和控制端子。第二半导体器件的负载路径串联连接并与第一半导体器件的负载路径串联连接。具有第一半导体器件和第二半导体器件的串联电路连接在整流器电路的负载端子之间。每个第二半导体器件的控制端子连接到其它第二半导体器件之一的负载端子。第二半导体器件中的一个具有连接到第一半导体器件的负载端子之一的控制端子。

10. 发明授权

US08569842B2 Semiconductor device arrangement with a first semiconductor device and with a plurality of second semiconductor devices 有权
标题翻译：具有第一半导体器件和多个第二半导体器件的半导体器件布置
公开(公告)号：US08569842B2
公开(公告)日：2013-10-29
申请号：US13275151
申请日：2011-10-17
申请人： Rolf Weis , Franz Hirler , Matthias Stecher , Armin Willmeroth , Gerald Deboy , Martin Feldtkeller
发明人： Rolf Weis , Franz Hirler , Matthias Stecher , Armin Willmeroth , Gerald Deboy , Martin Feldtkeller
IPC分类号： H01L27/06 , H01L27/088 , H01L27/098 , H01L29/161 , H01L29/20 , H01L29/778 , H01L29/788
CPC分类号： H01L27/0207 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L27/0623 , H01L27/0629 , H01L27/0727 , H01L27/088 , H01L27/0883 , H01L27/0886 , H01L27/098 , H01L29/0653 , H01L29/0692 , H01L29/0696 , H01L29/4236 , H01L29/4238 , H01L29/78 , H01L29/7817 , H01L29/7824 , H01L29/7825 , H01L29/7835 , H01L29/7838 , H03K17/06
摘要： A semiconductor device arrangement includes a first semiconductor device having a load path, and a number of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor. Each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors. One of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.
摘要翻译：半导体器件布置包括具有负载路径的第一半导体器件和多个第二晶体管，每个具有第一和第二负载端子与控制端子之间的负载路径。第二晶体管的负载路径串联连接并与第一晶体管的负载路径串联连接。每个第二晶体管的控制端连接到其它第二晶体管的负载端子。第二晶体管中的一个具有其控制端子连接到第一半导体器件的负载端子之一。

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