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1. 发明授权

US5511173A Programmable logic array and data processing unit using the same 失效
标题翻译：可编程逻辑阵列和数据处理单元使用相同
公开(公告)号：US5511173A
公开(公告)日：1996-04-23
申请号：US177794
申请日：1994-01-05
申请人： Shinichi Yamaura , Takashi Yasui , Keiichi Yoshioka
发明人： Shinichi Yamaura , Takashi Yasui , Keiichi Yoshioka
IPC分类号： G06F9/32 , G06F9/22 , H03K19/177 , G06F9/30
CPC分类号： H03K19/1772 , G06F9/223
摘要： A programmable logic array includes a plurality of AND planes. Each AND plane executes an AND logic operation and has input terminals and output terminals. The programmable logic array also includes a single OR plane provided in common for the plurality of AND planes. The single OR plane executes an OR logic operation and has input terminals coupled to the output terminals of the plurality of AND planes and output terminals. A data processing unit using the above programmable logic array is also provided.
摘要翻译：可编程逻辑阵列包括多个AND平面。每个AND平面执行AND逻辑运算，并具有输入端和输出端。可编程逻辑阵列还包括为多个AND平面共同提供的单个OR平面。单OR平面执行或逻辑运算，并且具有耦合到多个AND平面和输出端的输出端的输入端。还提供了使用上述可编程逻辑阵列的数据处理单元。

2. 发明授权

US5596761A Central processing unit with internal register initializing means 失效
标题翻译：具有内部寄存器初始化手段的中央处理单元
公开(公告)号：US5596761A
公开(公告)日：1997-01-21
申请号：US101399
申请日：1993-08-02
申请人： Keiichi Yoshioka , Takashi Yasui , Shinichi Yamaura
发明人： Keiichi Yoshioka , Takashi Yasui , Shinichi Yamaura
IPC分类号： G06F9/32 , G06F9/38 , G06F9/00
CPC分类号： G06F9/3861 , G06F9/32
摘要： A central processing unit (CPU) carries out selected reset interruption processing by using a vector address preset in accordance with an interruption source to generate an address to a data table whose contents are used to initialize selected registers. In this manner, the CPU can be reset without having first stored the processing state of the CPU in response to a reset interrupt request, without the need for extensive dedicated reset hardware, and with the ability to select desired reset values that can differ as between different interrupts and can be changed from time to time.
摘要翻译：中央处理单元（CPU）通过使用根据中断源预设的向量地址来执行所选择的复位中断处理，以将内容生成到其内容用于初始化所选择的寄存器的数据表。以这种方式，CPU可以被复位而不需要首先存储CPU的处理状态，而不需要广泛的专用复位硬件，并且具有选择期望的复位值的能力，所述复位值可以不同不同的中断，可以不时更改。

3. 发明授权

US5161229A Central processing unit 失效
标题翻译：中央处理器
公开(公告)号：US5161229A
公开(公告)日：1992-11-03
申请号：US533383
申请日：1990-06-05
申请人： Takashi Yasui , Keiichi Yoshioka , Shinichi Yamaura
发明人： Takashi Yasui , Keiichi Yoshioka , Shinichi Yamaura
IPC分类号： G06F9/48 , G06F9/38
CPC分类号： G06F9/3861
摘要： A central processing unit has a plurality of control sections; a device for selectively operating and unoperating the control sections by an external interrruption signal; and a device for processing an interruption sequence with respect to the interruption signal by the operations of the control sections in a state in which the control sections are operated. The control processing unit may be constructed such that the control sections are composed of two control sections and one of the two control sections processes a normal instruction sequence and is unoperated by the interruption signal, and the other of the two control sections is operated at the times of the normal instruction and interruption and processes the interruption sequence in addition to the normal instruction.
摘要翻译：中央处理单元具有多个控制部分; 用于通过外部中断信号选择性地操作和不操作所述控制部分的装置; 以及用于在控制部分被操作的状态下通过控制部分的操作来处理关于中断信号的中断序列的装置。控制处理单元可以被构造成使得控制部分由两个控制部分组成，并且两个控制部分中的一个控制部分处理正常指令序列并且由中断信号进行未操作，并且两个控制部分中的另一个在正常指令的次数和中断，并处理除了正常指令之外的中断序列。

4. 发明授权

US5301338A System including central processing unit 失效
标题翻译：系统包括中央处理单元
公开(公告)号：US5301338A
公开(公告)日：1994-04-05
申请号：US568827
申请日：1990-08-17
申请人： Shinichi Yamaura , Takashi Yasui , Keiichi Yoshioka
发明人： Shinichi Yamaura , Takashi Yasui , Keiichi Yoshioka
IPC分类号： G06F7/50 , G06F7/00 , G06F7/507 , G06F9/302 , G06F9/305 , G06F9/308 , G06F12/00 , G06F12/04
CPC分类号： G06F9/30014 , G06F9/30018
摘要： A central processing unit includes a programmable logic array, a timing control unit, a predecoder, a data input/output part, and a processing part. The processing part carries out a predetermined operation on m-bit low-order data from among data which is composed of n bits and which is read out from a memory and m-bit high-order data from among the data composed of n bits, and outputs a carry signal when the predetermined operation on the m-bit low-order data results in a carry. When the operation code is a read modify write instruction and when the processing part outputs the carry signal, the programmable logic array controls the input/output part so that only the result of the predetermined operation on the m-bit low-order data is written into the memory.
摘要翻译：中央处理单元包括可编程逻辑阵列，定时控制单元，预解码器，数据输入/输出部分和处理部分。处理部分从由n位组成的数据和从n位组成的数据中从存储器读出的m位低位数据中的m位低位数据执行预定的操作，并且当对m位低位数据的预定操作导致进位时，输出进位信号。当操作代码是读修改写指令时，当处理部分输出进位信号时，可编程逻辑阵列控制输入/输出部分，使得仅对m位低位数据进行预定操作的结果被写入进入记忆。

5. 发明授权

US5696957A Integrated circuit comprising a central processing unit for executing a plurality of programs 失效
标题翻译：集成电路，包括用于执行多个节目的中央处理单元
公开(公告)号：US5696957A
公开(公告)日：1997-12-09
申请号：US593482
申请日：1996-01-29
申请人： Shinichi Yamaura , Kazuhiko Hara , Keiichi Yoshioka , Takashi Yasui
发明人： Shinichi Yamaura , Kazuhiko Hara , Keiichi Yoshioka , Takashi Yasui
IPC分类号： G06F9/30 , G06F9/46
CPC分类号： G06F9/3012 , G06F9/462
摘要： An integrated circuit has a central processing unit for executing programs. The integrated circuit includes a register set, provided in the central processing unit, for storing crate required for executing a program in the central processing unit; and a register-file RAM, coupled to the central processing unit, for storing at least the same data as that stored in the register set in the central processing unit, wherein data stored in the register-file RAM can be supplied to the register set in the central processing unit.
摘要翻译：集成电路具有用于执行程序的中央处理单元。集成电路包括设置在中央处理单元中的寄存器组，用于存储在中央处理单元中执行程序所需的箱; 以及耦合到中央处理单元的寄存器文件RAM，用于存储至少与存储在中央处理单元中的寄存器中的数据相同的数据，其中存储在寄存器文件RAM中的数据可以被提供给寄存器组在中央处理单位。

6. 发明授权

US5606709A Register group circuit for data processing system 失效
标题翻译：数据处理系统寄存器组电路
公开(公告)号：US5606709A
公开(公告)日：1997-02-25
申请号：US344365
申请日：1994-11-23
申请人： Keiichi Yoshioka , Shinichi Yamaura , Kazuhiko Hara , Takao Katayama
发明人： Keiichi Yoshioka , Shinichi Yamaura , Kazuhiko Hara , Takao Katayama
IPC分类号： G06F7/00 , G06F13/40 , G06F13/20
CPC分类号： G06F13/4027
摘要： A general-purpose register group circuit provided in a data processing system includes a plurality of register groups connected to a first bus and a second bus, data being written into the plurality of register groups via the first bus according to a first control signal and being read therefrom via the second bus according to a second control signal. An output register group is connected to the plurality of register groups via the first and second buses. The data read from the plurality of register groups is written into the output register group according to a third control signal, and data read from the output register group is sent to an inner bus of the data processing system according to a fourth control signal. Each of the plurality of register groups includes a plurality of unit registers, each of which registers includes a first part for setting the second bus to either a high-impedance state or a reference level according to data latched therein and the second control signal. The output register group includes a second part for driving the inner bus according to a state of the second bus.
摘要翻译：提供在数据处理系统中的通用寄存器组电路包括连接到第一总线和第二总线的多个寄存器组，经由第一总线根据第一控制信号被写入多个寄存器组的数据，并且根据第二控制信号经由第二总线从其读取。输出寄存器组经由第一和第二总线连接到多个寄存器组。根据第三控制信号将从多个寄存器组读取的数据写入输出寄存器组，并且根据第四控制信号将从输出寄存器组读取的数据发送到数据处理系统的内部总线。多个寄存器组中的每一个包括多个单元寄存器，其中每个寄存器包括用于根据锁存在其中的数据和第二控制信号将第二总线设置为高阻抗状态或参考电平的第一部分。输出寄存器组包括用于根据第二总线的状态驱动内部总线的第二部分。

7. 发明授权

US5938758A Microprocessor having function of prefetching instruction 失效
标题翻译：具有预取指令功能的微处理器
公开(公告)号：US5938758A
公开(公告)日：1999-08-17
申请号：US933579
申请日：1997-09-19
申请人： Takao Katayama , Shinichi Yamaura , Keiichi Yoshioka , Kazuhiko Hara
发明人： Takao Katayama , Shinichi Yamaura , Keiichi Yoshioka , Kazuhiko Hara
IPC分类号： G06F9/38 , G06F9/32 , G06F9/46 , G06F9/48 , G06F13/32 , G06F13/00
CPC分类号： G06F9/32 , G06F9/3802
摘要： A microprocessor having an instruction prefetch function includes a storage circuit in which an instruction externally supplied to the microprocessor via an external interface is stored, a first latch circuit which latches a write address value of the storage circuit in response to an interrupt signal externally supplied to the microprocessor, and an internal interrupt signal outputting circuit which compares a read address value of the storage circuit indicating the instruction stored in the storage circuit with the write address value supplied from the first latch circuit and which generates the internal interrupt signal only when the read address value and the write address value coincide with each other. The microprocessor processes an interrupt process in response to the internal interrupt signal.
摘要翻译：具有指令预取功能的微处理器包括存储电路，其中存储经由外部接口向外部提供给微处理器的指令，第一锁存电路，响应于外部提供给中断信号而锁存存储电路的写入地址值微处理器和内部中断信号输出电路，其将指示存储在存储电路中的指令的存储电路的读取地址值与从第一锁存电路提供的写入地址值进行比较，并且仅在读取时产生内部中断信号地址值和写入地址值彼此一致。微处理器响应于内部中断信号处理中断过程。

8. 发明授权

US06266756B1 Central processing unit compatible with bank register CPU 失效
标题翻译：中央处理单元与银行寄存器CPU兼容
公开(公告)号：US06266756B1
公开(公告)日：2001-07-24
申请号：US08682003
申请日：1996-07-16
申请人： Kazuhiko Hara , Shinichi Yamaura , Keiichi Yoshioka , Keiji Nakamura , Takao Katayama
发明人： Kazuhiko Hara , Shinichi Yamaura , Keiichi Yoshioka , Keiji Nakamura , Takao Katayama
IPC分类号： G06F1200
CPC分类号： G06F9/342 , G06F9/30036 , G06F9/30112 , G06F9/30167
摘要： When data that does not fill a bit size (32 bits) of a first register is stored in the first register, 8-bit data is supplied from a second register or a first constant generator to unfilled higher 16 bit positions of the first register, and a second constant generator supplies 8-bit data to fill the remaining bit positions in the first register.
摘要翻译：当未填充第一寄存器的位大小（32位）的数据被存储在第一寄存器中时，8位数据从第二寄存器或第一常数发生器提供给第一寄存器的未填充的较高16位位置，并且第二常数发生器提供8位数据以填充第一寄存器中的剩余位位置。

9. 发明授权

US5630158A Central processing unit including inhibited branch area 失效
标题翻译：中央处理单元包括禁止分支区域
公开(公告)号：US5630158A
公开(公告)日：1997-05-13
申请号：US361936
申请日：1994-12-22
申请人： Kazuhiko Hara , Shinichi Yamaura , Keiichi Yoshioka , Takao Katayama
发明人： Kazuhiko Hara , Shinichi Yamaura , Keiichi Yoshioka , Takao Katayama
IPC分类号： G06F9/26 , G06F9/32 , G06F9/355 , G06F9/38 , G06F9/00
CPC分类号： G06F9/342 , G06F9/321 , G06F9/322 , G06F9/3861
摘要： A central processing unit includes an instruction register storing instruction codes, a timing control unit controlling timings of steps of execution of an instruction, an execution unit executing an operation on data and temporarily storing data, the execution unit having a program counter and a data bus, a decoder decoding instruction codes read from the instruction register and controlling the instruction register, the timing control unit and the execution unit, and a next enable unit receiving an indication signal indicating proceeding to a next instruction should be performed and controlling outputting of the indication signal to the instruction register and the timing control unit based on first and second signals. The first signal is supplied from the decoder and instructing data on the data bus to be input to the program counter. The second signal is supplied from the execution unit and indicating whether a counter value of the program counter is an odd number or an even number.
摘要翻译：中央处理单元包括存储指令代码的指令寄存器，控制指令执行步骤的定时的定时控制单元，执行对数据的操作和暂时存储数据的执行单元，执行单元具有程序计数器和数据总线应执行从指令寄存器读取的解码器解码指令代码和控制指令寄存器，定时控制单元和执行单元，以及接收指示进行下一条指令的指示信号的下一个使能单元，并且控制该指示的输出基于第一和第二信号向指令寄存器和定时控制单元发送信号。第一个信号从解码器提供，并指示数据总线上的数据输入到程序计数器。第二信号从执行单元提供并指示程序计数器的计数器值是奇数还是偶数。

10. 发明授权

US5594890A Emulation system for emulating CPU core, CPU core with provision for emulation and ASIC having the CPU core 失效
标题翻译：用于仿真CPU核心的仿真系统，具有用于仿真的CPU核心和具有CPU核心的ASIC
公开(公告)号：US5594890A
公开(公告)日：1997-01-14
申请号：US200705
申请日：1994-02-23
申请人： Shinichi Yamaura , Keiichi Yoshioka , Kazuhiko Hara , Takao Katayama
发明人： Shinichi Yamaura , Keiichi Yoshioka , Kazuhiko Hara , Takao Katayama
IPC分类号： G06F11/22 , G06F11/36 , G06F17/00
CPC分类号： G06F11/3652
摘要： An IC is provided with a CPU core selected from a plurality of CPU cores, each of which has a specific function. Each CPU core has a system-bus terminal and a common emulator connecting-exclusive terminal. The IC is also provided with a predetermined function device connected to a system bus of the selected CPU core. An emulation bus connects an emulator to the selected CPU core via the common emulator connecting-exclusive terminal. An emulator performs emulation on the selected CPU core which is connected via the emulation bus when the selected CPU core is in a monitor mode. The number of terminal elements and the function associated with each terminal element of the common emulator connecting-exclusive terminal are identical among the common emulator connecting-exclusive terminals.
摘要翻译： IC具有从多个CPU核心中选择的CPU核心，每个CPU核心具有特定功能。每个CPU内核都有一个系统总线端子和一个通用的仿真器连接专用端子。 IC还具有连接到所选CPU核心的系统总线的预定功能装置。仿真总线通过通用仿真器连接专用端子将仿真器连接到选定的CPU内核。仿真器对选定的CPU内核进行仿真，当所选择的CPU内核处于监视模式时，通过仿真总线连接。公共仿真器连接专用端子的终端元件数量和与每个终端元件相关联的功能在通用仿真器连接专用端子中是相同的。

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