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1. 发明申请

US20170302290A1 ANALOG TO DIGITAL CONVERTER 审中-公开
公开(公告)号：US20170302290A1
公开(公告)日：2017-10-19
申请号：US15637846
申请日：2017-06-29
申请人： Huawei Technologies Co., Ltd.
发明人： Yu Cai , Chunhui Zhang , Jifang He
IPC分类号： H03M1/14 , G11C27/02 , G01N15/14 , H03K17/06
CPC分类号： H03M1/146 , G01N15/1436 , G01N15/1459 , G02F7/00 , G11C27/02 , G11C27/024 , G11C27/026 , H03K17/06
摘要： The present embodiments provide an analog to digital converter, including a beam splitter, M photodetectors, M amplifier modules, and an encoder. Each output end of the beam splitter is corresponding to an input end of a photodetector, an output end of each photodetector is connected to an input end of an amplifier module, and an output end of each amplifier module is connected to an input end of the encoder. The beam splitter splits an inputted analog optical signal into M optical signals, outputs each optical signal to a corresponding photodetector to convert each optical signal into a current signal, inputs each current signal to a corresponding amplifier module to generate an output voltage, and outputs the output voltage to a corresponding input end of the encoder.

2. 发明授权

US07675451B2 Serial-parallel type analog-to-digital converter and analog-to-digital conversion method 失效
标题翻译：串行并行型模数转换器和模数转换方式
公开(公告)号：US07675451B2
公开(公告)日：2010-03-09
申请号：US12232636
申请日：2008-09-22
申请人： Shigemitsu Murayama , Yasuhide Shimizu , Kohei Kudo , Hiroaki Yatsuda
发明人： Shigemitsu Murayama , Yasuhide Shimizu , Kohei Kudo , Hiroaki Yatsuda
IPC分类号： H03M1/36
CPC分类号： H03M1/146 , H03M1/1215 , H03M1/365
摘要： A serial-parallel type analog-to-digital converter includes a reference voltage generator, a higher bit comparing portion and a lower bit comparing portion, and a reference voltage selecting portion, wherein the lower bit comparing portion includes the plurality of comparison stages.
摘要翻译：串行并行型模数转换器包括参考电压发生器，较高位比较部分和低位比较部分以及参考电压选择部分，其中低位比较部分包括多个比较级。

3. 发明申请

US20090195432A1 Systems and Methods for Analog to Digital Conversion 有权
标题翻译：用于模数转换的系统和方法
公开(公告)号：US20090195432A1
公开(公告)日：2009-08-06
申请号：US12024909
申请日：2008-02-01
申请人： James A. Bailey
发明人： James A. Bailey
IPC分类号： H03M1/12
CPC分类号： H03M1/146 , H03M1/365
摘要： Various embodiments of the present invention provide systems and circuits that provide for conversion of analog signals to digital signals. For example, various embodiments of the present invention provide partially clocked, multi-step analog to digital converters. Such analog to digital converters include a clocked fine conversion stage, a clocked coarse conversion stage, and a clock circuit. The fine conversion stage includes a first group of comparators clocked by a first clock and a second group of comparators clocked by a second clock. The first group of comparators is operable to compare an input voltage with a first fine reference voltage range, and the second group of comparators is operable to compare the input voltage with a second fine reference voltage range. The coarse conversion stage includes a group of clocked comparators that are operable to compare the input voltage with a coarse reference voltage range. The clock circuit selectably asserts one of the first clock and the second clock based at least in part on an output of the second conversion stage.
摘要翻译：本发明的各种实施例提供了提供将模拟信号转换成数字信号的系统和电路。例如，本发明的各种实施例提供部分时钟的多步模拟转换器。这种模数转换器包括时钟精细转换级，时钟粗转换级和时钟电路。精细转换级包括由第一时钟计时的第一组比较器和由第二时钟计时的第二组比较器。第一组比较器可操作以将输入电压与第一精细参考电压范围进行比较，并且第二组比较器可操作以将输入电压与第二精细参考电压范围进行比较。粗转换级包括一组时钟比较器，其可操作以将输入电压与粗参考电压范围进行比较。至少部分地基于第二转换级的输出，时钟电路可选地置位第一时钟和第二时钟之一。

4. 发明申请

US20080204294A1 Analog-to-digital converter apparatus, systems, and methods 有权
标题翻译：模数转换器装置，系统和方法
公开(公告)号：US20080204294A1
公开(公告)日：2008-08-28
申请号：US11710798
申请日：2007-02-26
申请人： Hai Yan
发明人： Hai Yan
IPC分类号： H03M1/12
CPC分类号： H03M1/124 , H03M1/146 , H03M1/361
摘要： Various embodiments disclose apparatus, systems, and methods operating with a first circuit branch with transistors coupled in series between first and second supply nodes, and a second circuit branch with second transistors coupled in series between the first and second supply nodes. The second circuit branch may include a resistive unit coupled in series with the second transistors. The first and second circuit branches may receive analog information and to provide digital output information. The digital output information may include output values based on a relationship between a voltage across the first resistive unit and a voltage difference between first and second components of the analog input information. Other embodiments disclose additional apparatus, systems, and methods.
摘要翻译：各种实施例公开了利用在第一和第二供应节点之间串联耦合的晶体管的第一电路支路操作的装置，系统和方法，以及具有串联连接在第一和第二供应节点之间的第二晶体管的第二电路支路。第二电路支路可以包括与第二晶体管串联耦合的电阻单元。第一和第二电路分支可以接收模拟信息并提供数字输出信息。数字输出信息可以包括基于第一电阻单元两端的电压与模拟输入信息的第一和第二分量之间的电压差之间的关系的输出值。其他实施例公开了附加的装置，系统和方法。

5. 发明授权

US07397410B2 Input tracking high-level multibit quantizer for delta-sigma ADC 有权
标题翻译：用于Δ-ΣADC的输入跟踪高级多位量化器
公开(公告)号：US07397410B2
公开(公告)日：2008-07-08
申请号：US11711324
申请日：2007-02-27
申请人： YuQing Yang
发明人： YuQing Yang
IPC分类号： H03M1/12
CPC分类号： H03M1/146 , H03M1/361 , H03M1/365 , H03M3/424 , H03M3/452
摘要： A quantization circuit includes a plurality of resistors, a plurality of tap points, and a plurality of coarse comparators. Each coarse comparator has a first input coupled to an input voltage and a second input coupled to a corresponding coarse tap point voltage. Each coarse comparator operates during a first phase to produce a “1” only if the input voltage exceeds the corresponding coarse tap point voltage. A plurality of fine comparators each have a first input coupled to the input voltage, and each fine comparator operates during a second phase to produce a fine output level indicative of whether the input voltage exceeds a corresponding tap point voltage of a group of tap points located immediately below the tap point connected to the highest coarse comparator producing a “1”.
摘要翻译：量化电路包括多个电阻器，多个抽头点和多个粗略比较器。每个粗略比较器具有耦合到输入电压的第一输入和耦合到对应的粗抽头点电压的第二输入。每个粗略比较器在第一阶段运行，只有在输入电压超过相应的粗分接点电压时才产生“1”。多个精细比较器各自具有耦合到输入电压的第一输入，并且每个精细比较器在第二阶段期间操作以产生指示输入电压是否超过位于一组抽头点的对应分接点电压的精细输出电平紧接在与最高粗略比较器连接的分接点下方产生“1”。

6. 发明申请

US20080055145A1 Input tracking high-level multibit quantizer for delta-sigma ADC 有权
公开(公告)号：US20080055145A1
公开(公告)日：2008-03-06
申请号：US11711324
申请日：2007-02-27
申请人： YuQing Yang
发明人： YuQing Yang
IPC分类号： H03M1/12
CPC分类号： H03M1/146 , H03M1/361 , H03M1/365 , H03M3/424 , H03M3/452
摘要： A quantization circuit includes a plurality of resistors, a plurality of tap points, and a plurality of coarse comparators. Each coarse comparator has a first input coupled to an input voltage and a second input coupled to a corresponding coarse tap point voltage. Each coarse comparator operates during a first phase to produce a “1” only if the input voltage exceeds the corresponding coarse tap point voltage. A plurality of fine comparators each have a first input coupled to the input voltage, and each fine comparator operates during a second phase to produce a fine output level indicative of whether the input voltage exceeds a corresponding tap point voltage of a group of tap points located immediately below the tap point connected to the highest coarse comparator producing a “1”.

7. 发明授权

US07324038B2 Subranging analog to digital converter with multi-phase clock timing 有权
标题翻译：使用多相时钟定时将模数转换器分段
公开(公告)号：US07324038B2
公开(公告)日：2008-01-29
申请号：US10625702
申请日：2003-07-24
申请人： Franciscus Maria Leonardus van der Goes , Jan Mulder , Christopher Michael Ward , Jan Roelof Westra , Ruby van de Plassche , Marcel Lugthart
发明人： Franciscus Maria Leonardus van der Goes , Jan Mulder , Christopher Michael Ward , Jan Roelof Westra , Ruby van de Plassche , Marcel Lugthart
IPC分类号： H03M1/12
CPC分类号： H03M1/146 , H03K17/04106 , H03M1/204 , H03M1/365
摘要： An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.
摘要翻译： N位模数转换器包括参考梯形图，连接到输入电压的跟踪和保持放大器，在其输入处连接到粗略电容器的粗略ADC放大器，并具有由第一时钟控制的粗略ADC复位开关两相时钟的相位，精细ADC放大器在其输入端连接到精细电容器，并具有由两相时钟的第二时钟相位控制的精细ADC复位开关，开关矩阵从第二时钟相位选择电压子范围参考梯形图，用于基于粗ADC放大器的输出的精细ADC放大器使用，并且其中粗电容器在第一时钟相位期间被充电到粗略的参考梯形电压，并且在第二时钟相位期间连接到T / H输出其中精细电容器在第一时钟相位期间连接到电压子范围，并且在第二时钟相位期间连接到T / H输出;以及编码器，其将粗略和精细ADC放大器的输出转换为Nb 它输出。

8. 发明授权

US06888483B2 High speed analog to digital converter 失效
标题翻译：高速模数转换器
公开(公告)号：US06888483B2
公开(公告)日：2005-05-03
申请号：US10893999
申请日：2004-07-20
申请人： Jan Mulder
发明人： Jan Mulder
IPC分类号： H03K17/041 , H03M1/06 , H03M1/08 , H03M1/14 , H03M1/20 , H03M1/36 , H03M1/00
CPC分类号： H03M1/0863 , H03K17/04106 , H03M1/146 , H03M1/204 , H03M1/36 , H03M1/365
摘要： An input stage includes a plurality of arrays of autozero amplifiers arranged in series in each array, wherein each autozero amplifier receives an output of a preceding autozero amplifier, wherein a first autozero amplifier in each array amplifiers receives an input signal and a corresponding reference voltage at its inputs, and wherein at least one of the autozero amplifiers includes a circuit that receives the signal corresponding to the output signal, the circuit substantially passing the signal corresponding to the output signal and the reference voltages to the amplifiers during the clock phase φ2 and substantially rejecting the signal corresponding to the output signal during the clock phase φ1.
摘要翻译：输入级包括在每个阵列中串联布置的多个自动调零放大器阵列，其中每个自动调零放大器接收前一自动调零放大器的输出，其中每个阵列放大器中的第一自动调零放大器接收输入信号和对应的参考电压其输入，并且其中至少一个自动调零放大器包括接收对应于输出信号的信号的电路，所述电路在时钟相位phi 2 <！ - SIPO - >并且在时钟相位phi1 <1>中基本上拒绝对应于输出信号的信号。

9. 发明申请

US20030218557A1 Analog to digital converter with interpolation of reference ladder 失效
标题翻译：具有参考梯形图插补的模数转换器
公开(公告)号：US20030218557A1
公开(公告)日：2003-11-27
申请号：US10158774
申请日：2002-05-31
发明人： Jan Mulder
IPC分类号： H03M001/34
CPC分类号： H03K17/04106 , H03M1/146 , H03M1/204 , H03M1/365 , H04L25/026 , H04L25/0276
摘要： An N-bit analog to digital converter includes a reference ladder connected to an input voltage at one end, and to ground at another end, an array of differential amplifiers whose differential inputs are connected to taps from the reference ladder, wherein each amplifier has a first differential input connected to the same tap as a neighboring amplifier, and a second differential input shifted by one tap from the neighboring amplifier, and an encoder that converts outputs of the array to an N-bit output.
摘要翻译： N位模数转换器包括连接到一端的输入电压并在另一端接地的参考梯形图，其差分放大器的阵列与差分输入端连接到来自参考梯形图的抽头，其中每个放大器具有连接到与相邻放大器相同的抽头的第一差分输入和从相邻放大器偏移一抽头的第二差分输入，以及将阵列的输出转换为N位输出的编码器。

10. 发明申请

US20030218556A1 SUBRANGING ANALOG TO DIGITAL CONVERTER WITH MULTI-PHASE CLOCK TIMING 有权
标题翻译：将数字转换器与多相时钟时序相结合
公开(公告)号：US20030218556A1
公开(公告)日：2003-11-27
申请号：US10359201
申请日：2003-02-06
申请人： Broadcom Corporation
发明人： Franciscus Maria Leonardus van der Goes , Jan Mulder , Christopher Michael Ward , Jan Roelof Westra , Rudy van de Plassche , Marcel Lugthart
IPC分类号： H03M001/12
CPC分类号： H03M1/146 , H03K17/04106 , H03M1/204 , H03M1/365
摘要： An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.
摘要翻译： N位模数转换器包括参考梯形图，连接到输入电压的跟踪和保持放大器，在其输入处连接到粗略电容器的粗略ADC放大器，并具有由第一时钟控制的粗略ADC复位开关两相时钟的相位，精细ADC放大器在其输入端连接到精细电容器，并具有由两相时钟的第二时钟相位控制的精细ADC复位开关，开关矩阵从第二时钟相位选择电压子范围参考梯形图，用于基于粗ADC放大器的输出的精细ADC放大器使用，并且其中粗电容器在第一时钟相位期间被充电到粗略的参考梯形电压，并且在第二时钟相位期间连接到T / H输出其中精细电容器在第一时钟相位期间连接到电压子范围，并且在第二时钟相位期间连接到T / H输出;以及编码器，其将粗略和精细ADC放大器的输出转换为Nb 它输出。

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