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1. 发明申请

US20100259340A1 Active termination and switchable passive termination circuits 有权
标题翻译：主动终端和可切换无源终端电路
公开(公告)号：US20100259340A1
公开(公告)日：2010-10-14
申请号：US12384793
申请日：2009-04-08
申请人： Joseph Aziz , Andrew Chen , Derek Tam , Ark-Chew Wong , Agnes Neves Woo , Marcel Lugthart
发明人： Joseph Aziz , Andrew Chen , Derek Tam , Ark-Chew Wong , Agnes Neves Woo , Marcel Lugthart
IPC分类号： H03H7/38
CPC分类号： H04L25/0298
摘要： According to one exemplary embodiment, an active termination circuit includes at least one active termination branch, where the at least one active termination branch includes at least one transistor for providing an active termination output. The at least one active termination branch further includes an amplifier driving the at least one transistor, where the amplifier has a non-inverting input coupled to the active termination output via a feedback network. The amplifier controls a current flowing through the at least one transistor so as to provide the active termination output. The active termination output can be provided at a drain of the at least one transistor, where a source of the at least one transistor is coupled to ground through a degeneration transistor and a tail current sink.
摘要翻译：根据一个示例性实施例，有源终端电路包括至少一个有源终端分支，其中所述至少一个有源终端分支包括用于提供有源终端输出的至少一个晶体管。所述至少一个有源终端分支还包括驱动所述至少一个晶体管的放大器，其中所述放大器具有经由反馈网络耦合到所述有源终端输出的非反相输入。放大器控制流过至少一个晶体管的电流，以便提供有源终端输出。可以在至少一个晶体管的漏极处提供有源终端输出，其中至少一个晶体管的源极通过退化晶体管和尾部电流吸收器耦合到地。

2. 发明申请

US20060164126A1 High-speed comparator 有权
标题翻译：高速比较器
公开(公告)号：US20060164126A1
公开(公告)日：2006-07-27
申请号：US11038388
申请日：2005-01-21
申请人： Jan Mulder , Franciscus van der Goes , Marcel Lugthart
发明人： Jan Mulder , Franciscus van der Goes , Marcel Lugthart
IPC分类号： G01R19/00
CPC分类号： G01R19/16519 , G01R19/16557 , H03K3/356139 , H03K5/2481 , H03K5/249 , H03M1/0604
摘要： A differential comparator with improved bit-error rate performance operating with a low supply voltage. The differential comparator includes a first pair of transistors receiving a differential input. A second pair of transistors is coupled to the first pair of transistors. A pair of resistive elements is connected between the first pair and second pair of transistors so as to increase bias currents shared by the first and second pairs of transistors. The increased bias currents reduce a time required by the differential comparator to transition from a meta-stable state to a stable state, thereby improving a bit-error rate of the differential comparator. The resistive elements can use linear resistors or transmission gates. Gates of either the first or second pair of transistors can provide an output.
摘要翻译：差分比较器，具有更低的电源电压，具有改进的误码率性能。差分比较器包括接收差分输入的第一对晶体管。第二对晶体管耦合到第一对晶体管。一对电阻元件连接在第一对和第二对晶体管之间，以增加由第一和第二对晶体管共享的偏置电流。增加的偏置电流减少差分比较器从元稳定状态转变到稳定状态所需的时间，从而提高差分比较器的误码率。电阻元件可以使用线性电阻或传输门。第一或第二对晶体管的栅极可以提供输出。

3. 发明授权

US08289046B2 Switchable passive termination circuits 有权
标题翻译：可切换无源终端电路
公开(公告)号：US08289046B2
公开(公告)日：2012-10-16
申请号：US13173706
申请日：2011-06-30
申请人： Joseph Aziz , Andrew Chen , Derek Tam , Ark-Chew Wong , Agnes Neves Woo , Marcel Lugthart
发明人： Joseph Aziz , Andrew Chen , Derek Tam , Ark-Chew Wong , Agnes Neves Woo , Marcel Lugthart
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H04L25/0298
摘要： According to one exemplary embodiment, an active termination circuit includes at least one active termination branch, where the at least one active termination branch includes at least one transistor for providing an active termination output. The at least one active termination branch further includes an amplifier driving the at least one transistor, where the amplifier has a non-inverting input coupled to the active termination output via a feedback network. The amplifier controls a current flowing through the at least one transistor so as to provide the active termination output. The active termination output can be provided at a drain of the at least one transistor, where a source of the at least one transistor is coupled to ground through a degeneration transistor and a tail current sink.
摘要翻译：根据一个示例性实施例，有源终端电路包括至少一个有源终端分支，其中所述至少一个有源终端分支包括用于提供有源终端输出的至少一个晶体管。所述至少一个有源终端分支还包括驱动所述至少一个晶体管的放大器，其中所述放大器具有经由反馈网络耦合到所述有源终端输出的非反相输入。放大器控制流过至少一个晶体管的电流，以便提供有源终端输出。可以在至少一个晶体管的漏极处提供有源终端输出，其中至少一个晶体管的源极通过退化晶体管和尾部电流吸收器耦合到地。

4. 发明授权

US07800449B2 Single-ended-to-differential converter with common-mode voltage control 有权
标题翻译：具有共模电压控制的单端到差分转换器
公开(公告)号：US07800449B2
公开(公告)日：2010-09-21
申请号：US11060395
申请日：2005-02-17
申请人： Jan Mulder , Marcel Lugthart , Chi-Hung Lin
发明人： Jan Mulder , Marcel Lugthart , Chi-Hung Lin
IPC分类号： H03F3/04
CPC分类号： H03H11/32
摘要： Provided is a circuit to perform single-ended to differential conversion while providing common-mode voltage control. The circuit includes a converter to convert a single-ended signal to a differential signal and a stabilizing circuit adapted to receive the differential signal. The stabilizing circuit includes a sensor configured to sense a common-mode voltage level of the differential signal and a comparator having an output port coupled to the converter. The comparator is configured to compare the differential signal common-mode voltage level with a reference signal common-mode voltage level and produce an adjusting signal based upon the comparison. The adjusting signal is applied to the converter via the output port and is operative to adjust a subsequent common-mode voltage level of the differential signal.
摘要翻译：提供了在提供共模电压控制的同时执行单端到差分转换的电路。电路包括将单端信号转换为差分信号的转换器和适于接收差分信号的稳定电路。稳定电路包括被配置为感测差分信号的共模电压电平的传感器和具有耦合到转换器的输出端口的比较器。比较器被配置为将差分信号共模电压电平与参考信号共模电压电平进行比较，并且基于该比较产生调整信号。调整信号经由输出端口被施加到转换器，并且可操作地调整差分信号的后续共模电压电平。

5. 发明授权

US06727756B2 Single-ended-to-differential converter with common-mode voltage control 有权
公开(公告)号：US06727756B2
公开(公告)日：2004-04-27
申请号：US10425736
申请日：2003-04-30
申请人： Jan Mulder , Marcel Lugthart , Chi-Hung Lin
发明人： Jan Mulder , Marcel Lugthart , Chi-Hung Lin
IPC分类号： H03F345
CPC分类号： H03H11/32
摘要： Provided is a circuit to perform single-ended to differential conversion while providing common-mode voltage control. The circuit includes a converter to convert a single-ended signal to a differential signal and a stabilizing circuit adapted to receive the differential signal. The stabilizing circuit includes a sensor configured to sense a common-mode voltage level of the differential signal and a comparator having an output port coupled to the converter. The comparator is configured to compare the differential signal common-mode voltage level with a reference signal common-mode voltage level and produce an adjusting signal based upon the comparison. The adjusting signal is applied to the converter via the output port and is operative to adjust a subsequent common-mode voltage level of the differential signal.

6. 发明授权

US06583747B1 Subranging analog to digital converter with multi-phase clock timing 失效
公开(公告)号：US06583747B1
公开(公告)日：2003-06-24
申请号：US10158773
申请日：2002-05-31
申请人： Franciscus Maria Leonardus van der Goes , Jan Mulder , Christopher Michael Ward , Jan Roelof Westra , Rudy van de Plassche , Marcel Lugthart
发明人： Franciscus Maria Leonardus van der Goes , Jan Mulder , Christopher Michael Ward , Jan Roelof Westra , Rudy van de Plassche , Marcel Lugthart
IPC分类号： H03M112
CPC分类号： H03M1/146 , H03K17/04106 , H03M1/204 , H03M1/365
摘要： An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.

7. 发明授权

US07262639B2 High-speed comparator 有权
标题翻译：高速比较器
公开(公告)号：US07262639B2
公开(公告)日：2007-08-28
申请号：US11038388
申请日：2005-01-21
申请人： Jan Mulder , Franciscus Maria Leonardus van der Goes , Marcel Lugthart
发明人： Jan Mulder , Franciscus Maria Leonardus van der Goes , Marcel Lugthart
IPC分类号： H03K5/22
CPC分类号： G01R19/16519 , G01R19/16557 , H03K3/356139 , H03K5/2481 , H03K5/249 , H03M1/0604
摘要： A differential comparator with improved bit-error rate performance operating with a low supply voltage. The differential comparator includes a first pair of transistors receiving a differential input. A second pair of transistors is coupled to the first pair of transistors. A pair of resistive elements is connected between the first pair and second pair of transistors so as to increase bias currents shared by the first and second pairs of transistors. The increased bias currents reduce a time required by the differential comparator to transition from a meta-stable state to a stable state, thereby improving a bit-error rate of the differential comparator. The resistive elements can use linear resistors or transmission gates. Gates of either the first or second pair of transistors can provide an output.
摘要翻译：差分比较器，具有更低的电源电压，具有改进的误码率性能。差分比较器包括接收差分输入的第一对晶体管。第二对晶体管耦合到第一对晶体管。一对电阻元件连接在第一对和第二对晶体管之间，以增加由第一和第二对晶体管共享的偏置电流。增加的偏置电流减少差分比较器从元稳定状态转变到稳定状态所需的时间，从而提高差分比较器的误码率。电阻元件可以使用线性电阻或传输门。第一或第二对晶体管的栅极可以提供输出。

8. 发明申请

US20050140446A1 Single-ended-to-differential converter with common-mode voltage control 有权
公开(公告)号：US20050140446A1
公开(公告)日：2005-06-30
申请号：US11060395
申请日：2005-02-17
申请人： Jan Mulder , Marcel Lugthart , Chi-Hung Lin
发明人： Jan Mulder , Marcel Lugthart , Chi-Hung Lin
IPC分类号： H03H11/32 , H03F3/45
CPC分类号： H03H11/32
摘要： Provided is a circuit to perform single-ended to differential conversion while providing common-mode voltage control. The circuit includes a converter to convert a single-ended signal to a differential signal and a stabilizing circuit adapted to receive the differential signal. The stabilizing circuit includes a sensor configured to sense a common-mode voltage level of the differential signal and a comparator having an output port coupled to the converter. The comparator is configured to compare the differential signal common-mode voltage level with a reference signal common-mode voltage level and produce an adjusting signal based upon the comparison. The adjusting signal is applied to the converter via the output port and is operative to adjust a subsequent common-mode voltage level of the differential signal.

9. 发明授权

US06771127B2 Single-ended-to-differential converter with common-mode voltage control 有权
标题翻译：具有共模电压控制的单端到差分转换器
公开(公告)号：US06771127B2
公开(公告)日：2004-08-03
申请号：US10105253
申请日：2002-03-26
申请人： Jan Mulder , Marcel Lugthart , Chi-Hung Lin
发明人： Jan Mulder , Marcel Lugthart , Chi-Hung Lin
IPC分类号： H03F345
CPC分类号： H03H11/32
摘要： Provided is a circuit to perform single-ended to differential conversion while providing common-mode voltage control. The circuit includes a converter to convert a single-ended signal to a differential signal and a stabilizing circuit adapted to receive the differential signal. The stabilizing circuit includes a sensor configured to sense a common-mode voltage level of the differential signal and a comparator having an output port coupled to the converter. The comparator is configured to compare the differential signal common-mode voltage level with a reference signal common-mode voltage level and produce an adjusting signal based upon the comparison. The adjusting signal is applied to the converter via the output port and is operative to adjust a subsequent common-mode voltage level of the differential signal.
摘要翻译：提供了在提供共模电压控制的同时执行单端到差分转换的电路。电路包括将单端信号转换为差分信号的转换器和适于接收差分信号的稳定电路。稳定电路包括被配置为感测差分信号的共模电压电平的传感器和具有耦合到转换器的输出端口的比较器。比较器被配置为将差分信号共模电压电平与参考信号共模电压电平进行比较，并且基于该比较产生调整信号。调整信号经由输出端口被施加到转换器，并且可操作地调整差分信号的后续共模电压电平。

10. 发明授权

US06653966B1 Subranging analog to digital converter with multi-phase clock timing 有权
标题翻译：使用多相时钟定时将模数转换器分段
公开(公告)号：US06653966B1
公开(公告)日：2003-11-25
申请号：US10359201
申请日：2003-02-06
申请人： Franciscus Maria Leonardus van der Goes , Jan Mulder , Christopher Michael Ward , Jan Roelof Westra , Rudy van de Plassche , Marcel Lugthart
发明人： Franciscus Maria Leonardus van der Goes , Jan Mulder , Christopher Michael Ward , Jan Roelof Westra , Rudy van de Plassche , Marcel Lugthart
IPC分类号： H03M100
CPC分类号： H03M1/146 , H03K17/04106 , H03M1/204 , H03M1/365
摘要： An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.
摘要翻译： N位模数转换器包括参考梯形图，连接到输入电压的跟踪和保持放大器，在其输入处连接到粗略电容器的粗略ADC放大器，并具有由第一时钟控制的粗略ADC复位开关两相时钟的相位，精细ADC放大器在其输入端连接到精细电容器，并具有由两相时钟的第二时钟相位控制的精细ADC复位开关，开关矩阵从第二时钟相位选择电压子范围参考梯形图，用于基于粗ADC放大器的输出的精细ADC放大器使用，并且其中粗电容器在第一时钟相位期间被充电到粗略的参考梯形电压，并且在第二时钟相位期间连接到T / H输出其中精细电容器在第一时钟相位期间连接到电压子范围，并且在第二时钟相位期间连接到T / H输出;以及编码器，其将粗略和精细ADC放大器的输出转换为Nb 它输出。

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