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1. 发明授权

US07616144B2 Resistor ladder interpolation for PGA and DAC 有权
标题翻译： PGA和DAC的电阻梯形图插补
公开(公告)号：US07616144B2
公开(公告)日：2009-11-10
申请号：US11857417
申请日：2007-09-18
申请人： Jan Mulder , Franciscus Maria Leonardus van der Goes , Jan Westra , Rudy van der Plassche
发明人： Jan Mulder , Franciscus Maria Leonardus van der Goes , Jan Westra , Rudy van der Plassche
IPC分类号： H03M1/78
CPC分类号： H03K17/04106 , H03M1/204 , H03M1/365
摘要： A voltage interpolation circuit includes a resistive ladder connected between ground and a voltage input and having a plurality of resistors with voltage taps between the resistors. An amplifier (optionally) has first and second capacitors connected together at their respective first terminals and to an input of the amplifier. A first plurality of switches connect respective taps to a second terminal of the first capacitor. A second plurality of switches connect the respective taps to a second terminal of the second capacitor. An output voltage is interpolated by controlling the first and second pluralities of switches.
摘要翻译：电压内插电路包括连接在地和电压输入端之间的电阻梯形电阻，并具有多个电阻器，电阻器之间具有电压抽头。放大器（可选地）具有在其相应的第一端子和放大器的输入端连接在一起的第一和第二电容器。第一多个开关将各个抽头连接到第一电容器的第二端子。第二多个开关将各个抽头连接到第二电容器的第二端子。通过控制第一和第二多个开关来内插输出电压。

2. 发明授权

US07482891B2 Interpolating programmable gain attenuator 有权
标题翻译：内插可编程增益衰减器
公开(公告)号：US07482891B2
公开(公告)日：2009-01-27
申请号：US11822652
申请日：2007-07-09
申请人： Jan R. Westra , Jan Mulder , Franciscus Maria Leonardus van der Goes
发明人： Jan R. Westra , Jan Mulder , Franciscus Maria Leonardus van der Goes
IPC分类号： H03H7/24
CPC分类号： H03H11/245 , H03H7/24
摘要： A programmable gain attenuator includes a termination resistor. A first termination switch connects one side of the termination resistor to a first output. A second termination switch connects another side of the termination resistor to a second output. A first resistor ladder is arranged between a first input and the first side of the termination resistor. A first plurality of switches connect a corresponding tap from the first resistor ladder to the first output. A second resistor ladder is arranged between a second input and the second side of the termination resistor. A second plurality of switches connect a corresponding tap from the second resistor ladder to the second output. A first switch of the first plurality of switches is turned on, followed by a second switch of first plurality of switches turned off, followed by a third switch of first plurality of switches turned on. A first switch of the second plurality of switches is turned on, followed by a second switch of second plurality of switches turned off, followed by a third switch of second plurality of switches turned on.
摘要翻译：可编程增益衰减器包括终端电阻。第一终端开关将终端电阻器的一侧连接到第一输出。第二终端开关将终端电阻器的另一侧连接到第二输出端。在第一输入和终端电阻的第一侧之间布置第一电阻梯。第一多个开关将来自第一电阻梯的相应抽头连接到第一输出。在第二输入端和终端电阻器的第二侧之间布置第二电阻梯。第二多个开关将来自第二电阻梯的相应抽头连接到第二输出。第一多个开关的第一开关被接通，接着是第一多个开关的第二开关被关闭，随后开启第一组开关的第三开关。第二多个开关的第一开关被接通，随后是第二多个开关的第二开关被关闭，随后是第二多个开关的第三开关导通。

3. 发明授权

US07242267B2 Interpolating programmable gain attenuator 有权
标题翻译：内插可编程增益衰减器
公开(公告)号：US07242267B2
公开(公告)日：2007-07-10
申请号：US10830112
申请日：2004-04-23
申请人： Jan R. Westra , Jan Mulder , Franciscus Maria Leonardus van der Goes
发明人： Jan R. Westra , Jan Mulder , Franciscus Maria Leonardus van der Goes
IPC分类号： H03H7/24
CPC分类号： H03H11/245 , H03H7/24
摘要： A programmable gain attenuator includes a termination resistor. A first termination switch connects one side of the termination resistor to a first output. A second termination switch connects another side of the termination resistor to a second output. A first resistor ladder is arranged between a first input and the first side of the termination resistor. A first plurality of switches connect a corresponding tap from the first resistor ladder to the first output. A second resistor ladder is arranged between a second input and the second side of the termination resistor. A second plurality of switches connect a corresponding tap from the second resistor ladder to the second output. A first switch of the first plurality of switches is turned on, followed by a second switch of first plurality of switches turned off, followed by a third switch of first plurality of switches turned on. A first switch of the second plurality of switches is turned on, followed by a second switch of second plurality of switches turned off, followed by a third switch of second plurality of switches turned on.
摘要翻译：可编程增益衰减器包括终端电阻。第一终端开关将终端电阻器的一侧连接到第一输出。第二终端开关将终端电阻器的另一侧连接到第二输出端。在第一输入和终端电阻的第一侧之间布置第一电阻梯。第一多个开关将来自第一电阻梯的相应抽头连接到第一输出。在第二输入端和终端电阻器的第二侧之间布置第二电阻梯。第二多个开关将来自第二电阻梯的相应抽头连接到第二输出。第一多个开关的第一开关被接通，接着是第一多个开关的第二开关被关闭，随后开启第一组开关的第三开关。第二多个开关的第一开关被接通，随后是第二多个开关的第二开关被关闭，随后是第二多个开关的第三开关导通。

4. 发明授权

US07019679B2 Multiplexer with low parasitic capacitance effects 有权
标题翻译：具有低寄生电容效应的多路复用器
公开(公告)号：US07019679B2
公开(公告)日：2006-03-28
申请号：US10953420
申请日：2004-09-30
申请人： Jan Mulder , Franciscus Maria Leonardus van der Goes
发明人： Jan Mulder , Franciscus Maria Leonardus van der Goes
IPC分类号： H03M1/34
CPC分类号： H03K17/002 , H03K17/145 , H03M1/36 , H03M1/365
摘要： A differential multiplexer includes a plurality of multiplexing circuits. Each multiplexing circuit inputs a corresponding differential input signal including a positive input signal and a negative input signal, and outputs positive and negative output signals. Each multiplexing circuit includes first, second, third and fourth transistors. The first and second transistors input the positive input signal. The third and fourth transistors input the negative input signal. Outputs of the first and third transistors are connected to the positive output signal. Outputs of the second and fourth transistors are connected to the negative output signal. The positive and negative output signals are controlled using gate voltages on the first and fourth transistors. The second and third transistors are turned off when the differential multiplexer is in use. The transistors are cross-coupled to make leakage between the positive and negative input signals common mode in the positive and negative output signals.
摘要翻译：差分多路复用器包括多个复用电路。每个复用电路输入包括正输入信号和负输入信号的对应差分输入信号，并输出正和负输出信号。每个复用电路包括第一，第二，第三和第四晶体管。第一和第二晶体管输入正输入信号。第三和第四晶体管输入负输入信号。第一和第三晶体管的输出端连接到正输出信号。第二和第四晶体管的输出端连接到负输出信号。正和负输出信号通过第一和第四晶体管上的栅极电压来控制。当使用差分多路复用器时，第二和第三晶体管截止。晶体管交叉耦合以在正输入信号和负输出信号中的正输入信号和负输入信号共模之间产生泄漏。

5. 发明授权

US06583747B1 Subranging analog to digital converter with multi-phase clock timing 失效
公开(公告)号：US06583747B1
公开(公告)日：2003-06-24
申请号：US10158773
申请日：2002-05-31
申请人： Franciscus Maria Leonardus van der Goes , Jan Mulder , Christopher Michael Ward , Jan Roelof Westra , Rudy van de Plassche , Marcel Lugthart
发明人： Franciscus Maria Leonardus van der Goes , Jan Mulder , Christopher Michael Ward , Jan Roelof Westra , Rudy van de Plassche , Marcel Lugthart
IPC分类号： H03M112
CPC分类号： H03M1/146 , H03K17/04106 , H03M1/204 , H03M1/365
摘要： An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.

6. 发明授权

US07551035B2 Fast converter for crossing voltage domains 有权
标题翻译：用于交叉电压域的快速转换器
公开(公告)号：US07551035B2
公开(公告)日：2009-06-23
申请号：US11508966
申请日：2006-08-24
申请人： Jan Roelof Westra , Franciscus Maria Leonardus van der Goes , Erol Arslan
发明人： Jan Roelof Westra , Franciscus Maria Leonardus van der Goes , Erol Arslan
IPC分类号： H03F3/04
CPC分类号： H03F3/343
摘要： A voltage domain crossing circuit and method are disclosed. In one embodiment, the voltage domain crossing circuit comprises an AC coupling component, a DC biasing component and a high voltage output amplifier. The AC coupling component receives an input low voltage signal and AC couples and splits the signal into two voltages. The two voltages are then DC biased to a predetermined bias voltage using the DC biasing component. The high voltage output amplifier then amplifies the biased voltages in the high voltage domain yielding a signal in the high voltage domain. Other embodiments of the voltage domain crossing circuit and method are also disclosed.
摘要翻译：公开了一种电压域交叉电路和方法。在一个实施例中，电压域交叉电路包括AC耦合部件，DC偏置部件和高压输出放大器。 AC耦合组件接收输入低电压信号，并且AC将信号分离成两个电压。然后使用DC偏置组件将两个电压直流偏置到预定的偏置电压。然后，高电压输出放大器放大高电压域中的偏置电压，产生高电压域中的信号。还公开了电压域交叉电路和方法的其他实施例。

7. 发明授权

US07262639B2 High-speed comparator 有权
标题翻译：高速比较器
公开(公告)号：US07262639B2
公开(公告)日：2007-08-28
申请号：US11038388
申请日：2005-01-21
申请人： Jan Mulder , Franciscus Maria Leonardus van der Goes , Marcel Lugthart
发明人： Jan Mulder , Franciscus Maria Leonardus van der Goes , Marcel Lugthart
IPC分类号： H03K5/22
CPC分类号： G01R19/16519 , G01R19/16557 , H03K3/356139 , H03K5/2481 , H03K5/249 , H03M1/0604
摘要： A differential comparator with improved bit-error rate performance operating with a low supply voltage. The differential comparator includes a first pair of transistors receiving a differential input. A second pair of transistors is coupled to the first pair of transistors. A pair of resistive elements is connected between the first pair and second pair of transistors so as to increase bias currents shared by the first and second pairs of transistors. The increased bias currents reduce a time required by the differential comparator to transition from a meta-stable state to a stable state, thereby improving a bit-error rate of the differential comparator. The resistive elements can use linear resistors or transmission gates. Gates of either the first or second pair of transistors can provide an output.
摘要翻译：差分比较器，具有更低的电源电压，具有改进的误码率性能。差分比较器包括接收差分输入的第一对晶体管。第二对晶体管耦合到第一对晶体管。一对电阻元件连接在第一对和第二对晶体管之间，以增加由第一和第二对晶体管共享的偏置电流。增加的偏置电流减少差分比较器从元稳定状态转变到稳定状态所需的时间，从而提高差分比较器的误码率。电阻元件可以使用线性电阻或传输门。第一或第二对晶体管的栅极可以提供输出。

8. 发明申请

US20070182605A1 Fast converter for crossing voltage domains 有权
标题翻译：用于交叉电压域的快速转换器
公开(公告)号：US20070182605A1
公开(公告)日：2007-08-09
申请号：US11508966
申请日：2006-08-24
申请人： Jan Roelof Westra , Franciscus Maria Leonardus van der Goes , Erol Arslan
发明人： Jan Roelof Westra , Franciscus Maria Leonardus van der Goes , Erol Arslan
IPC分类号： H03M1/06
CPC分类号： H03F3/343
摘要： A voltage domain crossing circuit and method are disclosed. In one embodiment, the voltage domain crossing circuit comprises an AC coupling component, a DC biasing component and a high voltage output amplifier. The AC coupling component receives an input low voltage signal and AC couples and splits the signal into two voltages. The two voltages are then DC biased to a predetermined bias voltage using the DC biasing component. The high voltage output amplifier then amplifies the biased voltages in the high voltage domain yielding a signal in the high voltage domain. Other embodiments of the voltage domain crossing circuit and method are also disclosed.
摘要翻译：公开了一种电压域交叉电路和方法。在一个实施例中，电压域交叉电路包括AC耦合部件，DC偏置部件和高压输出放大器。 AC耦合组件接收输入低电压信号，并且AC将信号分离成两个电压。然后使用DC偏置组件将两个电压直流偏置到预定的偏置电压。然后，高电压输出放大器放大高电压域中的偏置电压，产生高电压域中的信号。还公开了电压域交叉电路和方法的其他实施例。

9. 发明授权

US06653966B1 Subranging analog to digital converter with multi-phase clock timing 有权
标题翻译：使用多相时钟定时将模数转换器分段
公开(公告)号：US06653966B1
公开(公告)日：2003-11-25
申请号：US10359201
申请日：2003-02-06
申请人： Franciscus Maria Leonardus van der Goes , Jan Mulder , Christopher Michael Ward , Jan Roelof Westra , Rudy van de Plassche , Marcel Lugthart
发明人： Franciscus Maria Leonardus van der Goes , Jan Mulder , Christopher Michael Ward , Jan Roelof Westra , Rudy van de Plassche , Marcel Lugthart
IPC分类号： H03M100
CPC分类号： H03M1/146 , H03K17/04106 , H03M1/204 , H03M1/365
摘要： An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.
摘要翻译： N位模数转换器包括参考梯形图，连接到输入电压的跟踪和保持放大器，在其输入处连接到粗略电容器的粗略ADC放大器，并具有由第一时钟控制的粗略ADC复位开关两相时钟的相位，精细ADC放大器在其输入端连接到精细电容器，并具有由两相时钟的第二时钟相位控制的精细ADC复位开关，开关矩阵从第二时钟相位选择电压子范围参考梯形图，用于基于粗ADC放大器的输出的精细ADC放大器使用，并且其中粗电容器在第一时钟相位期间被充电到粗略的参考梯形电压，并且在第二时钟相位期间连接到T / H输出其中精细电容器在第一时钟相位期间连接到电压子范围，并且在第二时钟相位期间连接到T / H输出;以及编码器，其将粗略和精细ADC放大器的输出转换为Nb 它输出。

10. 发明授权

US07324038B2 Subranging analog to digital converter with multi-phase clock timing 有权
标题翻译：使用多相时钟定时将模数转换器分段
公开(公告)号：US07324038B2
公开(公告)日：2008-01-29
申请号：US10625702
申请日：2003-07-24
申请人： Franciscus Maria Leonardus van der Goes , Jan Mulder , Christopher Michael Ward , Jan Roelof Westra , Ruby van de Plassche , Marcel Lugthart
发明人： Franciscus Maria Leonardus van der Goes , Jan Mulder , Christopher Michael Ward , Jan Roelof Westra , Ruby van de Plassche , Marcel Lugthart
IPC分类号： H03M1/12
CPC分类号： H03M1/146 , H03K17/04106 , H03M1/204 , H03M1/365
摘要： An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.
摘要翻译： N位模数转换器包括参考梯形图，连接到输入电压的跟踪和保持放大器，在其输入处连接到粗略电容器的粗略ADC放大器，并具有由第一时钟控制的粗略ADC复位开关两相时钟的相位，精细ADC放大器在其输入端连接到精细电容器，并具有由两相时钟的第二时钟相位控制的精细ADC复位开关，开关矩阵从第二时钟相位选择电压子范围参考梯形图，用于基于粗ADC放大器的输出的精细ADC放大器使用，并且其中粗电容器在第一时钟相位期间被充电到粗略的参考梯形电压，并且在第二时钟相位期间连接到T / H输出其中精细电容器在第一时钟相位期间连接到电压子范围，并且在第二时钟相位期间连接到T / H输出;以及编码器，其将粗略和精细ADC放大器的输出转换为Nb 它输出。

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